1Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 2University of ... technologies and the high levels of process variation further.
Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 2University of California, Los Angeles
Abstract —Deep sub-micron scaled CMOS offers relatively low RF performance at mm-wave frequencies compared with III-V technologies and the high levels of process variation further exacerbate design margins and lesser performance. Instead of optimizing mm-wave circuits for performance at design time, we instead adopt a “maximum tune-ability” approach in which the mm-wave front-end circuitry is made highly tunable and optimized at run-time by digital control and optimization algorithms to overcome process variation effects.
process variation. The design was fabricated on two different wafer runs spaced 6 months apart and 10 chips were selected from each run for a total of 20 chips. Using a setup similar to the one discussed in [3], the center frequency and output power of each chip was measured at the same supply and bias conditions for each chip.
Index Terms — millimeter-wave calibration, mm-wave optimization
I. INTRODUCTION Recent advances in silicon technology have enabled the possibility of constructing CMOS based Gb/s communication systems beyond the 50 GHz frequency range. Design of RF front-ends at mm-wave carriers (100 GHz) and beyond is a relatively new topic with most emphasis placed on the circuit design aspects. One major challenge of mm-wave front-ends operating at frequencies beyond 100 GHz is that the stage gain for power amplifiers is quite low [1,2,3], typically only 3-6 dB of gain per stage. This low available gain makes the front-end extremely sensitive to the effects of process variation as a small change in the CMOS device parameters may drastically reduce the front-end performance. To illustrate this we first constructed the simple circuit shown in Fig. 1, where a 140 GHz oscillator is coupled directly to a power amplifier, also optimally centered at 140 GHz (D-Band).
Fig. 2. Measured center frequency of 20 D-band oscillator-PA chips from two different fabrication runs.
Figure 2 and 3 plot the output frequency and power measured from the 20 chips respectively. As the frequency spread is quite large (135.9 GHz < f
