CMOS output stages for low-voltage power supplies - IEEE Xplore

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Abstract—Compact and power-efficient CMOS output stages are presented and compared by designing two low-voltage operational amplifiers with similar gain ...
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CMOS Output Stages for Low-Voltage Power Supplies G. Palmisano, Associate Member, IEEE, G. Palumbo, and R. Salerno

Abstract—Compact and power-efficient CMOS output stages are presented and compared by designing two low-voltage operational amplifiers with similar gain and gain-bandwidth performance. The amplifiers were realized in a standard 1.2-µm CMOS process with threshold voltages around 0.8 V and using a 1.5-V power supply. They achieve an open-loop gain and a gain-bandwidth product close to 65 dB and 1 MHz, respectively. By connecting them in unity-gain configuration and delivering a 1-V peak-to-peak output voltage into a 500 and 50 pF load, total harmonic distortions of −77 and −67 dB can be achieved, while using quiescent currents as low as 50 µA in the output branches.



Index Terms—Amplifier, CMOS, low-voltage.

I. INTRODUCTION

D

ESIGN OF IC’s operating from low supply voltages is gaining more and more importance for applications outside traditional areas where low power dissipation is mandatory [1]–[5]. Indeed, low consumption is a also key design aspect in modern portable equipment, since battery lifetime must be increased. In addition, low consumption increases both packing density and circuit reliability. The best way to cut down power consumption is to reduce both the power-supply voltage and current. Unfortunately, due to the fundamental dependence of transistor noise on the quiescent current, no appreciable reduction of the supply current can usually be achieved for some high-performance analog blocks. Therefore, the only way to reduce power consumption is by reducing the supply voltage. Typical supply voltages for today’s analog circuits are around 2.5–3 V, while future trends suggest supply voltages of 1.5 V or even less [6]–[8]. With these very low supply values, traditional CMOS solutions cannot be adopted, unless processes with low threshold voltages are used. However, great efforts have been devoted to implementing new low-voltage circuits with standard CMOS processes [9]–[20], since low threshold voltage processes have various drawbacks including high leakage currents. One fundamental circuit in most analog IC’s is the operational amplifier (opamp). This circuit, unlike the transconductance amplifier, includes an output stage capable of driving off-chip low load resistances. Drive capability, linearity, and output swing are mainly (or almost completely) set by the output stage [21]–[26], which is the most critical block in the Manuscript received February 1999; revised September 1999. This work was supported by the applied research project of CNR “Microelectronics.” This paper was recommended by Associate Editor J. Silva Martinez. The authors are with DEES (Dipartimento Elettrico Elettronico e Sistemistico), Universita’ di Catania, I-95125 Catania, Italy. Publisher Item Identifier S 1057-7130(00)01461-0.

design of low-voltage opamps [27]–[33]. Unfortunately, while output swing can in principle be guaranteed using complementary common source transistors, adequate overdrive for the output transistors and accurate bias-current control are very hard to achieve with standard CMOS technologies at 1.5 V. In this paper, two high-efficiency output stages providing rail-to rail output swing and high output current are presented. One is a symmetric class-AB stage [34], [35], and the other is an asymmetric class-AB stage [25]. In order to compare their performance, they were included in operational amplifiers with a 1.5-V power supply, realized in a standard 1.2-µm CMOS process with threshold voltages around 0.8 V. To save input swing, the two opamps have the same input stage arranged with a folded-mirror active load. Their die area and power dissipation are 0.08 µm2 and less than 300 µW, respectively. The output stages are capable of driving an output load of 500 in parallel to 50 pF providing a 1-V peak-to-peak output voltage and a total harmonic distortion (THD) of about −77 and −67 dB, respectively. We present the two output stages in Sections II and III and the overall opamps in Section IV. In Section V, we discuss the measurement results and, finally, in Section VI, we make conclusions and remarks. II. THE SYMMETRIC CLASS-AB OUTPUT STAGE The first output stage is shown in Fig. 1(a). It is based on a novel solution which provides the drive capability of a simple inverter stage (i.e., with the same peak-to-peak output swing and an overdrive limited by only two saturation voltages), and uses a simple and accurate current control. High linearity for low input level is also achieved. A. Circuit Behavior The circuit can be divided into an input and an output section. The input section is made up of transistors M1A–M4A and Transistors M1A and M2A and current generators have equal aspect ratios and drive the diode-connected transistors M3A and M4A, respectively. The output section is implemented by two inverters, M5A–M6A and M7A–M8A, which have a common output. Using a supply voltage lower than two threshold voltages, each inverter has one transistor in saturation (M5A, M8A) and the other in cutoff (M6A, M7A). The currents and in M8A, are mirrored from M3A and in M5A, M4A, respectively. For low input levels, M6A and M7A are in cutoff region and the circuit performs a class-A operation with high linearity. Indeed, the currents in the output transistors M5A and M8A are

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B. Current Control In stand-by conditions, the output current is equal to zero and current is forced to be equal to Setting

(1)

current

is equal to current

or, in other words, (2)

(a)

Since

it follows that (3)

and, hence, the bias current in M5A and Thus, current and M8A are accurately set by current generators C. Harmonic Distortion

(b) Fig. 1. Symmetric class-AB output stage. (a) Detailed schematic. (b) Simplified schematic.

provided by M1A and M2A through the diode-connected transistors M3A and M4A, respectively. As the input level increases, for example in the positive diequals transistors M3A and M5A rection, current turn off and node A, which becomes a high-impedance node, Transistor M6A turns on and delivers is driven close to a high current to the output load. Transistor M7A remains in cutoff and the current in M8A also increases, although its value Hence, most of the is limited by the low impedance at node output current is supplied by transistor M6A, which is in cutoff in the quiescent condition. Similar behavior holds for large negative input signals. In this case, transistors M4A and M8A turn off, node becomes a high-impedance node and is driven by close to Again, most of the output current is hence supplied by M7A, and that like M6A is in the cutoff region in the quiescent condition. Transistors M5A and M8A were designed with low aspect ratios to provide low dc power dissipation. On the other hand, transistors M6A and M7A, which are in the cutoff region in the quiescent condition, were designed with large aspect ratios to achieve high drive capability for large input levels.

Harmonic distortion in class-AB circuits can be evaluated with the approach suggested in [36]. The method gives the second and third-order harmonic distortions as a function of the as well as the output derivative small-signal voltage gain at the highest and lowest extreme of the input variation and respectively. The following harmonic distortion terms results in (4a)

(4b) Since the harmonic distortion comes mainly from the output transistors, the simplified circuit in Fig. 1(b) can be used to evaluate it. By setting (see Appendix) the gain factors of complementary transistors to equal and assuming ideal matching bein tween transistors of the same type (i.e., Appendix A), we get (5a) and (5b), shown at the bottom of the page, where is the ratio of the large area transistors (M6A, M7A) to the low area transistors (M5A, M8A), that is

(6)

(5b)

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Since the bias currents and the gain factors are equal for both nMOS and pMOS transistors, drain-source saturation voltages and are are also equal, and voltages on nodes and given by (7a)

(7b) Substituting (7) in (5) and assuming equal threshold voltages, the second-order harmonic distortion is equal to zero, as excircuit, and the following pected from a symmetrical classthird-order harmonic distortion results

(a)

(8) The third-order harmonic distortion is linearly related to factor and to the peak value of the input signal Factor sets the ratio of the maximum output current to the bias current, hence creating a tradeoff between drive capability and linearity. A more accurate evaluation of the second-order harmonic distortion can be achieved by considering transistor mismatches. From (4a), (4b), and (A.1)–(A.5) of Appendix A, we get (9), shown at the bottom of the page, where, according to (A.2) and and account for the mismatch between the gain (A.5), factors of complementary transistors and the mismatch between the aspect ratios of M5A to M8A, and M6A to M7A, respectively. It is clear that the dominant contribution is due to the mismatch of the gain factors, which is increased by factor III. THE ASYMMETRIC CLASS-AB OUTPUT STAGE The second output stage is shown in Fig. 2(a). This solution [25] is simpler than the previous one, but, due to its asymmetric topology, we expect a lower linearity performance. A. Circuit Behavior Of the transistors in the output branch, M4B and M5B, one is driven directly by the input, and the other through the noninverting gain stage made up of transistors M1B–M3B and curand which perform a kind of foldedrent generators output stage is mirror amplifier. Thus, an asymmetric classachieved. For low input levels, the output transistors M4B and M5B are both in a saturation region and the circuit performs a classoperation. As the input level increases, for example in the positive direction, and the voltage in the high-impedance node reaches the value transistor M5B turns off and the output current is only supplied by transistor M4B. On the

(b) Fig. 2 Asymmetric class-AB output stage. (a) Detailed schematic. (b) Simplified schematic.

other hand, for large negative input signals, node goes close and M5B delivers the output current. It is clear that the to circuit’s behavior is not symmetrical for positive and negative input voltages. To allow a comparison between the two output stages under similar design conditions, overall quiescent currents and aspect ratios were set as equal in both stages. More precisely, the aspect ratios of transistors M4B and M5B in Fig. 2(a) were set as equal to the sum of the aspect ratios of transistors M5A, M7A and M6A, M8A, in Fig. 1(a), respectively. B. Current Control and the current mirror Due to current generators is given by M2B, M3B, current

(10)

(9)

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(a)

(b) Fig. 3. Low-voltage opamps. (a) Symmetric class-AB output stage. (b) Asymmetric class-AB output stage.

In stand-by condition, current are given by

is equal to

and both

where is the equivalent resistance at node approach in Appendix B, we get

Following the

(13) (11)

Assuming the threshold voltages and gain factors of complementary transistors to be equal, (13) can be written as

By using (10) and (11), the bias currents in the output stage can be set accurately. C. Harmonic Distortion Due to the asymmetry of the output stage in Fig. 2(a), we expect the second-order harmonic distortion to be much higher than the third one. Therefore, we apply the method described in Appendix B [37]. To this purpose, the output stage in Fig. 2(a) can be simplified as shown in Fig. 2(b). Parameter G is the small-signal gain of the folded-mirror amplifier (M1B–M3B) and is given by

(12)

(14) By comparing the dominant harmonic distortions of the cirfrom (8) and from (13), we cuits in Figs. 1 and 2, i.e., output stage to be expect the THD in the symmetric classoutput 10-dB better than the THD of the asymmetric classstage for a 1-V peak-to-peak output signal. IV. OVERALL OPAMPS Two opamps were designed using the output stages previously discussed. Their schematics are shown in Fig. 3(a) and (b) for the symmetric and the asymmetric output stage, respectively. To increase their common mode input range (CMR), both opamps use the same input stage, i.e., a differential transconductance amplifier with a folded-mirror active load (M1–M7). The intermediate stage is instead arranged in

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TABLE I TRANSISTOR ASPECT RATIOS

TABLE II COMPENSATION CAPACITORS

a different fashion for each opamp. It is a simple common source amplifier (M8–M9), in Fig. 3(a), and a noninverting folded-mirror amplifier (M17–M21), in Fig. 3(b). Non-inverting gain is required for frequency compensation purposes. Neglecting bulk effects and assuming equal saturation voltages, the CMR is CMR

(a)

(15)

It does not depend on the power supply and lies in the range 0.3–0.5 V. To guarantee stability in a closed-loop configuration, a hybrid nested Miller compensation was used [38]–[42]. The external equal to and for the first and loop capacitor second opamp, respectively, and the equivalent resistance at the set the dominant pole output of the input stage (16) is the open-loop gain of the inner amplifier, which where includes the intermediate and the output stage. The gain-bandwidth product is hence given by (17) At frequencies as high as the gain-bandwidth product, capacitor can be considered short-circuited and the nondominant poles to be those of the inner amplifier in unity-gain feedback. We set the compensation capacitances to provide a maximally flat Butterworth response [42]. To avoid right half-plane zeros, triode-biased transistors were used. V. EXPERIMENTAL RESULTS The circuits were fabricated in a standard 1.2-µm CMOS process with threshold voltages of around 0.8 V for both pMOS and nMOS transistors. To allow comparison between the two output stages under similar operating conditions, gain, gainbandwidth, and power dissipation were set equally in both amand the power supply were set to 5 µA plifiers. Current

(b) Fig. 4. Frequency response of the opamp with the symmetric class-AB output stage. (a) Module. (b) Phase.

and 1.5 V, respectively. Transistor aspect ratios and compensation capacitors are reported in Tables I and II, respectively. The measurements were carried out by loading the output of both opamps with 50 pF in parallel to 500 . The frequency responses are shown in Figs. 4 and 5 for the first and second opamp, respectively. The first opamp has a 68-dB dc gain and 1-MHz gain-bandwidth product with a phase margin equal to 65 . The second opamp has a 63-dB dc gain and 0.95-MHz gain-bandwidth product with a phase margin equal to 60 . By setting the closed-loop gain to 20 dB and using a 1-kHz input signal, the curves of the harmonic distortion versus the output voltage in

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(a)

Fig. 6.

HD with a 500- load.

Fig. 7.

HD with a 300- load.

(b) Fig. 5. Frequency response of the opamp with the asymmetric class-AB output stage. (a) Module. (b) Phase.

Fig. 6 were found. The worst THD’s are better than −53 and −47 dB, up to a 1-V peak-to-peak output voltage. After extrapolating these results for a unity-gain configuration, THD’s better than −73 and −67 dB are achieved. According to the analysis in Section II, the dominant nonlinearity in the opamp using the output dB in the stage in Fig. 1(a) comes from HD3, which varies by a overall output range. The expected values of HD3 from (8) range from −66 to −59 and agree well with the experimental ones. For the opamp in Fig. 3(b), which uses the output stage in Fig. 2(a), the dominant nonlinearity comes from HD2, which is around −51 dB (the expected value from (14) is −52 dB). It dB and is 10-dB higher than in HD3. varies by The circuits were also tested with a load resistance of 300- . HD’s versus the output voltage are shown in Fig. 7. The worst THD’s are 3-dB and 14-dB higher than in the previous case (i.e., 500 ) for the first and second opamp, respectively. Finally, we see that for low output voltages harmonic distortion is very similar in both opamps. For high output voltages (greater than 0.8 V and 0.6 V in Figs. 6 and 7, respectively), the THD of the opamp in Fig. 3(b) becomes higher due to the dominant contribution of HD2 which is caused by the asymmetric output stage.

The main measured performance parameters are summarized in Table III. The chip photos are shown in Fig. 8. VI. CONCLUSION Two power-efficient CMOS output stages for low-voltage operational amplifiers have been discussed and compared experimentally. In addition, design equations for current control and a detailed analysis of nonlinearity have been provided for the two output stages. They were used in two tree-stage operational amplifiers designed with the same main electrical parameters to ensure proper comparison. Several experimental measurements were carried out on integrated samples which were fabricated in a 1.2-µm standard CMOS process. Using overall transistor aspect ratios of 150/1.2 and 450/1.2 for the nMOS and pMOS output stage transistors, respectively, the symmetric class-AB output stage was capable of driving an output load of 300 in parallel to 50 pF, while providing a better than −73 dB THD in unity-gain configuration with a higher

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where and are the bias voltages at nodes and reis the mismatch of the gain factor bespectively, and term tween the nMOS and pMOS transistors, given by

TABLE III MEASURED MAIN PERFORMANCE

(A.2)

When the input signal is high, transistor M6A and M8A are switched off, and the derivative of the output signal evaluated at the positive peak of the input signal is

(A.3) is the peak amplitude of the input where signal, and term is given by (6). When the input signal is low, transistors M5A and M7A are switched off, and the derivative of the output signal at the negative input peak becomes

(a)

(A.4) (b)

where parameter

is defined by

Fig. 8. Chip photos. (a) Opamp in Fig. 3(a). (b) Opamp in Fig. 3(b).

than 0.9-V peak-to-peak output voltage. In similar signal conditions, the asymmetric class-AB output stage provides a THD of −53 dB.

APPENDIX A HARMONIC DISTORTION IN THE SYMMETRIC OUTPUT STAGE Let us consider the simplified circuit in Fig. 1(b). The smallis given by signal voltage gain,

(A.5)

APPENDIX B HARMONIC DISTORTION IN THE ASYMMETRIC OUTPUT STAGE Again, consider the simplified circuit in Fig. 2(b) and a siand assume an ideal nusoidal input signal with amplitude class- operation. The circuit has different transconductance gains, and for the two half waves, which are given by (B.1a)

(A.1)

(B.1b)

PALMISANO et al.: CMOS OUTPUT STAGES FOR LOW-VOLTAGE POWER SUPPLIES

Hence, current

and

can be expressed as for (B.2a) for

for (B.2b) for and By expanding the first two terms, we get

in Fourier series and considering

(B.3) from (B.2), we find that the secondSince order harmonic distortion of the output voltage is given by (B.4)

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G. Palmisano (A’98) was born in Lampedusa, Italy, in 1956. He received the Laurea degree in electronics engineering from the University of Pavia, Pavia, Italy, in 1982. From 1983 to 1991, he was with the Department of Electronics, University of Pavia, involved in researching CMOS and BiCMOS analog integrated circuits. In 1992, he was a Visiting Professor at the Universidad Autonoma Metropolitana, Mexico City, teaching a course on microelectronics to doctoral students. In 1993, he joined the Faculty of Engineering, University of Catania, Catania, Italy, as an Associate Professor of Microelectronics. Since 1995, he has been a Consultant for STMicroelectronics, Catania, Italy, involved in the design of RF integrated circuits for portable communications equipment. He has designed several innovative analog circuits, such as operational amplifiers, switched-capacitor filters, and A/D and D/A converters, within the framework of national and European research projects, in addition to several integrated circuits for both the baseband and RF front-end of mobile communicatioins systems within research collaborations with electronics industries. His current research interests include current-mode analog circuits, low-voltage cmplifiers, and building blocks for integrated RF transceivers.

G. Palumbo, photograph and biography not available at time of publication.

R. Salerno was born in Dolceaqua, Italy, in 1970. He received the Laurea degree in electronics engineering from the University of Catania, Catania, Italy, in 1995, where he has been working toward the Ph.D. degree in electronics engineering since 1997. In 1996, he was with STMicroelectronics, Catania, involved in researching low-noise amplifiers and image-rejection mixers for RF front-ends. His current research interests include low-voltage amplifiers and building blocks for integrated transceivers.