Compact Model of Memristors and Its Application in Computing Systems Hai (Helen) Li and Miao Hu Department of Electrical and Computer Engineering Polytechnic Institute of New York University 6 MetroTech Center, Brooklyn, NY, USA
[email protected] Abstract—In this paper, we present a compact model of the spintronic memristor based on the magnetic-domain-wall motion mechanism for circuit design. Our model also takes into account the variations of material parameters and fabrication process, which significantly affects the actual electrical characteristics of a memristor in nano-scale technologies. Our proposed model can be easily implemented by Verilog-A languages and compatible to SPICE-based simulation. Based on our model, we also show some potential applications of memristor in computing system, including the detailed analysis and optimizations based on our proposed model. Keywords-Memristor, spin torque, spintronic, magnetic tunneling junction (MTJ), compact model
I.
INTRODUCTION
In the circuit theory before 1971, there were only three fundamental passive circuit elements – resistor, capacitor and inductor. Professor Chua observed its incompleteness and predicted the existence of memristor, the fourth basic circuit element which can build the bridge between the magnetic flux ϕ and the electronic charge q [1]. In 2008 – 37 years after Professor Chua’s prediction, the first experimental realization of memristor was demonstrated in a solid-state thin film twoterminal device by HP Labs [2]. The memristive effect was achieved by moving the doping front along the device [2]. Beside the solid-state device, magnetic technology provides other possible solutions to build a memristive system [3, 4]. Three spintronic memristor structures have been proposed in [3]. They are spin valve with spin-torque-induced domain-wall motion in the free layer, MTJ (magnetic tunneling junction) with spin-torque-induced magnetization switching, and thinfilm element with spin-torque-induced domain-wall motion. Compared to the solid-state thin film device [2], the behavior of a spintronic memristor, e.g., the relationship between the memristance and the current through the memristor, can be controlled more flexibly. Also, the technology to integrate magnetic device on the top of CMOS device has become mature in the development of magnetic memory [5]. Memristors have many unique properties, such as simple physical structure, high-density, non-volatility, historic behavior, low power consumption and good scalability [6]. The non-volatile nature and the good scalability (down to 10nm and below with an integration density of 100Gbits/cm2) of
978-3-9810801-6-2/DATE10 © 2010 EDAA
memristor make it an attractive candidate for the nextgeneration memory technology [6]. Because it can record the historic behavior of the current through it, memristor is expected to have a great potential in electronic neutral network [7, 8]. Applications in analog circuitries, such as Op-Amp and UWB receiver, have also been investigated recently [9-11]. Beside the researches at material level and application levels, memristor models based on piecewise line approximation were proposed by Wang [12] and Zhang [13] recently. A compact model for spintronic memristor was also proposed by Chen [14]. As process technology scales down, device parameter fluctuation incurred by process variations has become an critical issue to affecting device characteristic [15]. For example, two memristors with identical designs could have quite different memristances even if they are close to each other physically. Although the spintronic memristor model in [14] discussed the design corner and device mismatch by considering the variations of the key electrical properties, the impact of the diverse process variations on those electrical properties was not evaluated. In this paper, we will bridge the gap between the parameters of the compact model of spintronic memristor and their implication to the circuit design by taking into account the impacts of process variations. Among all the related process variations, line-edge roughness (LER) has been proved as one of the key sources of device variations at sub-45nm technology node [16]. LER is caused by the random uncertainties in the process of lithograph and etching, and causes the random deviation of line edge print-images from its ideal pattern [17]. Due to the fundamental problems with the molecular structure of the photoresist, LER does not decrease as the geometry dimension of devices shrinks. Because spintronic memristor is implemented on the basis of thin-film deposition technology, random discrete doping (RDD) could also result in the variations of material parameters, such as domain wall velocity coefficient Γv, the hard anisotropy in the direction perpendicular to the thin film plan Hp, and the easy anisotropy in the strip direction Hk. Our compact model, which considers all above process variations, can be easily implemented by Verilog-A language. It can be easily embedded in SPICE-based simulators in the
circuit design. Our spintronic memristor compact model substantially improves simulation efficiency without scarifying the simulation accuracy. The rest of our paper is organized as follows: Section II provides the fundamentals of memristor and spintronic memristor; Section III briefly explains the compact model proposed in [14]; Section IV discusses the impact of process variations on the electrical properties of spintronic memristor; Section V concludes our paper. II.
(a)
PRELIMINARIES
A. Memristor Theory The original definition of memristors is derived from the logic completeness of circuit theory [1, 18]. It is defined as a two-terminal element in which the magnetic flux ϕ between the terminals is a function of the amount of electric charge q that can pass through the device. Hence, memristance M can be explicitly expressed by the equation (1)
𝑑𝑑𝑑𝑑 = 𝑀𝑀 ∙ 𝑑𝑑𝑑𝑑.
By doing a simple transformation of Eq. (1), memristance can be expressed as: 𝑀𝑀(𝑞𝑞) =
𝑑𝑑𝑑𝑑 � 𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑 � 𝑑𝑑𝑑𝑑
=
𝑉𝑉 𝐼𝐼
.
(2)
The unit of memristance is actually Ω, which is the same as the unit of resistance. The difference between a memristor and a resistor is that the memristance of a memristor is a function of charge q, which varies over time [19]. B. Spintronic Memristor Among all spintronic memristive structures proposed in [3], the spin valve memristor with spin-torque-induced domainwall motion could be the most promising one for its simplest structure. In fact, the fabrication process of such spintronic memristors is similar to the mature technology that was used to manufacture the spin valve based GMR (Giant Magnetoresistance) head in a hard disk drive [20]. Hence, we choose it as the objective of this research work. Figure 1(a) illustrates the structure of the spin-torqueinduced domain-wall motion based memristor [14]. Its basic structure is a long spin-valve strip, which consists of two ferromagnetic layers called reference layer and free layer, respectively. The magnetization direction of reference layer is fixed all the time by coupling to a pinned magnetic layer (called pin layer). The free layer is divided into two segments by a domain-wall: one segment has the parallel magnetization direction to the reference layer, while another segment’s magnetization direction is anti-parallel to the reference layer. The domain wall in the free layer could be moved by the spinpolarized current. The resistance per unit length of each segment is determined by the relative magnetic directions of free layer and reference layer: when the magnetization direction of the free layer in a segment is parallel (anti-parallel) to the reference layer, the resistance per unit length of the segment is at its low (high) state. We could use rL and rH to denote the
(b) Figure 1. A spintronic memristor based on spin valve magneticdomain-wall motion. (a) Structure. (b) Equivalent circuit.
value of the resistance per unit length when the segment of spin-valve strip is at its low- or high-resistance states, respectively. Figure 1(b) shows the simplified equivalent circuit model of the spin-torque-induced domain-wall motion based memristor. The memristance of such a spintronic memristor can be expressed as: 𝑀𝑀(𝑥𝑥) = [𝑟𝑟𝐻𝐻 ∙ 𝑥𝑥 + 𝑟𝑟𝐿𝐿 ∙ (𝐷𝐷 − 𝑥𝑥)] = [𝑟𝑟𝐿𝐿 ∙ 𝐷𝐷 + (𝑟𝑟𝐻𝐻 − 𝑟𝑟𝐿𝐿 ) ∙ 𝑥𝑥],
(3)
where x is the position of domain-wall and D is the length of the device, as shown in Fig. 1(a). In Eq. (3), we assume the width of domain wall is negligible compared to the length of the device. Hence, the impact of the domain wall on overall memristance can be ignored. How fast the domain-wall can move mainly relies on the strength of spin-current applied on it. More precisely, the domain-wall velocity v is proportional to the current density J [21], as 𝑣𝑣 =
𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑
= 𝛤𝛤𝑣𝑣 ∙ 𝐽𝐽.
(4)
Here 𝛤𝛤𝑣𝑣 is domain wall velocity coefficient, which is related to device structure and material property.
The domain wall movement in the spintronic memristor happens only when the applied current density (J) is above the critical current density (Jcr) [21-25]. When reading the memristance of a spintronic memristor, a small sensing current (Ird) can be applied to the device. The value of memristance is read out by measuring the voltage drop across the memristor. As long as the read current density Jrd is below Jcr, the state of the spintronic memristor will not be disturbed. It is different from the motion of doping front in the solidstate memristor, which happens whenever there is a current applied on it [6]. In order to overcome the memristance “drift” due to non-zero input flux, some tricky circuit designs, i.e., refreshing scheme [6].
III.
COMPACT MODEL OF SPINTRONIC MEMRISTOR
3) Domain wall position x
A. Compact Model of Spintronic Memristor Chen et al. [14] proposed a compact model of the spin valve memristor with spin-torque-induced domain-wall motion, including three main equations: 1) Memristance at domain wall position x If considering the width of domain wall w and assuming that the resistance per unit length of the thin film strip changes linearly from rL to rH within the domain wall, the overall memristance of such a spintronic memristor can be calculated as: 𝑤𝑤
𝑀𝑀(𝑥𝑥) = �𝑟𝑟𝐻𝐻 ∙ �𝑥𝑥 − 2 � + (𝑟𝑟𝐻𝐻 + 𝑟𝑟𝐿𝐿 ) ∙ = [𝑟𝑟𝐿𝐿 ∙ 𝐷𝐷 + (𝑟𝑟𝐻𝐻 − 𝑟𝑟𝐿𝐿 ) ∙ 𝑥𝑥]
𝑤𝑤 2
𝑤𝑤
+ 𝑟𝑟𝐿𝐿 ∙ �𝐷𝐷 − 𝑥𝑥 − �� 2
,
(5)
0 < 𝑥𝑥 < 𝐷𝐷. Eq. (5) shows that M(x) does not depend on the width of wall w. In fact, such an assumption of the domain wall resistance is close to the physical phenomena and incurs very marginal error in the calculation of memristance [21-25]. 2) Effective current density Jeff The effective current density Jeff of a spintronic memristor can be calculated as: 𝐽𝐽eff = �
𝐽𝐽 =
0,
1
ℎ∙𝑧𝑧
∙
𝑉𝑉
𝑀𝑀(𝑥𝑥)
,
𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝐽𝐽 ≥ 𝐽𝐽cr 𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝐽𝐽 < 𝐽𝐽cr
.
(6a)
Here, we assume that a voltage input V is applied to the spintronic memristor. M(x) is the memristance when domain wall is at position x. h and z are the thickness and the width of spin-valve strip, respectively. If considering a current input I to the spintronic memristor, Jeff becomes to 𝐽𝐽eff = �
TABLE I. e uB Hp Hk Ms A
α P
γ
Jcr D h z ReL GMR
𝐽𝐽 =
0,
𝐼𝐼
ℎ∙𝑧𝑧
,
𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝐽𝐽 ≥ 𝐽𝐽cr 𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝐽𝐽 < 𝐽𝐽cr
.
CONSTANTS AND PARAMETERS IN MODEL
Physical constants Elementary charge (C) 1.602e-19 -1 Bohr magneton (J·T ) 9.274e-24 Materials parameters (typical value) Hard anisotropy (Oe) 5000 Easy anisotropy (Oe) 100 Magnetization saturation (emu/cc) 1010 Exchange parameter (J/m) 1.8e-11 Damping parameter 0.002~0.1 Polarization efficiency 0.35 Gyromagnetic ratio 1.75e7 Critical current density 5·107A/cm2 Model parameters Length (nm) 1000 thickness (Å) 70 Width (nm) 10 50 (when h=70 Å) Low sheet resistance (Ω/ ) Giant magneto resistance ratio 20%
(6b)
The domain wall position x can be calculated by the integral of the domain wall velocity v over time t as: 𝑥𝑥 = ∫0 𝑣𝑣 ∙ 𝑑𝑑𝑡𝑡.
𝑡𝑡
(7)
𝑣𝑣 = 𝛤𝛤v ∙ 𝐽𝐽eff .
(8)
As we explained in Section II-B, the domain wall velocity v is proportional to the current density J and it can move only when J is bigger than Jcr [21-25]. Therefore, v is proportional to the effective current density Jeff: By combining Eq. (7) and (8), the domain wall position x can be calculated as: 𝑡𝑡
𝑥𝑥 = 𝛤𝛤v ∙ ∫0 𝐽𝐽eff ∙ 𝑑𝑑𝑑𝑑 .
(9)
The domain wall velocity coefficient 𝛤𝛤𝑣𝑣 is related to device structure and material property, which can be expressed as: Γ𝑣𝑣 =
𝑃𝑃∙𝜇𝜇 𝐵𝐵 𝑒𝑒∙𝑀𝑀𝑠𝑠
.
(10)
Here P is polarization efficiency, uB is Bohr magneton, e is elementary charge and Ms is magnetization saturation. B. Electrical Property of Spintronic Memristor TABLE I list the physical constants, the material parameters and the model parameters based on experimental results. In the compact model of spintronic memristor, there are three important electrical parameters – square sheet resistance 𝑅𝑅𝑒𝑒𝑒𝑒 and 𝑅𝑅𝑒𝑒𝑒𝑒 , critical current density Jcr, and domain wall velocity coefficient 𝛤𝛤𝑣𝑣 . 1) Square sheet resistance 𝑅𝑅𝑒𝑒𝑒𝑒 and 𝑅𝑅𝑒𝑒𝑒𝑒 We define 𝑅𝑅𝑒𝑒𝑒𝑒 and 𝑅𝑅𝑒𝑒𝑒𝑒 as the square sheet resistances of the thin film strip in the spintronic memristor when the magnetic directions of the two ferromagnetic layers are antiparallel and parallel, respectively. Usually, GMR (giant magneto resistance ratio) is used to represent the difference between 𝑅𝑅𝑒𝑒𝑒𝑒 and 𝑅𝑅𝑒𝑒𝑒𝑒 , which is 𝐺𝐺𝐺𝐺𝐺𝐺 =
𝑅𝑅𝑒𝑒𝑒𝑒 −𝑅𝑅𝑒𝑒𝑒𝑒 𝑅𝑅𝑒𝑒𝑒𝑒
.
(11)
Therefore, the values of the resistance per unit length of spin-valve strip rL and rH can be calculated as: 𝑟𝑟𝐿𝐿 =
𝑟𝑟𝐻𝐻 =
𝑅𝑅𝑒𝑒𝑒𝑒
𝑧𝑧 𝑅𝑅𝑒𝑒𝑒𝑒 ∙(1+𝐺𝐺𝐺𝐺𝐺𝐺 )
.
(12)
𝑧𝑧
The low square sheet resistance 𝑅𝑅𝑒𝑒𝑒𝑒 is determined by the resistivity of the thin-film strip at the low resistance state ρ and the thickness h by 𝜌𝜌
𝑅𝑅𝑒𝑒𝑒𝑒 = . ℎ
(13)
ρ is an intrinsic electrical parameter determined by the device structure and material property only.
𝛼𝛼 ∙𝛾𝛾∙𝐻𝐻𝑝𝑝 ∙𝑒𝑒∙𝑀𝑀𝑠𝑠 𝑃𝑃∙𝜇𝜇 𝐵𝐵
∙�
2𝐴𝐴
𝑀𝑀𝑠𝑠 ∙𝐻𝐻 𝑘𝑘
.
(14)
Here, Hp is the hard anisotropy in the direction perpendicular to the thin film plane (y direction), Hk is the easy anisotropy in the strip direction (x direction), A is exchange parameter, α is damping parameter, and γ is gyromagnetic ratio. However, the theoretical calculation of Jcr cannot explain all experimental measurements [14]. Therefore, Jcr is usually considered as an intrinsic electrical parameter that is directly obtained from the experimental calibration. 3) Domain wall velocity coefficient Γv Domain wall velocity coefficient Γv is an electrical parameter to describe how fast the domain wall can move. Instead of calculating Γv by using Eq. (10), usually people get this parameter directly from measurement. IV.
The following three factors greatly affect the electrical properties of a memristor: (1) the memristance at domain wall position x, (2) the critical current density Jcr, and (3) the changing speed of memristance. In this section, we will analyze the impacts of process variations from these three aspects accordingly. A. Memristance at domain wall position x By combining Eq. (5), (12), and (13), the memristance at domain wall position x can be further represented as: 𝐷𝐷
ℎ∙𝑧𝑧
+ 𝜌𝜌 ∙ 𝐺𝐺𝐺𝐺𝐺𝐺 ∙
𝑥𝑥
ℎ ∙𝑧𝑧
.
(15)
Here, ρ and GMR are determined by the device structure and material property only. Hence, the device geometry variations on length D, thickness h, and width z become the primary sources of the memristance variations. 𝜎𝜎𝐷𝐷 , 𝜎𝜎ℎ , and 𝜎𝜎𝑧𝑧 denote the standard deviations of each geometry parameter D, h and z, respectively. Compared to thickness h and width z, the overall length 𝐷𝐷 of the spintronic memristor is fairly long (See TABLE I). Hence, the impact of 𝜎𝜎𝐷𝐷 can be negligible. As shown in Figure 1, ℎ ∙ 𝑧𝑧 is actually the cross section area 𝑆𝑆 of the spintronic memristor. Accordingly, 𝜎𝜎𝑆𝑆 can be used to represent the standard deviation of 𝑆𝑆. After considering the variation of the cross section area, we have 𝑀𝑀′(𝑥𝑥) = 𝑀𝑀(𝑥𝑥) ∙
1
1+σ S
.
Mean
(16)
Here, 𝑀𝑀(𝑥𝑥) and 𝑀𝑀′ (𝑥𝑥) are designed value of memristance and the one affected by the variations of cross section area, respectively. Figure 2(a) illustrate the relationship between 𝑀𝑀′ (𝑥𝑥) and domain wall position x under different variations of the cross
+3sigma
-3sigma
7000 6000 5000 4000 0
200
400
600
800
1000
Domain Wall Position x (nm) (a)
10.0%
Lower bound of Memristance Upper bound of memristance
8.0% 6.0% 4.0% 2.0% 0.0% 4000
STATISTICAL ANALYSIS
𝑀𝑀(𝑥𝑥) = 𝜌𝜌 ∙
Memristance (Ω)
𝐽𝐽𝑐𝑐𝑐𝑐 =
Percentage
2) Critical current density Jcr Theoretically, the critical current density Jcr is a materialrelated parameter, which can be calculated by [21-25]:
8000
4500
5000
5500
6000
6500
7000
Memristance (Ω) (b) Figure 2. Memristance variation. (a) Memristance vs. domain wall postion; (b) Distributions of the lower-bound 𝑀𝑀𝐿𝐿 and upper-bound 𝑀𝑀𝐻𝐻
section area. Here we assume the cross section area follows a Gaussian distribution 𝜎𝜎𝑆𝑆 = 5%. Positive variation means that the cross section area is bigger than the designed value, and hence results in the decrease of memristance. On the contrary, negative variation leads to the increase of memristance. Figure 2(b) shows the distributions of the lower-bound 𝑀𝑀𝐿𝐿 and upper-bound 𝑀𝑀𝐻𝐻 of memristance from Monte-Carlo simulations. We note that cross section area variation does not affect the GMR of memristor. Because of the small 𝐺𝐺𝐺𝐺𝐺𝐺, the distribution of 𝑀𝑀𝐿𝐿 and 𝑀𝑀𝐻𝐻 could overlap with each other when the variation of cross section area is big. This can be improved by increasing the 𝐺𝐺𝐺𝐺𝐺𝐺 of spin-valve technology or choosing other materials/ structure with bigger distinction between the two resistance states. B. Critical current density Jcr Critical current density Jcr is an intrinsic electrical parameter, which can be calculated based on Eq. (14). Among all the related material parameters, the actual values of hard anisotropy Hp and the easy anisotropy Hk heavily rely on the LER and RDD existing in manufacture process. We use 𝜎𝜎𝐻𝐻𝑝𝑝 and 𝜎𝜎𝐻𝐻𝑘𝑘 to denote the standard deviations of Hp and Hk, respectively. Then, the relationship between the actual critical ′ current density 𝐽𝐽𝑐𝑐𝑐𝑐 by taking into account process variation and the designed 𝐽𝐽𝑐𝑐𝑐𝑐 can be approximately expressed as ′ 𝐽𝐽𝑐𝑐𝑐𝑐 ≅ 𝐽𝐽𝑐𝑐𝑐𝑐 ∙
1+𝜎𝜎 𝐻𝐻 𝑝𝑝 1 2
1+ ∙𝜎𝜎 𝐻𝐻 𝑘𝑘
.
(17)
8.0%
60 40
Velocity (m/s)
Percentage
6.0% 4.0% 2.0%
20 0
Mean
-3sigma
+3sigma
-20 -40 -60
0.0%
0
3.5E+07 4.0E+07 4.5E+07 5.0E+07 5.5E+07 6.0E+07 6.5E+07
200
Critical current density Jcr (A/cm )
The domain wall velocity coefficient Γv describes how fast the domain wall can move when applying a certain amount of current density on the memristor. It is also an electrical parameter affected by process variation. Usually people get Γv and its standard deviation 𝜎𝜎Γ 𝑣𝑣 directly from measurement.
Eq. (6a) and (6b) show that the effective current density Jeff has different relationship with memristance 𝑀𝑀(𝑥𝑥) when applying a voltage or a current input to the spintronic memristor. Here, we will discuss the two situations separately.
1) Voltage driven By combining Eq. (6a) and (15), the effective current density Jeff when a voltage input is applied to the spintronic memristor can be further derived to 0,
𝑉𝑉
,
𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝐽𝐽 ≥ 𝐽𝐽cr 𝑤𝑤ℎ𝑒𝑒𝑒𝑒 𝐽𝐽 < 𝐽𝐽cr
.
(17a)
An interesting observation is that, when the spintronic memristor is stimulated by a voltage source, Jeff is independent to device geometry variations. The relationship between the actual domain wall velocity 𝑣𝑣 ′ (𝑥𝑥) after considering process variations and the designed one 𝑣𝑣(𝑥𝑥) can be expressed as 𝑣𝑣 ′ (𝑥𝑥) = 𝑣𝑣(𝑥𝑥) ∙ �1 + 𝜎𝜎Γ 𝑣𝑣 � .
(18a)
2) Current driven When a current input is applied to the two terminals of the spintronic memristor, 𝑣𝑣′ becomes to 𝑣𝑣 ′ (𝑥𝑥) = 𝑣𝑣(𝑥𝑥) ∙
1+𝜎𝜎 Γ 𝑣𝑣 1+𝜎𝜎 𝑆𝑆
.
1000
(18b)
40
Velocity (m/s)
C. Chaning Speed of Memristance In a spintronic memristor, the changing speed of memristance is reflected by the domain wall velocity v, which is determined by domain wall velocity coefficient Γv and effective current density Jeff based on Eq. (8).
𝜌𝜌 ∙𝐷𝐷+𝜌𝜌∙𝐺𝐺𝐺𝐺𝐺𝐺 ∙𝑥𝑥
800
60
′ Figure 3 shows the distribution of 𝐽𝐽𝑐𝑐𝑐𝑐 with the assumption that both Hp and Hk have Gaussian distributions with 5% standard deviation each. In order to minimize the disturbance of Jrd on the read operation of memristor, Jrd should be ′ controlled under the lower bound of 𝐽𝐽𝑐𝑐𝑐𝑐 distribution.
𝐽𝐽 =
600
(a)
Figure 4. Variation of critical current density 𝐽𝐽𝑐𝑐𝑐𝑐 .
𝐽𝐽ef f = �
400
Domain Wall Position x (nm)
2
20 0
-3sigma
Mean
+3sigma
-20 -40 -60 0
200
400
600
800
1000
Domain Wall Position x (nm) (b) Figure 3. Domain wall velocity variation. (a) Domain wall velocity vs. domain wall postion when applying a voltage input; (b) Domain wall velocity vs. domain wall postion when applying a current input.
In this case, both cross section area and domain wall velocity coefficient variations will contribute to the variation of domain wall velocity. Figure 4(a) and Figure 4(b) illustrate the relationship between 𝑣𝑣 ′ (𝑥𝑥) and domain wall position x by varying 𝜎𝜎Γ 𝑣𝑣 and 𝜎𝜎𝑆𝑆 while applying a sinusoidal voltage 𝑉𝑉𝑖𝑖𝑖𝑖 = 𝑉𝑉𝑚𝑚 ∙ sin(𝜔𝜔𝜔𝜔) or current 𝐼𝐼𝑖𝑖𝑖𝑖 = 𝐼𝐼𝑚𝑚 ∙ sin(𝜔𝜔𝜔𝜔), respectively. The frequency of the input flux f = ω/2π is set to 10MHz (=1/100ns). The amplitude of voltage 𝑉𝑉𝑚𝑚 = 0.75𝑉𝑉 , or the amplitude of current 𝐼𝐼𝑚𝑚 = 150µ𝐴𝐴 . Because current driven suffers from the additional variation of cross section area, the domain wall velocity shows larger variations than that of voltage driven. When domain wall position 𝑥𝑥 ≅ 975𝑛𝑛𝑛𝑛 at the +3𝜎𝜎 corner in Figure 4(b), the current density is smaller than 𝐽𝐽𝑐𝑐𝑐𝑐 , and hence, domain wall stops moving toward the right end.
Besides the variations of Γv and S, 𝑣𝑣 ′ (𝑥𝑥) is also affected by the variations of critical current density 𝐽𝐽𝑐𝑐𝑐𝑐 . At which domain wall position 𝑥𝑥′ where 𝐽𝐽(𝑥𝑥) = 𝐽𝐽𝑐𝑐𝑐𝑐 is determined by the variations of material characteristics, i.e., Hp and Hk.
To demonstrate the variation of the hysteretic profile, the designed I-V curves when applying the sinusoidal voltage or current input flux are shown in Figure 5(a) and Figure 5(b), respectively. The same input waveforms in Section IV.-C.-3) were used here. Ideally, the value of memristance M oscillates between 5kΩ (= rL·D) and 6kΩ (= rH·D). In the experiment, we set the standard deviations 𝜎𝜎𝑆𝑆 = 5%, 𝜎𝜎𝐻𝐻𝑝𝑝 = 5%, 𝜎𝜎𝐻𝐻𝑘𝑘 = 5%, and 𝜎𝜎Γ 𝑣𝑣 = 5% . To demonstrate the impacts of the process
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Figure 5. I-V curves. (a) voltage input; (b) current input.
variation, the curves at the 3σ minimum (−3 σ) and the 3σ maximum (+3σ) corners are also presented in the corresponding figures. The compact model of the spintronic memristor can be easily implemented by Verilog-A language. It could be used to simulation the electrical behavior of a two-terminal spintronic memristor in SPICE tool. V.
CONCLUSION
In this paper we analyze the physical mechanism of the magnetic-domain-wall motion based spintronic memristor in details. The main sources of process variations are considered and their impacts on memristor electrical characteristics are analyzed quantitatively. The proposed process variation-aware spintronic memristor model consists of a set of analytical equations and can be easily implemented by Verilog-A language for circuit design. ACKNOWLEDGMENT
[14] [15] [16]
[17]
[18] [19] [20]
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The authors are grateful to Professor Xie (Pennsylvania State University) for discussion.
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