COMPARATIVE STUDY OF POWER REDUCTION TECHNIQUES ...

International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 2 , May 2011,(80-88) ,ISSN 2231-3133

COMPARATIVE STUDY OF POWER REDUCTION TECHNIQUES FOR STATIC RANDOM ACCESS MEMORY Varun Kumar Singhal1, Balwinder Singh2 1,2

ACS Division, CDAC (Centre for Development of Advanced Computing), Mohali, India

Abstract The growing market of portable electronics devices demands lesser power dissipation for longer battery life and compact system. As Static Random Access Memory (SRAM) is used in high speed applications such as cache memory and occupies about 90% of silicon area. Various research works have been done to trim down its power consumption. There are two ways of reducing over all power consumption in CMOS SRAM these are either by decreasing the dynamic power or decreasing standby power. This paper aims to provide a comprehensive stuff for early design phases of low power COMS SRAM for designers and researchers. The different techniques available like voltage swing reduction, shared-bit line architecture, charge recycling technique, ZA asymmetric cell, 9T cell, 9T balanced cell architecture, sense-amplifying cell are discussed in this paper.

more important. High power dissipation of SRAM degrade the performance and even leads to burnout of IC under some critical conditions. Hence by using low power SRAM we can overcome these problems. Also if total heat generation inside an IC reduces, power budget will also get down and manufacturing cost reduces. The power dissipation occurs in the form of dynamic power and standby power. Dynamic power is the power consumed during read and write operation while standby power is the power consumed inside the cell when a bit is stored inside it, it is due to leakage of charge. Different approaches to reduce power in SRAM has been proposed by many authors are discussed in this paper. The main power consumption element under dynamic power in CMOS SRAM is the charging and discharging of bit lines. Since in memory there are long running bit lines and for every read and write operation one bit line charges to full swing and another discharges to ground. The power consumed in this cycle is given by equation 1[6],

Key words: Static random access memory (SRAM), bit lines, cell leakage.

I. Introduction In present scenario every one wants hand held electronics devices with high performance, high speed, long battery life and lot of features. Different manufacturers also dedicated to fulfill this requirement. Memory occupies app. 90% of the silicon area and dissipate considerable amount of power. Static Random Access Memory (SRAM) is used in high speed applications such as cache memory which is very close or inside the processor and in case of its high power consumption, dissipation of heat generated inside the processor is a problem due to that low power SRAM has become

Where, P = Power f = Clock frequency = Capacitance of bit lines = Capacitance of data lines = voltage swing on bit lines = supply voltage In conventional SRAM, Then equation 1 reduces to,

With the increase in memory size Cbl and Cdl will also increase and power consumption varies directly with memory size. To avoid this banked organization is used[2]. Further power varies directly with ∆Vbl


which is optimized by reducing voltage swing [4], charge recycling[5,6], sense-amplifying cell[11], etc. The main power consumption element under standby-power in CMOS SRAM is the leakage current. As shown in Fig 1 a CMOS SRAM cell consists of two cross coupled inverters and two nMOS m5, m6 as access transistors. SRAM cell always is in state „0‟ or in „1‟. If cell stores „0‟ then m2, m3 are „on‟ and m1, m4 are „off‟. If it stores „1‟ then m1, m4 are „on‟ and m2, m3 are „off‟. In both the cases there are two leakage current paths from supply to ground. This leakage current is the cause of standby power. As any device is not ideal so we can only decrease the amount of leakage current to suppress power budget. Cell leakage can be minimizes at fabrication level. In this paper first the read and write operations of conventional 6T SRAM are discussed and then the work done by different author has been discussed.

II. Conventional 6T CMOS SRAM Cell Fig. 1 shows the conventional 6T SRAM cell. It consists of 2 PMOS and 4 NMOS transistors. The structure is like two cross coupled inverters with two NMOS as word select.

difference will be sensed by sense amplifier and finally stored bit will be available at the output of sense amplifier. From the operation it is clear that the cell dissipate power in two cases, one is during reading and writing the bit, due to switching activity of transistors, and another is when the cell is in idle state, because one transistor from both the inverter is in „on‟ state continuously which dissipate power due to leakage current. In addition to this the peripheral circuits such as row decoder, column decoder and sense amplifier also dissipates a lot of power.

III. Techniques to Reduce Power A lot of work has been done to minimize the power dissipation in CMOS SRAM. This section describes the different power reduction techniques in SRAM proposed by different authors. A. Banked Organization Banked organization[2] approach focuses on reducing the total active capacitance and resistance of the bit and address lines of memory by dividing it in to small blocks. It is clear that whenever memory cells are accessed either for read or write operation a complete row and a complete column is activated, and the capacitance of all long running lines effects the total power dissipation. One solution is if we divide memory in to sub blocks as shown is Fig 2 then the net active capacitance for read/write operation will reduce to half for both bit lines and address line because their length is broken down in two parts. Bank 2

Bank 3

Bank 0

Bank 1

Fig 1. Conventional 6T SRAM cell 2.1 Cell operation We can perform either write or read operation on the cell. For write operation two signals will be produce from the input date one is „bl‟ and another is „blb. Where bl = data and blb = compliment of data. Then word line (wl) goes high which enables the access transistors and the data will be written in the cell. For read operation both „bl‟ and „blb‟ lines are pree-charge to voltage Vpre and then „wl‟ goes high, since SRAM is already either in state „0‟ or in „1‟, then according to the state only one line discharges to Gnd and a voltage difference is establishes between „bl‟ and „blb‟ lines. This

common signals

An-1 An

Fig 2. Banked organization of SRAM In general consider a memory contains x no. of cell(i.e. it can store a maximum of x bits) and organized in n2 blocks called banks then number of


cells per bank will be x/n2 and bit line and word line capacitance will reduces to 1/n. Fig 2 shows the banked organization of memory for n = 2. From equation 1 it is clearly seen that if Cbl and Cdl decreases P will also reduce. But due to the increase in control circuit silicon area increases. So, there should be an optimization for calculating the value of n.

B. Reducing Voltage Swing From equation 3, power dissipation is directly proportional to supply voltage. i.e.,

Therefore with the decrease in supply voltage, power consumption will also reduce but in turn increases the delay due to decrease in current flowing in the circuit. B. S. Amrutur et al.[3] presents technique to reduce the power requirements of a wide access width memory while having minimum effect on its access time. Table 1 summarizes the results at 5.0, 3.0 and 1.5V. A 2k × 32bit SRAM has been designed in 1.2µm CMOS process. The memory is partitioned into 8 blocks each 256 rows and 32 cells. Table 1. Delay and power at different voltage for reduced voltage swing scheme. Supply (V) 1.5 3.0 5.0

T Access (Gate delay) 22.3 21.0 19.4

Power (mW) 5.2 75.0 366.0

Gate delay (ns) 2.3 0.63 0.38

At 5.0V power consumed is 366.0mW and delay is 0.38ns and at 3.0V power consumed is 75.0mW and delay is 0.63ns while at 1.5V power consumed is 5.2mW and delay is 2.3ns. Power at 1.5V is minimum.

C. Shared-Bit Line Architecture H. Morirnura et al.[4] proposes a shared-bit line SRAM cell architecture with modified address assignment that reduces wasted memory-cell current to zero while suppressing the area penalty. The architecture is shown in Fig 3. Two extra access transistors are added with the conventional 6T SRAM cell (m1 and m2 for cell2 in Fig 3). Here, „blb1‟ and

m1 are shared by cell1 and cell2, similarly „bl2‟ and m2 are shared by cell2 and cell3. For both read/write operation on cell2 „wl‟ and „ysel1‟ goes high. For write operation data and databar is put on „blb1‟ and „bl2‟ and for read operation data stored in cell will appears on the same lines. Cell1 and cell3 are not activated because „ysel0‟ and „ysel1‟ are low and hence there is no wastage of memory-cell current. While selecting cell1 m3 and m4 are „off‟ because „ysel1‟ is low and „bl0‟ and „blb1‟ works as bit and bitbar lines for cell1. There are 7 transistors per cell which increases the silicon area but only one bit line per column decreases capacitance and hence a lot of power saved. Since parasitic capacitance of the „ysel‟ is larger than that of a bit line because it is connected with two transistors. The power dissipation due to charging and discharging of these parasitic capacitances is concealed by the assignment of the column address in such a way that column address is assigned to more significant bits in a memory address. Because the changing probability of a more significant bit is lower than that of a less significant bit in general, this modified address assignment makes it possible to lower the effective operating frequency of the „ysel‟ and reduces the power. A test chip has been fabricated at 0.35µm triple-metal MTCMOS logic process. The area penalty is 13% compared to the standard 6T cell. Test chip operating voltage is 1V and it is a synchronous 64kb (2kw×16b×2) SRAM macro cell. Simulated maximum operating frequency at 1V supply is 33MHz. The chip has been tested at 10MHz and a conventional checker-hoard test pattern was used. The power consumed in the memory cell array is reduced from 1728µW to 486µW, which is 1/4 to that of the conventional one, due to the shared-bit line architecture. Although the dynamic power reduces but one can not perform read or write operation on adjacent cells in a row because there will be a clash of data on the middle line. Suppose in Fig 3, if there is a requirement of writing “11” simultaneously in cell2 and cell3, the patterns should be: blb1 = „1‟ bl2 = „0‟ bl2 = „1‟ blb3 = „0‟ „bl2‟ can‟t be „0‟ and „1‟ simultaneously, the architecture becomes unstable. A similar case will be in writing “00” in any adjacent cells.


Fig 3. Shared-bit line architecture[4]

D. Charge Recycling Technique As mentioned earlier the main power consumption component is the charging and discharging of bit lines. K. Kim et al.[5] and B. D. Yang et al.[6] proposes a write scheme using charge recycling (CR) method in which the previous charge on a bit line is reuse on the adjacent bit line to develop a low voltage swing. In this scheme bit lines are paired with the help of transmission gate switches number of pairs are represented by N. Figure 4 shows the CR-SRAM for N=2, means 2 bit line pairs are paired.

EV are „on‟ and EQ are „off‟ and write operation is carry out. The common voltage on ith bit line pair during equalization is given by equation 5,

Where, N = no. of bit lines paired. i = ith pair of bit line (i=1, 2...N) For N = 2, Vcom1 (i=1) = (3/4)Vdd Vcom2 (i=2) = (1/4)Vdd and the voltage difference developed between bit and bitbar lines is Vdd/N(i.e. Vdd/2 for N = 2). When N bit lines are paired, the voltage swing and power of bit lines are reduced to 1/N and 1/N2, respectively[6]. A test chip of 32kb has been fabricated and tested, table 2 summarizes the measured results. Table 2. Results of charge recycling technique on SRAM

Fig 4. CR-SRAM for N=2 Switches P1, P2, S1 and S2 are controlled by input data. Suppose din1 is the input data to be write in first column and din2 is the input data to be write in second column. Then, if dinx is high, switches P1,P2 are „on‟ and switches S1,S2 are „off‟, while if dinx is low, switches P1,P2 are „off‟ and switches S1,S2 are „on‟. The circuit works in two modes, the equalization mode and the evaluation mode. In equalization mode switches EQ are „on‟ and EV are „off‟ and bit and bitbar lines are charged to some common voltage. While in evaluation mode switches

Parameter

Conven -tional

CRSRAM [5]

CRSRAM [6]

Memory size Technology N Frequency

32kb .13µm 100MH z 1.5V 1.5V .99mW -

32kb .13µm 4 100MHz

32kb .13µm 8 100MHz

1.5V 0.25V .162mW -

1.2V 0.15V .135mW .128mW

Supply voltage ΔVbl Write power Read power


E. ZA Asymmetric Cell Y. J. Chang et al.[7] propose an 8T SRAM cell, termed as “zero-aware asymmetric (ZA) cell”. Zeroaware is because it minimizes power consumption in write „0‟cycle only and asymmetric is because it is not symmetric (standard 6T cell is symmetric, Fig 1). Fig 5 shows the cell structure of zero-aware asymmetric (ZA) cell. It consists of 2 pMOS (m1 and m3) and 6 nMOS (m2, m4, m5, m6, m7 and m8) transistors. During read operation „ws‟ signal is high so that m5 is „on‟ and cell behaves as conventional 6T cell. For write operation there is two possibilities write „1‟ and write „0‟. Write ‘0’ For writing „0‟, node A must be written to high. To achieve this „bl‟ is set to low and „wz‟ set to high. When „wwl‟ goes high there will be further two cases writing „0‟ to „0‟ and writing „1‟ to „0‟. In first case there will not be any state transition. But in second case node A charges by „wz‟ through m7 and node B flip its state from „1‟ to „0‟.

bit lines per column due to which total capacitance for the memory increases.

F. 9T Cell Architecture C.M.R. Prabhu et al.[9] propose 9-t SRAM cell architecture which reduce the power consumption during write „0‟ and write „1‟ operation. Fig 6 shows the circuit diagram. It includes two extra tail transistors (m3 and m4) in the both pull-down paths and a transistor m5 to control switching of m3 and m4. Signal „rwl‟ is always high for the read operation, so that the signal „ws‟ is same as node voltage A. „bl‟ and „blb‟ are made high by the precharge circuit. If „0‟ is written in the cell then node „A‟ is at logic „0‟ then transistors m3 and m4 are „on‟ and „off‟ respectively. Then „bl‟ starts discharging through transistors m8-m2-m3. „blb‟ remains at logic „1‟ because m4 is „off‟. Similarly, if „1‟ is written in the cell then node „A‟ is at logic „1‟ then m3 and m4 are „off‟ and „on‟ respectively. Then „blb‟ starts discharging through transistors m9-m6-m4, „bl‟ remains at logic „1‟ because m3 is „off‟.

Fig5. Zero-aware asymmetric (ZA) cell[7] Write ‘1’ For writing „1‟ node A must be written to low. To achieve this „bl‟ set to high and „wz‟ set to low. When „wwl‟ goes high, again there will be two cases writing „1‟ to „1‟ and writing „0‟ to „1‟. In first case there will not be any state transition. But in second case node A discharges by „wz‟ through m7 and node B flips its state from „0‟ to „1‟. There is a reduction in average write power up to 61% and 68% for the baseline instruction and data caches, respectively with 12.6% cell area penalty in this cell. The cell structure is like it has two ports on node „A‟ one is write port „wz‟ through m7 and another is read port „blb‟ through m8. There are three

Fig 6. 9T cell architecture[9] For the write operation „rwl‟ is low so, that cell effectively contains 8 transistors. For writing „1‟ node B must be written to low to achieve this „bl‟ set to high and „blb‟ set to low and „ws‟ set to high. When „wl‟ goes high there are two possibilities writing „1‟ to „1‟ and writing „0‟ to „1‟. In first case there will not be any state transition. But in second case transition occur because m4 is „on‟. For write „0‟ node A must be written to low this is done by setting „bl‟ to „1‟ and blb to „0‟ and „ws‟ set to low. When „wl‟ goes to high, again there are two


possibilities writing „0‟ to „0‟ and writing „1‟ to „0‟. In first case there will not be any state transition. But in second case transition occur because m3 is „on‟. Simulation of the proposed work has been carry out for 0.12µm technology at 1.2V supply, table 3 shows the simulation results. Table 3. Write power comparison of conventional versus 9-t cell architecture Cell Type Conventional 9T cell [9] % reduction

0 → 1 write power in µw 20.21 12.46 38.37%

1 → 0 write power in µw 19.72 10.39 47.31%

There is a power reduction of 38.37% for „0‟ to „1‟ write operation and 47.31% for „1‟ to „0‟ write operation.

similar to za asymmetric cell[7]. When „bl‟ and „blb‟ are precharged to some precharge voltage Vpre, m6 will turns „on‟. If there is „1‟ in cell „blb‟ will discharge through m9-m4-m6 and if there is „0‟ in cell „bl‟ will discharge through m7-m3 and m6 will turn „off‟. For writing „0‟ node B must be written to high. To achieve this „bl‟ set to low and „blb‟ set to high. When „wl‟ goes high there will be two cases writing „0‟ to „0‟ and writing „1‟ to „0‟. In first case there will not be any state transition but in second case node B charges through m9 and node A flips its state from „1‟ to „0‟ because it is the input port of inverter made up of m1 and m3. For writing „1‟ node A must be written to high. To achieve this „bl‟ set to high and „blb‟ set to low. When „wl‟ goes to high, again there will be two cases writing „1‟ to „1‟ and writing „0‟ to „1‟. In first case there will not be any state transition. But in second case node B discharges through m9 and node A flips its state from „0‟ to „1‟ because it is the input port of inverter made up of m1 and m3.

G. 9T Balanced Cell Architecture C.M.R. Prabhu et al.[10] proposes a 9T balanced SRAM cell architecture which consists of an asymmetric inverter pair to reduce the power consumption, named as 9T balanced cell. The proposed circuit consumes low power during both write and read operations. Fig 7 shows the circuit diagram. It includes two extra tail transistors (m5 and m6) and an extra pass transistor (m8) for read operation. The design is quite similar to zero-aware (ZA) asymmetric cell[7] which utilizes a tail transistor to reduce write power consumption during write „0‟ operation.

The circuit is simulated for 0.25µm at 2.5V. It consumes 0.891mw power during read „1‟ while 0.0025mw during read „0‟. This tremendous decrease in read „0‟ power is due to the leakage current reduction by m5 and m6 transistors. In addition to this switching activity of cell is controlled by „bl‟ instead of extra signal „ws‟ in case of za cell[7].

H. Sense-Amplifying Cell K. Kanda[11] propose 7T SRAM cell architecture in which bit line swing is reduced to Vdd/6 and amplifying the voltage swing by a common tail transistor in pull down path of both inverters. As mentioned earlier the main power dissipation

Fig 7. 9T balanced cell[10] During read operation read word line (rwl) signal is set to low so that m5 and m8 are off. The cell is now

Fig 8 Sense-Amplifying Cell[11]


component is the charging and discharging of bit lines and in this scheme the bit line swing (ΔVbl) is reduced to Vdd/6 then according to equation 1 power is also reduce.

and N=4. The test chip operated at 100 MHz with1.5V supply. Results obtained are increase in read delay is 5%, 25% noise margin decrease, and 11% increase in area. Write power reduces to 13.6mW from 135mW which is 89.93% (app. 90%) less then the power in conventional cell. As there is an increase in delay and tremendous decrease in write power the technique is suitable for low power devices, not for high performance devices.

Figure 8 shows the circuit diagram, it includes one extra transistor (m5 termed as Vss switch) between the ground and pull-down paths both the inverters which is controlled by signal „scl‟. Signal „scl‟ goes high during read and write operation only. Sizing of transistor m5 becomes important in this case. They define β as the ratio of channel widths of m5 and m4 (i.e. β = Wm5 / Wm4) and hence it becomes independent from technology specific parameters. An increase in the value of β will reduce the read delay hence it should be as high as possible, but by fabrication point of view it should have a finite value. Further m5 (the Vss switch) increases area penalty and the fact that a row acts as a word, in general, and all bits of a word are accessed simultaneously it is possible to put a single Vss switch for all cell in a row. But this will require β to be multiply by number of cells in a row which results in very large size of Vss switch. The solution is to make small groups and hence another parameter „N‟ is come in to role is defined as the number of cells per Vss switch or number of cells in a group. Simulation results shows that when N=2, area overhead is always larger than 10%, while it can be kept below 10% when N=4 and β=4 or less.

IV. COMPARISON Table 4 shows the comparison of different power reduction techniques for SRAM. It includes the results of work presented in this paper. Last column of table 4 gives the basic principle of power reduction in the particular scheme.

V. CONCLUSION In this paper, existing low power CMOS SRAM design techniques are discussed. Banked organization of memory reduces the power consumption due to capacitance of bit and word lines by dividing them in to groups. Voltage swing reduction reduces the power of SRAM while having minimum effect on its access time by reducing voltage swing. Shared-bit line SRAM cell architecture reduces memory cell current wastage. Also one bit line per column reduces capacitance. But there is a clash during read/write “00” or “11” on adjacent cells. Charge recycling and

A test chip of a 64-kb SRAM has been fabricated with 0.35µm triple-metal CMOS process taking β=3

Table 4. Comparison of different power reduction techniques for SRAM Author

Memory size 64kb

Technology 1.2µm

Supply voltage 1.5V

64kb

0.35µm

1.0V

10MHz

486µW

-

K. Kim et al.[5]

32kb

0.13µm

1.5V

100MHz

0.16mW

-

B. D. Yang et al.[6] C.M.R. Prabhu et al.[9] C.M.R. Prabhu et al.[10] K. Kanda[11]

32kb

0.13µm

1.2V

100MHz

0.14mW

0.13mW

-

0.12µm

1.2V

-

10.92µW

-

-

0.25 µm

2.5V

-

1.19mW

0.45mW

64kb

0.35µm

1.5V

100 MHz

13.6mW

-

B. S. Amrutur et al.[3] H. Morirnura et al.[4]

Operating Frequency -

Write power 5.2mW

Read power -

Basic principle Low supply voltage. Capacitance and leakage current reduction. Low bit lines voltage swing. Low bit lines voltage swing. Leakage current reduction Leakage current reduction Low bit lines voltage swing


sense amplifying schemes again focus on reducing voltage swing on bit and bitbar lines. Charge recycling uses bit line staking in series while sense amplifying scheme uses an additional voltage control circuit to control low voltage swing. Zero-aware asymmetric (ZA) cell reduces power during write operation only, considering the fact that about 85% to 90% of data bits are „0‟[7]. But it requires an extra signal „ws‟. 9T cell reduces write power while 9T balanced cell reduces both write and read power. 9T balanced cell it is similar to ZA cell but the switching activity is controlled bit line instead of extra signal WS as compared to ZA cell. The analysis and references in this paper is useful in the early design phases of low power SRAM.

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simultaneously read/write-disturbed accesses” IEEE journal of solid state circuits, vol. 43, no. 9, september 2008, pp.2109-2119. [23]M. Meterelliyoz, J. P. Kulkarni, K. Roy, “Analysis of SRAM and eDRAM cache memories under spatial temperature variations” IEEE transactions on computeraided design of integrated circuits and systems, vol. 29, no. 1, january 2010, pp.2-13. [24]H. Jeon, Y. B. Kim, M. Choi, “Standby leakage power reduction technique for nanoscale CMOS VLSI systems” IEEE transactions on instrumentation and measurement, vol. 59, no. 5, may 2010, pp.1127-1133. [25]S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi H. Shinohara, “A 65 nm SoC embedded 6TSRAM design for manufacturing with read and write cell stabilizing circuits” IEEE symposium on VLSI circuits digest of technical papers, pp.17-18. [26]A. Raychowdhury, S. Mukhopadhyay, K. Roy, “A feasibility study of subthreshold SRAM across technology generations” proceedings of the 2005 international conference on computer design (ICCD‟05), 2005, pp.417422. [27]P. Athe, S. Dasgupta, “A comparative study of 6t, 8t and 9t decanano SRAM cell” IEEE symposium on industrial electronics and applications (ISIEA 2009), october 4-6, 2009, Kuala Lumpur, Malaysia, pp.889-894. Varun Kumar Singhal received his B.E. (Electronics engineering) degree from Jiwaji University, Gwalior in 2009 and pursuing M.Tech. (VLSI design) from Centre for Development of Advanced Computing (CDAC), Mohali under Punjab Technical University, Jalandhar. His current interest includes Low power memory design, VLSI Design and microcontroller based system devices. Balwinder Singh has obtained his B. Tech degree from National Institute of Technology, Jalandhar and M. Tech degree from University Centre for Inst. & Microelectronics (UCIM), Panjab University, Chandigah in 2002 and 2004 respectively. He is currently serving as Design Engineer in Center for Development of Advanced Computing (CDAC), Mohali and is a part of the teaching faculty. He has 5+ years of teaching experience to both undergraduate and postgraduate students. Mr. Singh has published two books and many papers in the International & National Journal and Conferences. His current interest includes Genetic algorithms, Low power techniques, VLSI Design & Testing, and System on Chip.