Eduardo Sanchez. Ecole Polytechnique Fédérale de Lausanne. Exercices de
VHDL. Page 2. Eduardo Sanchez. Ecole Polytechnique Fédérale de Lausanne.
Exercices de VHDL Eduardo Sanchez
Ecole Polytechnique Fédérale de Lausanne
Compteur 4 bits library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port (Clk : Reset : Load : MaxCount : Zero : Count : end counter;
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in std_logic; in std_logic; in std_logic; in std_logic_vector(3 downto 0); out std_logic; out std_logic_vector(3 downto 0));
Eduardo Sanchez Ecole Polytechnique Fédérale de Lausanne
architecture behavioral of counter is signal counter_value, max_value : std_logic_vector(3 downto 0); begin MAX_HOLDER : process (Clk, Reset, Load, MaxCount) begin if (Reset = '1') then max_value '0'); elsif (Clk'event and Clk = '1') then if (Load = '1') then max_value
