Computer Interfaces - David Vernon

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The need for computer interfacing ... Programming flexibility (compared with hard -wired logic) ... MEMR (memory read): processor is reading from the contents.
Computer Interfaces David Vernon

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

The goal of this course is to introduce hardware and software design techniques and issues for interfacing computers and peripheral devices

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

Course Contents ‰ Digital data communication standards – serial communications ƒ ƒ ƒ ƒ ƒ

Devices RS232 RS422 Handshaking Implementation of RS232 on a PC

‰ Universal Serial Bus (USB) ƒ USB standards ƒ Types and elements of USB transfers ƒ Development procedure for USB applications Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

Course Contents ‰ Parallel Communications ƒ ƒ ƒ ƒ

General Purpose Interface Bus (GPIB) GPIB signals and lines Handshaking and interface management Implementation of a GPIB on a PC

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

Course Contents ‰ Digital and Analogue Interfacing ƒ Digital Interfacing o Digital I/O ports o Interfacing external signals to digital I/O ports o Optical isolation ƒ Analogue Interfacing o Revision of A/D and D/A conversion techniques o Multiplexing o Analogue I/O cards o Data acquisition and control using a PC

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

Course Texts: PC Interfacing Communications and Windows Programming, William Buchanan, Addison Wesley Microcomputer Interfacing and Applications, M. A. Mustafa, Newnes

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

Course Loading: 0.5 Module

1 Lecture each week (weeks 1, 2, 3, …) 1 Tutorial every second week (weeks 3, 5, 7, 10, 12, 14) 1 Lab demonstration every fourth week (weeks 4, 11, 15) 1 Assignment, due on the last day of week 15 (22nd Dec.) Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces

Motivation

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces

Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

The need for computer interfacing ‰ ‰

Advanced control applications need flexible processing power, i.e. computers Control data has to be input and output ƒ Input from sensors (speed, acceleration, temperature, ..) ƒ Output to actuators (motors, switches, valves, …)

‰

Examples: ƒ Robotics ƒ Industrial process control

‰

Advantages of using computers for Data Acquisition & Control ƒ ƒ ƒ ƒ ƒ

High speed Programming flexibility (compared with hard-wired logic) Mass storage of data Data analysis and visualization Low cost (relatively) Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces ‹

Issues: ‰ Input vs output (direction) ƒ Communication between devices ƒ Data acquisition ƒ Device control

‰ Digital vs Analogue data (modality) ƒ Signal levels (may be a need for signal conditioning) ƒ Analogue to digital conversion (ADC) ƒ Digital to analogue conversion (DAC)

‰ Serial vs parallel (mechanism) ƒ Speed, distance, number of required lines, standard I/F

‰ Polled vs interrupt driven (mechanism) ƒ Simplicity, processor efficiency Copyright © 2007 David Vernon (www.vernon.eu)

Computer Interfaces

Microprocessor Architecture

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

History ‰ Early ’70s: Intel 4004 ƒ ƒ ƒ ƒ ƒ

4 bit of data (nibble) 2000 transistors 46 instructions 4kB program code 1kB data

‰ 1974 - : 8008, 8080, 8085 ƒ 8008: 14-bit address space (16kB memory) ƒ 8080: 16-bit address space (64kB memory)

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

History ‰ Early 80s: 8086 – Major revolution in processing power ƒ ƒ ƒ ƒ ƒ

16-bit data bus 20 bit address bus (1MB memory) PC & PC-XT 8088: Multiplexed 8-bit data bus 80286: enhance version (PC AT)

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

History ‰ 1985: Intel 80386 ƒ 32 bit data bus ƒ 32-bit address bus (4GB memory)

‰ 1986: Intel 80486 ƒ Memory cache ƒ On-chip maths co-processor

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

History ‰ 1990s: Pentium (P-5) ƒ 64-bit superscalar architecture ƒ MISD instruction pipeline (can execute more than one instruction at a time) ƒ 64-bit databus ƒ 32-bit address bus

‰ 2000s: Pentium II (P-6) ƒ Up to 4 processors on the same bus ƒ Single bit error detection and correction on the data-bus ƒ Multiple bit error detection

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture 8088 Microprocessor

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

8088 ‰ 8288 bus controller generates signals based on the 8088 status lines S0, S1, S2: ‰ Main control signals: ƒ IOR (I/O Read): processor is reading from the content of the address which is on the I/O bus ƒ IOW (I/O Write): processor is writing the contents of the data bus to the address on the I/O bus ƒ MEMR (memory read): processor is reading from the contents of the address which is on the address bus ƒ MEMW (memory write): processor is writing the contents of the data bus to the address which is on the address bus ƒ INTA (interrupt acknowledge): used by the processor to acknowledge an interrupt (sent via the 8259 interrupt controller) Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

8088 ‰ Two address spaces: ƒ Memory space ƒ I/O space

‰ Registers ƒ 4 general purpose registers AX Accumulator (all I/O operations & some arithmetic) BX base register (can be used as an address register) CX count register (e.g. loops) DX data register (some I/O and when multiplying & dividing) ƒ 4 addressing registers SI source index (extended addressing commands) DI destination index (used in some addressing modes) BP base pointer SP stack pointer Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

8088 ‰ Registers ƒ Status registers registers IP instruction pointer (contains address of next instruction to be executed) F flag register (with bits set depending on conditions or results of operations, e.g. is the result negative) ƒ Segment registers (16 bits – 64kB) CS register: code segment; defines the memory location where the code/instructions are stored DS register: data segment; defined where the data from the program will be stored SS register: stack segment; location of the stack ES register: extra segment ƒ All addresses are defined with respect to the segment registers ƒ 8086 has a segmented memory architecture Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Memory segmentation ‰ ‰ ‰ ‰

8086 has a 20-bit address space (1MB) But can only directly address 64kB (16-bit address space) I.e. it addresses the 1MB in chunks or segments A segmented memory address location is identified with a segment and an offset address (this is the logical address) segment:offset

16 bits : 16 bits

‰ The actual physical address is calculated by shifting the segment address 4 bits to the left and adding the offset! ‰ What’s the actual physical address in the following example? Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Memory segmentation ‰

In C the address 1234:9876h is specified as 0x12349876

‰

Near and far pointers ƒ A near pointer is a 16-bit pointer (64kB of data) ƒ A far pointer is a 20-bit pointer (1MB)

char far *ptr; /* declare a far pointer */ ptr = (char far *) 0x1234567; /*initialize a far pointer */

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Memory mapped I/O vs. Isolated I/O ‰ Memory mapped I/O ƒ Devices are mapped into the physical memory space ƒ Given real addresses on the address bus

‰ Isolated I/O ƒ Devices are mapped into a special isolated memory space ƒ Accessed via ports which act as a buffer between the processor and the device ƒ Accessed using the IN and OUT instructions (there are C equivalents) ƒ Isolated I/O uses 16-bit addressing from 0000h to FFFFh

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

80x86 bus controller signals ‰ R/W ƒ Low when data is being written ƒ High when data is being read ƒ M/IO o Low when selecting isolated memory o High when selecting normal memory space

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture

Copyright © 2007 David Vernon (www.vernon.eu) Typical PC Memory Map

Microprocessor Architecture ‹

Typical isolated I/O Memory Map 000h-01Fh 020h-021h 040h-05Fh 060h-07Fh 080h-09Fh 0A0h-0BFh 0C0h-0DFh 0E0h-0FFh 170h-178h 1F0h-1F8h 200h-20Fh 210h-217h 278h-27Fh 2F8h-2FFh 300h-31Fh 378h-37Fh 380h-3AFh 3A0h-3AFh 3B0h-3BFh 3C0h-3DFh 3F0h-3F7h 3F8h-3FFh

DMA controller Programmable interrupt controller (PIC) Counter/Timer Digital I/O DMA controller NMI Reset DMA controller Math co-processor Hard disk (secondary IDE drive or CD-ROM drive) Hard disk (primary IDE drive) Game I/O adapter Expansion unit Second parallel port (LPT2:) Second serial port (COM2:) Prototype card Primary parallel port (LPT1:) SDLC interface Primary binary synchronous port Graphics adapter Graphics adapter Floppy disk controller Primary serial port (COM1:)

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Isolated I/O ‰ Inputting a byte from an I/O port ƒ Borland C unsigned char value; value = inportb(PORTADDRESS); Prototyped in dos.h

ƒ Microsoft C++ unsigned char value; value = _inp(PORTADDRESS); Prototyped in conio.h

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Isolated I/O ‰ Inputting a word from an I/O port ƒ Borland C unsigned int value; value = inport(PORTADDRESS); Prototyped in dos.h

ƒ Microsoft C++ unsigned int value; value = _inpw(PORTADDRESS); Prototyped in conio.h

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Isolated I/O ‰ Outputting a byte from an I/O port ƒ Borland C unsigned char value; outportb(PORTADDRESS, value); Prototyped in dos.h

ƒ Microsoft C++ unsigned char value; _outp(PORTADDRESS,value); Prototyped in conio.h

Copyright © 2007 David Vernon (www.vernon.eu)

Microprocessor Architecture ‹

Isolated I/O ‰ Outputting a word from an I/O port ƒ Borland C unsigned int value; outport(PORTADDRESS, value); Prototyped in dos.h

ƒ Microsoft C++ unsigned int value; _outw(PORTADDRESS, value); Prototyped in conio.h

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Serial data transmission is used for digital communication between ‰ ‰ ‰ ‰

‹ ‹ ‹ ‹

Serial communciation protocol: 1 bit at a time, sequentially Parallel transmission: 1 word at a time (i.e. n bits in parallel) Advantages of serial transmission: very simple wiring Transmission Characteristics of RS-232 ‰ ‰

‹

Sensors and computers Computers and computers Computers and periperal devices (printer, stylus, mouse, ..) One of the most widely used communication techniques to interface external equipment

maximum distance of 20 metres Maximum bit rate 19 600 bps

Alternative serial communication standards: ‰ ‰ ‰

RS-422 (up to 10 Mbps over distance of 1.2km) USB-1 & USB-2 IEEE 1394 (Firewire / iLink) Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Electrical characteristics ‰ Logic 1: -3V to -25V; typically -12V ‰ Logic 0: +3v to +25V; typically +12V ‰ Any signal in the range -3V to +3V has an indeterminate logical state ‰ Quiescent or inactive state is -12V (i.e. logic 1)

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Connectors ‰ DB25S is a 25 pin connector with full RS-232 functionality ‰ The computer socket has a female outer casing with male connecting pins ‰ The terminating cable connector has a male outer casing with female connecting pins

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Connectors ‰ DB9S is a 9 pin connector with reduced RS-232 functionality ‰ The computer socket has a female outer casing with male connecting pins ‰ The terminating cable connector has a male outer casing with female connecting pins

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Connectors ‰ Most PCs use either a 9-pin connector for the primary (COM1:) serial port and a 25-pin for a secondary serial port (COM2:), or they use two 9-pin connectors ‰ Note: the 25-pin parallel port (LPT1:) is a 25-pin female connector on the PC and male on the cable ‰ The serial connector is male on the PC and female on the cable ‰ 25-to-9 in adaptors are available

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Frame format ‰ RS-232 uses asynchronous communications ‰ Start-stop format

‰ Each character is transmitted one at a time ƒ Delay between each character: inactive time ƒ Inactive time: -12v logic level high ƒ Each character is frames by a start bit (0), 7 data bits, 1 parity bit, 2 stop bits ƒ ASCII coding is used ƒ Parity is either even, odd, none o Parity bit is set to make the total number of either even or odd (or not checked) Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Frame format ‰ Both the transmitter and the receiver need to be set to the same bit-time interval (baud rate) ‰ Since RS-232 is asynchronous, clock rates don’t have to be exactly synchronized ‰ There is an overhead in using asynchronous communication: the additional start and stop bits ‰ The advantages is that it makes communication very simple

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Example ASCII coding, even parity, 2 stop bits: 1111101000001011000001111111111111100000111111 1100011001111010100111111111111

{inactive}11111 {start bit} 0 {‘A’}1000001 {parity bit} 0 {stop bits} 11 {start bit}0 {‘p’}0000111 {parity bit} 1 {stop bits}11 {inactive}11111111 {start bit}0 {‘p’}0000111 {parity bit} 1 {stop bits}11 {inactive}11 {start bit}0 {‘L’}0011001 {parity bit} 1 {stop bits}11 Message is ‘AppL’ Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Parity ‰ Simple form of error coding ‰ A parity bit is added to transmitted data to make the number of 1s (in the data) either even (even parity) or odd (odd parity) ‰ A single parity bit can only detect an odd number of errors (why?)

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Baud Rate ‰

‰ ‰

11 bits required to send a single character (10 if one stop bits are used) Bit rate (bits/sec): actual rate at which bits are transmitted Baud rate: rate at which the signalling elements, used to represent bits, are transmitted ƒ

ƒ

‰

Since one signalling element encodes one bit, both rates are identicial However, baud rates will differ from bit rates in modem communication

Time period of each bit = 1/baud rate seconds Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Types of equipment ‰ DTE

Data Terminal Equipment

ƒ Originally applied to CRT terminals or other input devices ƒ Today, DTE mainly applies to a computer

‰ DCE

Data Communication Equipment

ƒ Originally applied to modems or similar communications equipment ƒ Still applies today

‰ A modem is a device that converts a digital signal (e.g. from an RS232 interface) to an analogue signal for transmission over a traditional telephone line (MODEM: MOdulatorDEModulator)

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 Pin

Name

Abbrev

Functionality

1

Frame Ground

FG

This ground normally connects the outer sheath of the cable to the earth ground

2

Transmit Data

TD

Data is sent from the DTE (computer or terminal) to a DCE via TD

3

Receive Data

RD

Data is send from the DCE to a DTE via RD

4

Request to Send

RTS

DTE sets this active when it is ready to transmit data

5

Clear to Send

CTS

DCE sets this active to inform the DTE that it is ready to receive data

6

Data Set Ready

DSR

Signals that the DCE is ready to communicate

7

Signal Ground

SG

All signals are referenced to the signal ground

20

Data Terminal Ready

DTR

Signals that the DTE is ready to communicate RTS and CTS have no effect is DTR is not asserted and connected to DSR

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‹

Communication between two nodes ‰ Handshaking ƒ Hardware handshaking o RTS o CTS o DTR o DSR ƒ Software handshaking o Sending special control characters X-OFF, X-On (ctrl-S, ctrl-Q) ƒ No handshaking o If no handshaking is used then the receiver must be able to read the received characters before the transmitter send more (otherwise the input buffer will be overwritten) Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Simple No Handshaking Connections ƒ note the loop-backs

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Simple No Handshaking Connections ƒ Advantage: no handshaking so fewer wires ƒ Disadvantage: o all handshaking has to be done by software (hence, more complex software) o The lack of the DTR means neither device knows whether the other device is powered up and ready for data tranfer ƒ Typically used when the devices can operate at much faster speeds than the communication channel

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Software handshaking (Note that the software must recognize the X-ON and XOFF characters and take the appropriate action)

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Hardware handshaking ƒ To transmit: o Assert Transmitter RTS (high) o Wait until Transmitter CTS high o When receiver reads from its buffer (buffer empty), Receiver RTS goes high o ⇒Transmitter CTS, goes high o Transmitter sends data

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ DTR and DSR are responsible for establishing the connection ‰ RTS and CTS are responsible for the data transfer ‰ Without an active DTR signal, the RTS and CTS signals have no effect ‰ Deactivating DTR or DSR breaks the connection

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Hardware handshaking

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Hardware handshaking

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ DTE to DCE connections for handshaking

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Typical System Connections ƒ Loop-back connections are used to test hardware (cf. program 15.1 in text) ƒ Null modem connections are used for communication (cf. programs send and receive; 15.2 & 15.3 in text)

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 ‰ Types of error in serial communications ƒ Framing error: if the receiver has detected an invalid stop bit then the received serial character does not fit into the frame that the setup data format and the setup baud rate define. Thus the receiver has detected a framing error ƒ Break error: if the reception line is at a logical low for a longer time than usual then the receiver assumes that the connection to the transmitter is broken. The transmitter usually drives the line to a logical high level as long as no data is being transferred ƒ Overrun error: if data is arriving in the receiver faster than it is read from the receiver buffer register by the CPU, then a later received byte may overwrite the older data not yet read from the buffer. ƒ Parity error

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Universal Asynchronous Receiver Transmitter (8250) ‰ UART transmits and receives characters using RS-232 ‰ 40 pin IC ƒ Connection to the microprocessor is via D0-D7 ƒ Microprocessor write: asserts DOSTR and DOSTR (high & low, respectively) ƒ Microprocessor read: asserts DISTR and DISTR (high & low, respectively)

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Universal Asynchronous Receiver Transmitter (8250) ‰ Seven registers, selected using address lines A0, A1, A2

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Universal Asynchronous Receiver Transmitter (8250) ‰ Main input RS-232 handshaking lines: RI DSR CTS

Ring Indicate Data Set Ready Clear To Send

‰ Main output RS-232 handshaking lines: RTS DTR

Ready to Send Data Terminal Ready

‰ Serial Output SOUT

‰ Serial Input SIN Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Universal Asynchronous Receiver Transmitter (8250) ‰ Clock input: XTAL1 XTAL2 BAUDOT

connect to a crystal to control the interal clock oscillator (typically 1.8432 MHz) Baud rate (clock frequency / 16N; typically 9600 Baud)

‰ Hardware interrupts: INT

‰ Reset RESET

active low Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Programming RS-232 ‰ Main registers used in RS-232: ƒ Line Control Register (LCR) ƒ Line Status Register (LSR) ƒ Transmit and Receive Buffer (TD/RD)

‰ Base Address ƒ ƒ ƒ ƒ

primary port (COM1:) 3F8h Secondary port (COM1:) 2F8h Standard PC can support up to four COM ports The base addresses are set in the BIOS memory; address of each port stored ad address locations: 0040 : 0000 (COM1:) 0040 : 0002 (COM2:) 0040 : 0004 (COM3:) 0040 : 0006 (COM4:) Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART #include #include int main(void){ int far *ptr; /* 20-bit pointer */ ptr = (int far *) 0x0400000; /* 0040:0000 */ clrscr(); printf(“COM1: printf(“COM2: printf(“COM3: printf(“COM4: return(0);

%04x\n”, %04x\n”, %04x\n”, %04x\n”,

*ptr); *(ptr+1)); *(ptr+2)); *(ptr+3));

}

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Programming RS-232 ‰ Line Status Register (LSR) ƒ Determines the status of the transmitter and receiver buffers ƒ Read-only; all bits set by hardware

ƒ Status bit S6 should be checked to see if the output buffer (TD/RD) is empty – i.e. data has been sent – before writing to the buffer Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART ‹

Programming RS-232 ‰ Line Control Register (LCR) ƒ Read/Write register ƒ Sets up communications parameters o Number of bits per character o Parity o Number of stop bits o Baud rate

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART

Line Control Register

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices - UART ‹

Programming RS-232 ‰ Line Control Register (LCR) ƒ Baud rate • C7 set high to access the Baud rate divider • (C7 set low to access the TR/RX buffer) • Set baud rate by loading 16-bit divisor N LSB (least significant byte) -> TR/RX buffer address MSB (most significant byte)-> TR/RX buffer address + 1 • Value loaded depends on crystal frequency connected to the IC Baud rate = Clock frequency / (16 * N) e.g., for 1.8432 MHz crystal frequency, 9600 baud, N = 1.8432E6 / (9600*16) = 12 (000Ch) Copyright © 2007 David Vernon (www.vernon.eu)

Serial Devices: UART

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 /*

send.c

#define #define #define

TXDATA LSR LCR

#include #include #include

*/ 0x3F8 0x3FD 0x3FB

/* included for getch /* included for inputb and outputb

*/ */

void setup_serial(void); void send_character(int ch); int {

main(void) int ch; puts("Transmitter program. Please enter text (Cntl-D to end)"); setup_serial(); do { ch=getch(); send_character(ch); } while (ch!=4); return(0);

} Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-232 void setup_serial(void) { /* set up bit 7 to a 1 to set Register address bit

*/

outportb( LCR, 0x80); /* load TxRegister with 12, crystal frequency is 1.8432MHz

*/

outportb(TXDATA,0x0C); outportb(TXDATA+1,0x00); /* Bit pattern loaded is 00001010b, from msb to lsb these are: /* Access TD/RD buffer, normal output, no stick bit /* even parity, parity on, 1 stop bit, 7 data bits outportb(LCR, 0x0A); } void send_character(int ch) { char status; /*repeat until Tx buffer empty ie bit 6 set*/ do { status = inportb(LSR) & 0x40; } while (status!=0x40); outportb(TXDATA,(char) ch); }

Copyright © 2007 David Vernon (www.vernon.eu)

*/ */ */

Serial Interfaces: RS-232 /*

receive.c

#define #define #define #include #include #include void int

TXDATA LSR LCR

*/ 0x3F8 0x3FD 0x3FB /* included for getch /* included for inputb and outputb

setup_serial(void); get_character(void);

int main(void) { int inchar; setup_serial(); do { inchar=get_character(); putchar(inchar); } while (inchar!=4); return(0); }

Copyright © 2007 David Vernon (www.vernon.eu)

*/ */

Serial Interfaces: RS-232 void setup_serial(void) { /* set up bit 7 to a 1 to set Register address bit

*/

outportb( LCR, 0x80); /* load TxRegister with 12, crystal frequency is 1.8432MHz

*/

outportb(TXDATA,0x0C); outportb(TXDATA+1,0x00); /* Bit pattern loaded is 00001010b, from msb to lsb these are: /* Access TD/RD buffer, normal output, no stick bit /* even parity, parity on, 1 stop bit, 7 data bits outportb(LCR, 0x0A); } int get_character(void) { int status; /* Repeat until bit 1 in LSR is set */ do { status = inportb(LSR) & 0x01; } while (status!=0x01); return( (int)inportb(TXDATA)); }

Copyright © 2007 David Vernon (www.vernon.eu)

*/ */ */

Copyright © 2007 David Vernon (www.vernon.eu)

Serial Interfaces: RS-422 ‹ ‹

‹

Signal levels 0 to +5V Uses differential amplifiers at both transmitting and receiving ends to achieve high noise immunity Up to 10 Mbps over distance of 1.2km

Copyright © 2007 David Vernon (www.vernon.eu)

Copyright © 2007 David Vernon (www.vernon.eu)

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

Motivation for the development of the USB ‰ Cost, configuration, and attachment of many peripheral devices to a PC creates problems ‰ Traditional interfacing (legacy systems) ƒ Peripherals mapped onto the I/O space o Although the I/O space has 64k of addressable locations (16 bits), legacy ISA bus PCs only decode 10 bit, leaving only 1k of I/O space o I/O address conflicts are common ƒ Assigned a specific IRQ (Interrupt Request line) o But there is a limited number of IRQs available (16) o Some of these are dedicated to specific devices o Some are shared (but not at the same time) ƒ Sometimes assigned a DMA (Direct Memory Access) channel Copyrightwritten © 2007 David Vernon Peacock, (www.vernon.eu) (Based in part on a summary by Craig www.beyondlogic.org)

Universal Serial Bus - USB 2.0 ‹

Motivation for the development of the USB ‰ Traditional interfacing (legacy systems) ƒ Physical limitation: o serial and parallel interfaces only support a single device each o Only solution is to add additional (expensive) expansion cards ƒ Usability o Too many connectors and/or cables o System must be shut down to attach most peripheral o System must be restarted to install/load software

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

USB Design Goals ‰ ‰ ‰ ‰ ‰

Single connector type for any peripheral Ability to attach many peripherals Ease system resource conflicts Hot plug support (hot-swapable) Automatic detection and configuration (plug-and-play) ƒ Dynamically loadable and unloadable drivers o Plug in device o Host detects device o Host interrogates device o Host loads appropriate driver

‰ ‰ ‰ ‰ ‰

Low-cost for both PC and peripheral Enhanced performance Support for new peripheral designs Support for legacy hardware and software Low-power implementation Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹ ‹

650 pages in the definition of the USB 2.0 specification (see www.usb.org) USB 1.1 supported two speeds: ‰ Full speed 12 Mbit/s ‰ Low speed 1.5 Mbits/s ƒ Less susceptible to EMI (electromagnetic interference) ƒ Can use cheaper components

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USB 2.0 supports 480 Mbits/s ‰ High speed ‰ Competes with IEEE 1394 (Firewire) serial bus

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

USB is host controlled ‰ Only one host per bus ‰ Host is responsible for ƒ undertaking all transactions ƒ Scheduling bandwidth ƒ Data can be sent by one of several transaction methods using a token-based protocol

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USB uses a tiered star topology ‰ Devices/peripherals can’t be daisy-chained ‰ Need a hub ƒ Some peripherals have in-built hubs (e.g. keyboards) ƒ You can plug other devices into these

‰ Up to 127 devices can be connected to any one USB at any one given time Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

USB host controller specifications (USB 1.1) ‰ UHCI (Universal Host Controller Interface) ƒ Developed by Intel ƒ More work is done in software ƒ Hence cheaper hardware

‰ OHCE (Open Host Controller Interface) ƒ Developed by Compaq, Microsoft, and National Semiconductor ƒ More work done in hardware ƒ Hence simpler software!

‰ USB 2.0 ƒ EHCI (Enhanced Host Controller Interface)

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

USB Transfer modes ‰ ‰ ‰ ‰

Control Interrupt Bulk Isochronous ƒ Allows a device to reserve a defined amount of bandwidth with guaranteed latency ƒ Ideal for audio or video ƒ Avoids dropped frames due to congestion

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

Connectors Upstream connection to the host Downstream connection to a device Not interchangeable Type A plugs (and sockets) always face upstream to the host ‰ Type B plugs (and sockets) always face downstream to the peripheral device ‰ USB 2.0 includes mini-USB B connectors ‰ ‰ ‰ ‰

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

Connectors

Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

Electrical Characteristics ‰ USB uses a differential transmission pair for data ‰ Differential ‘1’ is transmitted by ƒ Pulling D+ over 2.8V ƒ Pulling D- under 0.3V

‰ Differential ‘0’ is transmitted by ƒ Pulling D- over 2.8V ƒ Pulling D+ under 0.3V

‰ The polarity of the signal is inverted depending on the speed of the bus ƒ Use ‘J’ and ‘K’ to signify logic levels ƒ ‘J’ is differential 0 in low speed ƒ ‘J’ is differential 1 in high speed Copyright © 2007 David Vernon (www.vernon.eu)

Universal Serial Bus - USB 2.0 ‹

Electrical Characteristics ‰ USB also uses single ended outputs (on D+, D-, or both) ‰ For example: ƒ Single Ended Zero (SE0) ƒ Used to signify a device reset if held for more than 10mS ƒ Generated by holding both D- and D+ low (