Control and Modulation Strategies for Modular Multilevel Converter based HVDC System Minyuan Guan and Zheng Xu Hairong Chen College of Electrical Engineering, Zhejiang University, Hangzhou, P.R. China Jinhua Polytechnic, Jinhua, P.R.China E-mail:
[email protected],
[email protected] E-mail:
[email protected] Abstract- The modular multilevel converter (MMC) is a new kind of voltage source converter (VSC) with a high number of voltage levels and considered to be suitable for HVDC transmission. Based on circuit configuration and operation mechanism, this paper presents an mathematical model of MMC. Then the vector control strategy widely used in two-level VSC is applied to the control of MMC. Due to modular structure and cascaded connections, a very high number of voltage levels is obtained by MMC in HVDC applications, for which the nearest level modulation (NLM) become feasible. A combination of NLM and optimized capacitor voltage balancing control is presented to reduce the switching frequency as well as the switching losses of power semiconductors. Time-domain simulation performed in PSCAD/EMTDC shows that the control and modulation methods provide good steady-state and dynamic system performance and significantly reduce the switching frequency of power semiconductors.
I.
INTRODUCTION
V
SC-HVDC based on self-commutated voltage source converters is an attractive technology, by which fast independent control of real and reactive power are realized [1]-[2]. There are several VSC topologies, two-level and multilevel VSCs, available for HVDC application [1]-[4]. Conventional multilevel VSCs, such as the neutral-pointclamped (NPC) converter [5] and the flying capacitor (FC) converter [4], encounter difficulties in increasing the number of voltage levels [6]. Recently, two-level converter and threelevel NPC converter have been utilized in VSC-HVDC [1]. However, the output voltage waveform of converters with a low number of voltage levels is far away from sinusoidal [2], [7]. Moreover, series connections of multiple semiconductors are required to enable high blocking voltage of converter arms. To ensure uniform voltage distribution not only statically but also dynamically, all semiconductors connected in series have to switch simultaneously with the accuracy in the microseconds range [2]. To avoid these problems, the modular multilevel converter (MMC), based on half-bridge cascaded connections, is proposed in [8]-[9]. MMC is well scalable to high-voltage levels of power transmission by cascade connection of multiple sub-modules (SMs) per arm [9], and direct connection of multiple power semiconductors may be avoided [10]. Furthermore, a high number of voltage levels is achieved due to increases in the number of cascaded connections, which provides high-quality output voltage [10].
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This paper reports our recent studies on MMC based HVDC system, and is organized in the following way. In Section II， the mathematical model of MMC is presented. Then the vector control, widely used in conventional VSCs, is introduced to the control of MMC. Section III describes the nearest level modulation methods and the optimized capacitor voltage balancing control, by which the switching frequency and switching losses of power semiconductors are reduced. Case studies are provided in Section IV where simulation results are presented. Finally, conclusions are drawn in Section V. II.
MODELING AND CONTROL
A. Basic Principals Fig. 1 depicts the circuit configuration of a MMC, with “o” representing the reference point of zero voltage potential. The converter topology consists of six converter arms where each arm contains a series connection of n nominally identical SMs and a converter reactor 2L [2]. The upper arm and the lower arm in one phase comprise a phase-unit. One submodule contains an IGBT half bridge as switching element and a storage capacitor [2]. Due to its modular design, the MMC is well scalable and flexible in structure. There are three different switching states relevant for the proper operation of a SM [10-11]:
IdP ua1 ap
Ud bn
an
ua 2
cp
bp
ua ub uc
Ud 2
uc1
ub1
ub 2
cn
o
Ud 2
uc 2
N Fig. 1. Circuit configuration of MMC
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ON-State: The upper IGBT is switched on, while the lower switched off. Thus, the capacitor voltage is applied to the terminal of the SM, and the charging or discharging of the capacitor depends on the current flow direction. OFF-State: The upper IGBT is switched off, while the lower switched on. Thus, zero voltage is applied to the terminal of the SM. BLOCK-State: This state with both IGBTs blocked may occur during startup or in series failure conditions. Via the alternation of ON-State and OFF-State, the output voltage of an individual SM is under control. Usually, the SMs at ON-State in one phase-unit are half of all the SMs in each phase unit [7]. By dividing them between the upper and lower arms, n+1 output voltage levels are available at the AC terminal [2]. In conventional three-phase AC/DC converters, each phase is connected to the grid side through one converter reactor. The converter reactors provide the connection of power exchange between the grid and the converter. In MMC, six converter reactors are required to connect six converter arms to the grid. Thus, the control strategies for conventional AC/DC converters can not be directly used in the control of MMC. B. Mathematical Model Fig. 2 illustrates the schematic diagram of a phase-unit. The inductance of an arm reactor is 2L, and the equivalent arm resistor is represented by 2R.
ik1
SM1
uk1 uk ik
Ud 2
SM 2
kp
SM n
Ud
ikdif kn
uk 2 ik 2
SM1
SM 2
SM n
o
ik 2
Ud di uk1 ) 2 L k1 2 Rik1 , 2 dt U di uk (uk 2 d ) 2 L k 2 2 Rik 2 . 2 dt uk (
dik Rik , dt u uk 1 . where vk k 2 2 uk vk L
(5) (6)
Subtracting (4b) from (4a) and after substituting the currents derived in (2) and (3), we obtain
(uk1 uk 2 ) U d 4 L
dikac 4 Rikac 4 RI kdc . (7) dt
The dominant ripple component of (uk1+uk2) is at double line-frequency, so ikac is considered at double line-frequency [11-13]. Thus, the phase current ik is almost equally divided between the upper and lower converter arms. The Ikdc is expressed as
I kdc
U k I k cos I dc . 2U dc 3
(8)
where Uk and Ik represent the amplitudes of phase voltage and current, is the phase-angular difference between phase voltage and current, and Idc represents the total DC current at converter DC-side. So the Idc is almost equally divided into three phase-units under balanced grid condition.
Ud 2
dia (t ) L dt ua va Ria dib (t ) ub vb Rib L dt L dic (t ) u v Ri c c c dt
(1)
(9)
Applying the dq0 transformation defined in [14] to (9) yields
did L dt ud vd L iq Rid . di q L uq vq L id Riq dt
(2)
The differential current ikdif can be decomposed into DC component Ikdc and AC component ikac. According to (1) and (2), the upper and lower arm currents are described by
ik I kdc ikac , 2
(4b)
C. Controller Design The MMC ac-side dynamics are described by (9), which resembles the conventional VSCs (e.g., two-level converter). Thus, the vector control design of the VSCs, which has been reported in many literatures [14-16], can be applied to MMC.
Defining the differential current ikdif as [12]
ik1
(4a)
The sum of (4a) and (4b) divided by 2 is
The phase current in phase-k (k=a, b, c) is expressed as
ikdif (ik1 ik 2 ) 2 .
(3b)
The upper and lower arm currents are determined by [12]
Fig. 2. Schematic diagram of a phase-unit.
ik ik 1 ik 2 .
ik I kdc ikac . 2
(3a)
850
(10)
where is the system angular frequency. In steady-state uq is zero, and the real and reactive power flows from the ac-side to the converter can be expressed as [14-16] (11a) P 1.5u d id ,
Q 1.5u d iq .
(11b)
The vector control can be divided into the inner loop current control and the out loop control. The inner loop current control is to regulate id and iq at their reference values, denoted by id* and iq*, by adjusting the output voltage references of the converter.
vd* ud Liq [k p1 (id* id ) ki1 (id* id )dt ] vq* u q Lid [k p 2 (iq* iq ) ki 2 (iq* iq )dt ]
The out loop control is to calculate reactive power references.
id*
and
iq*
(12a) (12b) by real and
id* P* / 1.5ud [k p 3 ( P* P) ki 3 ( P* P )dt ] (13a)
iq* Q* / 1.5u d [k p 4 (Q Q * ) ki 4 (Q Q* )dt ] (13b)
If the converter is assigned to control the DC voltage, (13a) should be replaced by (14). (14) id* [k p 5 (U d* U d ) ki 5 (U d* U d )dt ]
conditions [18]. This method is complex for converters with a very high number of voltage levels due to the increase of switching angles [18], and slow in dynamic response. The NLM takes advantage of the very high number of voltage levels by approximating the voltage reference to the closest generable voltage level of the converter [18-19]. Since the number of cascaded connections, hence the number of voltage levels, is very high in MMC for HVDC transmission, NLM become possible. B. NLM for MMC In Fig. 2, there are n, usually even number, SMs in one converter arm and 2n SMs in one phase-unit. Let UC represents the average capacitor voltage of all the SMs in phase-k, where k=a, b, c. Let vk* represents the instantaneous modulation waveform reference for phase-k, while vk is the output voltage of phase-k. Let np and nn represent the number of SMs switched at ON-State in the upper arm and the lower arms, respectively. (15) 0 n p , nn n The constraints of (15) need to be satisfied and the output voltage of the phase-k can be expressed as
The overall control block diagram is shown in Fig. 3. Ud u * d
i
U d*
P
2 3ud
P* Q Q*
d
2 3ud
id iq iq*
L L
* d
v
vq*
vk
If the capacitor voltage ripples are ignored, nn and np can be calculated as [19]
uq
MODULATION AND CAPACITOR VOLTAGE BALANCING
A. Modulation Methods for MMC Three-phase sinusoidal modulation waveforms va*, vb*, vc*, which are the references for the converter output voltage, are recovered from vd*, vq* by the inverse dq0 transformation defined in [14]. The modulation methods used in multilevel converters can be classified as PWM methods at high switching frequency and staircase modulation methods at low switching frequency [17-19]. Staircase modulation methods can be adopted by converters with a high number of voltage levels due to the strong reduction in the switching frequency and the switching losses of power semiconductors [18]. Representatives of staircase modulation methods are the multilevel selective harmonic elimination [17] and the nearest level modulation (NLM) [18-19]. In multilevel selective harmonic elimination methods, switching angles are computed offline and stored in tables, which are then interpolated according to the operating
(16)
To stabilize the DC-side voltage, the following equation should be satisfied. (17) n p nn n
Fig. 3. Block diagram of the controllers.
III.
uk 2 uk1 (nn n p ) UC . 2 2
nn
n v* f ( k ), uC 2
(18a)
np
n v* f ( k ), uC 2
(18b)
where f(x) is the nearest integer of x. If the n SMs at ONstate in one phase-unit are equally divided between the upper and the lower arms, the output voltage of this phase unit is nearly zero. With the rising of vk*, nn will increase and np will decrease accordingly to maintain the difference of vk and vk* within ±UC/2. C. Optimized Capacitor Voltage Balancing Control A balancing control of sub-module capacitor voltages is required for MMC. NLM determines the numbers of SMs to be switched at ON-State in the upper and lower arms (e.g., np and nn). For a specified number of SMs in the upper and lower arms, there are several switching combinations [11]. A direct capacitor voltage balancing control is adopted by many literatures on MMC [2], [11], in which the capacitor voltages in one converter arm are sorted and specified SMs are switched at ON-State at every switching instance according to the sorting results and the directions of the arm currents. It can be achieved as the following steps: Firstly, the individual 851
capacitor voltages in each converter arm are sorted. Then, the directions of current flow in each converter arms, which determine the charging or discharging of SM capacitors, are identified. Thirdly, the SMs have lower capacitor voltages or the ones have higher capacitor voltages in each arms are switched at ON-State at every switching instance according to the charging or discharging period. The direct capacitor voltage balancing control has desired dynamic performance. But it takes no account of the requirement to reduce switching frequency, which will result in high switching losses. Here, the direct capacitor voltage balancing control is optimized by adjusting the measured SM capacitor voltages before the sorting process. It focuses on the SMs whose capacitor voltages exceed the voltage limits, while the switching states of the other SMs are maintained to some extent by employing the maintaining factor [20]. It is illustrated in Fig. 4, and described as follows [20]: 1) Discharging Period: If the current flow in the arm is in discharging period, the SMs with higher capacitor voltages are required to be switched at ON-State in next switching instance. Then, the capacitor voltages of the OFF-State SMs whose capacitor voltages are above upper voltage limit and the capacitor voltages of the ON-State sub-modules are multiplied by the maintaining factor (larger than 1) to increase their possibilities to be switched at ON-State in next switching instance. Accordingly, the possibilities of the other SMs to be switched at OFF-State are increased. 2) Charging Period: If the current flow in the arm is in charging period, the SMs with lower capacitor voltages are required to be switched at ON-State in next switching instance. Then, the capacitor voltages of the OFF-State SMs whose capacitor voltages are above lower voltage limit are multiplied by the maintaining factor (larger than 1) to increase their possibilities to be switched off at next switching instance. Accordingly, the possibilities of the other SMs to be switched at ON-State are increased.
IV.
CASE STUDIES
A. Simulation System The simulation studies are performed in time-domain by the PSCAD/EMTDC software. The schematic diagram of the MMC based HVDC transmission system for simulation is shown in Fig. 5, in which two MMC converters are connected via DC cables, and two AC terminals are modeled as threephase ideal voltage sources in series connection with an resistor of 0.1 .
Fig. 5. Schematic diagram of the MMC-HVDC simulation system
The parameters of the simulation system are listed in TABLE I. The control and modulation methods described above are implemented in the simulation system. The rectifier station controls the real and reactive powers exchanging with the sending end AC system, while the inverter station regulates the DC voltage at 60 kV and the reactive power exchanging with receiving end AC system. TABLE I PARAMETERS OF THE STUDIED SYSTEM
n p / nn
UC
Quantity
Value
Nominal dc voltage
+/- 30 kV
SMs per arm
48 SMs
Nominal capacitor voltage
1.25 kV
Nominal apparent power
20 MVA
AC system source voltage
35 kV
AC system nominal frequency
50 Hz
Transformer voltage rating
Yn, 36 kV/31 kV
Transformer power rating
20 MVA
Transformer leakage inductance
1%
Arm inductance 2L
60 mH
Sub-module capacitor
4700 uF
DC cables
10 km
Fig. 4. Block diagram of optimized capacitor voltage balancing control.
The objective of the optimized capacitor voltage balancing control is to regulate the exceeding-limits capacitor voltages rapidly. For the other sub-modules whose capacitor voltages are within the voltage limits, their switching states are maintained to some degree to reduce switching frequency of power semiconductors [20]. Therefore, the switching losses can be reduced, without noticeable increase in the magnitudes of capacitor voltage ripples.
B. Case Studies 1) Dynamic Performance: To investigate the command tracking performance of the system, references of real and reactive power at rectifier station are stepped from 18 MW to 12 MW and 0 MVar to -6 MVar, at t= 0.3s, respectively. The maintaining factor is chosen to be 1. Fig. 6 and Fig. 7 show the dynamic response of the system to the changes in real and reactive power commands.
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Ud* Ud 0.3
0.4
0.5
0.4
0.5
0.4
0.5
Q* Q 0.3
40 20 0 -20 -40 0.2
0.3
0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 0.2
0.3
(b)
(c)
Current (kA)
Voltage (kV)
(a)
Q (MVar)
P (MW)
0.4 0.5 (d) Time (s) Fig. 6. System response at the inverter side: (a) DC voltage, (b) Reactive power, (c) AC voltages and (d) AC currents. 18 16 14 12 10 0.2
Voltage (kV)
TABLE II AVERAGE SWITCHING FREQUENCY OF POWER DEVICES AND MAXIMUM CAPACITOR VOLTAGES RIPPLES AT DIFFERENT MAINTAINING FACTORS
MAINTAINING F (HZ) FACTOR 1.00 1123 1.01 284 1.02 144 1.03 108 1.04 100 1.05 78
P* P 0.3
(a)
0.4
0.5
0.4
0.5
0
Q*
-4 -8 -12 0.2
Current (kA)
reactive powers as well as the DC voltage to track their reference values within a short period of time. The steadystate errors of the control system are small. Desired dynamic performance is achieved by the controllers. 2) Capacitor Voltage Balancing: Different maintaining factors are selected to evaluate the performance of the optimized capacitor voltage balancing control. The average switching frequency of power devices and the maximum capacitor voltage ripples from t=0.4s to 0.5s at the inverter side are calculated in Table II. The upper and lower voltage limits are set at 1.35kV and 1.15kV. Fig. 8 shows the capacitor voltage ripples of one SM at three different maintaining factors (e.g., 1.00, 1.02, and 1.04). The capacitor voltage ripples is increased and the average device switching frequency is reduced with the increasing of maintaining factor. As the maintaining factor increases from 1.00 to 1.02, the average switching frequency is reduced significantly while the capacitor voltage ripples is not increased noticeably. With the further increasing in the maintaining factor, the average switching frequency is reduced slowly. By selecting an appropriate maintaining factor (e.g., 1.02), the average device switching frequency can be significantly reduced without noticeably increasing the capacitor voltage ripples.
40 20 0 -20 -40 0.2 0.4 0.2 0.0 -0.2 -0.4 0.2
Q 0.3
0.3
(b)
(c)
0.4
0.5
Voltage (kV)
Q (MVar)
Voltage (kV)
64 62 60 58 56 0.2 2 1 0 -1 -2 0.2
1.4 1.3
2.40 5.95 4.85 6.38 9.89 6.77
-4.77 -3.92 -4.98 -4.70 -3.33 -5.48
1.00 1.02 1.04
1.2 0.40
0.42
0.44
0.46
0.48 0.50 Time (s)
Fig. 8. Simulated waveforms of one SM capacitor voltage at different maintaining factor.
V. 0.3
POS (%) NEG (%)
0.4
0.5 (d) Time (s) Fig. 7. System response at the rectifier side: (a) Real power, (b) Reactive power, (c) AC voltages and (d) AC currents.
Fig. 6(a) and Fig. 6(b) show the DC voltage and reactive power responses at the inverter side, Fig. 6(c) and Fig. 6(d) are the corresponding changes of AC voltages and currents at the inverter side. Fig. 7(a) and Fig. 7(b) show the real and reactive power responses at the rectifier side, Fig. 7(c) and Fig. 7(d) are the corresponding changes of AC voltages and currents at the rectifier side. The controllers regulate real and
CONCLUSION
The circuit configuration and operation mechanism of MMC are described, and then the mathematical model of MMC is deduced. Based on the derived model, the vector control widely used in two-level VSC is directly applied to MMC, by which an independent control of real and reactive power can be achieved. A high number of cascaded connections is required in MMC used for HVDC transmission, which associates with a high number of converter output voltage levels. Thus, NLM become feasible for MMC. Moreover, an optimized capacitor voltage balancing control is combined with NLM. The optimized capacitor voltage balancing control regulates the exceeding853
limits capacitor voltages rapidly. For the other SMs whose capacitor voltages are within the voltage limits, their switching states are maintained to some degrees. Therefore, the switching frequency and switching losses of the power devices can be reduced, without noticeable increase in the magnitudes of capacitor voltage ripples. By the simulation studies performed in PSCAD/EMTDC, the effectiveness of the control and modulation methods is validated.
[20] M. Guan, Z. Xu, “Optimized Capacitor Voltage Balancing Control for Modular Multilevel Converter Based VSC-HVDC System,” Proceedings of the CSEE, vol. 31, pp. 9-14, Apr. 2011. (in Chinese)
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