Control Design Strategy for Flying Capacitor Multilevel ... - IEEE Xplore

1728

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 3, MARCH 2016

Control Design Strategy for Flying Capacitor Multilevel Converters Based on Petri Nets Fernando Salinas, Mario A. González, Miguel F. Escalante, Member, IEEE, and Jesús de León Morales

Abstract—Multilevel power converters belong to a class of hybrid systems, where continuous and discrete variables coexist, representing a challenge for their control design. Flying capacitor multilevel converters require controlling the flying capacitor voltages and the output current. In this regard, several works have studied this problem. However, the discrete nature of the converter has not been directly included in the control design. In this paper, a hybrid representation of the converter is considered, and using Petri net (PN) methodology, a control scheme is proposed to regulate the flying capacitor voltages and the output current. An analysis of stability, using Lyapunov method, is presented, and sufficient stability conditions are obtained. From these conditions, the commutation rules are defined and used to define the transition rules for the PNs. Experimental results validate the performance of the proposed scheme. Index Terms—Hybrid systems, multilevel converters, Petri nets (PNs).

I. I NTRODUCTION

M

ULTILEVEL power converters represent a class of hybrid dynamical systems where voltages and currents are continuous variables, whereas the power semiconductor states are discrete in nature, representing a challenge for the control design in these systems. A converter belonging to this class of hybrid systems is the flying capacitor multilevel converter (FCMC). FCMC operation requires the regulation of flying capacitor voltages and output current. Several control strategies have been proposed to solve the capacitor voltage regulation problem, i.e., in open loop [1]–[7] and closed loop [8]–[18]. Furthermore, some proposed closed-loop strategies address also the output current regulation [19]–[26]. However, most of these control strategies are mainly based on classical control methodologies, which do not take into account the discrete nature of the FCMC. From this perspective, it seems

Manuscript received March 19, 2015; revised July 25, 2015; accepted August 31, 2015. Date of publication October 26, 2015; date of current version February 8, 2016. This work was supported by the CONACYT, UANL-PAICYT, and PROMEP DSA/103.5/15/6797 research funding programs. The authors are with the Department of Electrical Engineering, Facultad de Ingeniería Mecánica y Eléctrica, Universidad Autónoma de Nuevo León, 66451 San Nicolás de Los Garza, Mexico (e-mail: [email protected]; [email protected]; mescalante@ ieee.org; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2015.2494535

appropriate to model and analyze the power converter using approaches that take into account its hybrid behavior. In this sense, there exist two formalisms to model such systems. The first one is the conventional approach that models the hybrid system using state machines, in which the discrete and the continuous parts are decoupled. This approach requires an exhaustive and explicit enumeration of all the system states. The second one, known as Petri nets (PNs), is an alternative to automata models [27]. PNs incorporate additional analysis tools for an efficient solution of the control problem and do not require to enumerate explicitly the state space [28]. In this regard, the hybrid systems theory has been incorporated in the analysis of many industrial processes, making it possible to describe the complete dynamic, including discrete events. Indeed, PNs have been used to model and analyze discrete event systems [29]–[31]. Several studies propose PNs to control industrial processes [32], [33], to model warehouse systems [34], and to develop design software for hybrid dynamical systems [35]. Furthermore, there are some proposals in the field of power systems; see, for instance, [36] and [37]. Regarding applications in power electronics, PNs have been proposed as a modeling tool for classical converters [38] and, in some works, to implement the control loops [39]–[43]. In [39] and [40], PNs are used to model and control a parallel multicellular converter, and in [41]–[43], PNs are applied to the FCMC. In [41] and [42], a PN with one place representing each converter state is used to regulate the capacitor voltages while the number of commutation is minimized. In [43], two PNs are proposed to control the capacitor voltages and the output current of a four-level FCMC. The number of states in an FCMC rapidly grows when the number of levels is increased; thus, PNs offer an alternative for modeling and controlling this converter. On one hand, PNs have attractive properties: They allow a compact representation of the system (i.e., it does not require an exhaustive enumeration of all the states), and the interaction between continuous and discrete variables is easily handled. On the other hand, conventional techniques used in control system design can be applied to configure the PN transition rules and to study the system stability. In this paper, using a hybrid model to describe the dynamical behavior of an n-level FCMC, a control strategy based on two PNs is proposed to regulate simultaneously the capacitor voltages and the output current. Furthermore, sufficient conditions ensuring the stability of the closed-loop system are obtained. From these conditions, the converter switching state is decided, such that it allows regulating, simultaneously, the capacitor voltages and the output current.

0278-0046 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

SALINAS et al.: CONTROL DESIGN STRATEGY FOR FCMCs BASED ON PNs

1729

TABLE I F IVE -L EVEL C ONVERTER VARIABLES A SSOCIATED W ITH E ACH SDD

Fig. 1. Basic power structure for an n-level FCMC.

This paper is organized as follows. The FCMC system description and its mathematical model are introduced in Section II. Then, in Section III, the hybrid control based on PNs is presented. Section IV presents the obtained experimental results, which validate the proposed scheme. Finally, in Section V, the conclusions are given.

II. S YSTEM M ODELING AND D ESCRIPTION In this section, the hybrid dynamical model of an n-level FCMC is established. The FCMC basic power structure, associated with a resistive–inductive (R−L) load, is shown in Fig. 1. It consists of (n − 1) commutation cells, where each commutation cell is composed of two complementary switches (Tk and Tk , i.e., if Tk : on → Tk : off), and a flying capacitor Ck or the fixed input voltage E. Its dynamical behavior is described by vo =

n−1

vCk − vC(k−1) Sk

(1)

which represents a hybrid dynamical system, where x = (is , vC1 , . . . , vCn−2 )T is the state vector, and ⎡

Aqi

k=1

iCk = (Sk+1 − Sk )is ,

for k = 1, . . . , n − 2

⎢ ⎢ ⎢ ⎢ =⎢ ⎢ ⎢ ⎣

(2)

−R L

(S2 −S1 ) C1 (S3 −S2 ) C2

.. .

(Sn−1 −Sn−2 ) Cn−2

(S1 −S2 ) L

Sk =

1 0

if Tk switch is on, for k = 1, . . . , n − 1 if Tk switch is off, for k = 1, . . . , n − 1.

k E, n−1

for k = 1, . . . , n − 2.

(Sn−2 −Sn−1 ) ⎤ L

..

···

. ···

0 .. . .. . 0

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

T 0 0

···

0

qi corresponds to a specific discrete driving (SDD), and

Sk = {0, 1} for k = 1, . . . , (n − 1)

(6) (7)

where Q is the set of all SDDs. Furthermore, subset Qα ⊂ Q is the subset that contains all SDDs of level α defined as α=

n−1

Sk .

(8)

k=1

(4)

The dynamical model of the FCMC in state-space representation is given by x˙ = Aqi x + Bqi E

··· ···

Q = Sn−1 × · · · × S2 × S1 (3)

with S k being the complement of Sk . Proper and safe converter operation is obtained when the output voltage is composed of equal magnitude voltage levels, and the input voltage is equally distributed in the power semiconductors. This is achieved if vCk =

Bqi

Sn−1 = L

··· .. .

0 .. . .. . 0

where vo is the output voltage, vC(n−1) corresponds to the input voltage E, and vCk and iCk are the voltage and current at kth capacitor, respectively (vC0 = 0). Switching function Sk is defined as

(S2 −S3 ) L

(5)

Furthermore, we assume that all the components of the state vector are measurable, i.e., Aqi ∈ Rm×m , Bqi ∈ Rm×1 (with m = n − 1), and qi represents each possible converter switching state, with i = 0, 1, . . . , (|Sm | · · · · · |S2 | · |S1 |) − 1). The FCMC variables associated to each SDD are defined in Table I for a five-level converter.

1730


TABLE II R ESULTING E QUATIONS W HEN (12) I S E VALUATED FOR E ACH qi , FOR n = 5

Fig. 2. PN control scheme for capacitor voltages and output current regulation.

III. H YBRID C ONTROL B ASED ON PN S The proposed control scheme is based on two cascaded PNs, as shown in Fig. 2. The first PN implements the output current regulation, assigning the required voltage level, whereas the second one is designed to control the FCMC with the SDD that ensures the voltage level required by the current regulation loop and regulates the capacitor voltages, simultaneously. A. SDD Control Properties The selected SDD must ensure both control objectives (i.e., output current regulation and capacitor voltages’ regulation). Therefore, the SDD is determined by considering its control properties. In order to study the control properties of each SDD, let the output current error be defined as ei = is − i∗

(9)

and the capacitor voltage errors be defined as ∗ ek = vCk − vC , k

k = 1, 2, . . . , n − 2

(10)

∗ is the kth capacitor reference voltage defined in where vC k (4), vCk is the actual kth capacitor voltage, and is and i∗ are the output and reference currents, respectively. The following proposition establishes the conditions under which ei and ek , for k = 1, 2, . . . , n − 2, converge to zero. Proposition 1: Consider system (5) under the action of an SDD, i.e., qi for i = (0, 1, . . . , 2n−1 − 1). Then, for any initial condition of system (5), there exists an SDD such that the capacitor voltages vCk for k = 1, . . . , n − 2 and output current is converge to their reference values. Proof: Consider the following Lyapunov function:

1 1 Ck e2k + Le2i 2 2

The sufficient conditions ensuring V˙ ≤ 0 are determined by substituting each SDD in (12) and then finding the conditions under which each term in (12) is less than or equal to zero. This ends the proof. Table II summarizes the equations obtained when Proposition 1 is applied to a five-level FCMC, where each entry in Table II corresponds to (12) evaluated with each SDD, qi and i = 1, . . . , 15, for n = 5. From these equations, sufficient conditions for convergence are obtained and used to design the control strategy for the five-level FCMC.

B. Output Current Regulation The current regulation strategy design assumes that the capacitor voltages are regulated as established in (4). Then, the conditions required in (12) for the output current convergence (i.e., term associated to ei ≤ 0) are obtained by considering the maximum reachable current for each voltage level in steady state. The maximum reachable current issα for voltage level α is given by issα =

αE , R(n − 1)

α = 0, 1, . . . , (n − 1).

(13)

n−2

V =

(11)

k=1

where the first term in (11) is associated with the capacitor voltage errors, and the second one is associated with the output current error. Taking the time derivative of (11) and replacing the suitable expressions, we obtain V˙ = e1 (S2 −S1 )+e2 (S3 −S2 )+· · ·+en−2 (Sn−1 −Sn−2 )] is + ei [−Ris + (S1 − S2 )vC1 + (S2 − S3 )vC2 + · · · + (Sn−2 − Sn−1 )vCn−2 + Sn−1 E . (12)

In addition, it is desirable that the voltage level change will take place only between adjacent voltage levels. This is ensured if the voltage level is selected considering the amplitude of the reference current with respect to the maximum reachable current imax given by (13) when α = (n − 1). Thus, (n − 1) operating regions OR(i∗ ) are defined in terms of the reference current i∗ . The actual OR(i∗ ) is identified by testing the following condition: if

j−1 j imax ≤ i∗ ≤ imax =⇒ OR(i∗ ) = j n−1 n−1

(14)


1731

TABLE III P LACES ’ D EFINITION FOR THE C URRENT R EGULATION PN

TABLE IV T RANSITION R ULES FOR THE C URRENT R EGULATION PN

Fig. 3. (a) Applied voltage level α as a function of the reference current i∗ for a five-level FCMC. (b) PN for current regulation.

where imax = E/R and j = 1, . . . , (n − 1). Then, the required voltage level is ⎧ ∗ ⎪ if is < i∗ ⎨OR(i ), ∗ αk (i ) = αk−1 , (15) if is = i∗ ⎪ ⎩ ∗ ∗ OR(i ) − 1, if is > i . Fig. 3(a) illustrates the operating regions defined by (14) and the required voltage level for the output current regulation in a five-level FCMC. 1) PN for Current Regulation: PNs are composed of places, transitions, and directed arcs. Directed arcs connect places to transitions or transitions to places, and places are used to represent conditions to enable various events. Thus, a PN is represented by a transition together with an input place and an output place. A transition ti−j represents a transition from place i to place j. In addition to this, the dynamic behavior of a given system using PNs is captured by the presence of tokens at each place; each place may hold either none or a positive number of tokens. The presence or absence of a token in a place serves to validate if a condition associated to that place is true or false. A transition is enabled when there is a token at its input place, and when the transition is fired, a token is removed from the input place and assigned to the output place. The PN for the output current regulation of a five-level FCMC is shown in Fig. 3(b), and its places are defined in Table III. It has five places (or states) that represent the actual voltage level. In this PN, the token is moved to the place corresponding to the required voltage level. The rules that fire the transition ti−j , to

transfer a token from place pi to place pj , are obtained from (14) and (15) and are summarized in Table IV. Under this control scheme, the output current is regulated around its reference value; the peak-to-peak current ripple is approximated by Δio =

ΔE fc · L

(16)

where ΔE is the voltage difference between two adjacent voltage levels (i.e., E/4 for a five-level FCMC), fc is the frequency at which the current control loop is executed, and L is the output inductance. C. Flying Capacitor Voltage Regulation Once the required voltage level for the output current regulation is determined by the first PN, a second PN decides the SDD that ensures the required voltage level and regulates

1732


TABLE V C ONDITIONS FOR C APACITOR VOLTAGE C ONVERGENCE

Step 4) If still more than one SDD exists, then choose the SDD that reduces errors by increasing the capacitor voltages. This will ensure safe operation in case of an increase in the input voltage. The transition rules for the five-level FCMC are summarized in Table VI. Under this scheme, the kth capacitor maximum peak-to-peak voltage ripple is given by ΔVCk = 2

Iomax fp2 · Ck

(17)

where Iomax is the maximum output current, Ck is the kth capacitor capacitance, and fp2 is the frequency at which the PN for the capacitor voltage regulation is executed. IV. E XPERIMENTAL R ESULTS

Fig. 4. PN and places’ definition for capacitor voltage regulation.

the capacitor voltages, simultaneously. The SDD is selected from the set of redundant states corresponding to the requested voltage level. For a five-level FCMC, the capacitor voltage regulation is achieved if the capacitor voltage errors in (12) (i.e., terms associated to e1 , e2 , and e3 ) are less than or equal to zero.Table V shows each SDD and the conditions under which a given SDD can be selected to achieve the capacitor voltage regulation. In Table V, the symbol (−) means that no change is taking place in the associated capacitor voltage at that particular SDD, whereas ej → 0 means that error voltage in the jth capacitor tends to zero. 1) PN for Capacitor Voltage Regulation: Fig. 4 shows this PN and defines its places for a five-level FCMC, where its places represent the commutation cells’ states; place p5 represents the OFF state for all switches, and place pi , for i = 6, . . . , 9, represents the ON state for commutation cells 1–4, respectively. The rules to fire a transition ti−j to transfer a token from place pi to place pj (i.e., turn ON or turn OFF a commutation cell) are obtained from the following procedure. Procedure: Step 1) Choose the subset Qα from (6), ensuring the desired voltage level α. Step 2) Select an SDD ∈ Qα , such that it reduces the error in the capacitor voltages (see Table V). Step 3) If more than one SDD exists, then select the SDD that reduces the higher number of voltage errors.

In this section, experimental results and a discussion of some relevant practical issues are presented. The used prototype, as shown in Fig. 5(b), is a five-level FCMC, with the following nominal parameters: input voltage of 100 V, flying capacitor values of 390 μF, connected load R = 6.1 Ω, and L = 2.8 mH. All the tests are performed with nominal input voltage and R−L load, with a sampling frequency of 20 kHz for the output current and capacitor voltages’ control loops (i.e., fc = fp2 = 20 kHz). The control algorithm, given by (13)–(15), and the transition rules defined in Tables IV and VI are implemented in a dSPACE 1104 development system and an ACTEL ProASIC field-programmable gate array board. Fig. 5(a) shows the control scheme block diagram. First, the converter response is studied under large input voltage variations. Fig. 6 shows the capacitor voltage response for large input voltage variations. From t1 to t2 , the input voltage drops from nominal value to 0 V. After this, from t3 to t4 , the voltage is re-established to nominal voltage. In both events, the capacitor voltages are regulated to their reference values, including during the transient time. The output current regulation is evaluated with a piecewise current reference, which is composed of three different waveforms. Figs. 7 and 8 show the obtained results. Notice that the output current tracking error is bounded, as shown in the bottom trace in Figs. 7 and 8, indicating that the output current regulation is achieved. Moreover, the output voltage is composed by equalmagnitude and adjacent discrete voltage levels (see the top traces in Figs. 7–9), indicating that the capacitor voltage regulation is also achieved. The output current regulation strategy, expressed in (13)–(15), takes into account the maximum reachable current. If the load resistance changes, then the operating regions OR(i∗ ) will also change. One alternative to deal with this issue is to incorporate an online estimation scheme for the output resistance. To demonstrate this approach, we have included an estimation scheme, based on least mean squares, for the output resistance. The estimation scheme is activated whenever the output current error is about 30% greater than the expected current error given by (16). When this is the case, then the commanded voltage level is set to zero during eight consecutive sampling periods; five consecutive measurements of the output current are stored, and then the least mean square algorithm is applied to estimate the equivalent load resistance.


1733

TABLE VI T RANSITION R ULES FOR THE PN C ONTROLLING THE C ONVERTER S WITCHING S TATES . (N OTATION : e+ ≡ ek > 0 AND e− ≡ ek < 0, k = 1, 2, 3) k k

Fig. 6. Capacitor voltages’ evolution under large input voltage variations.

Fig. 5. (a) Control scheme block diagram. (b) Laboratory prototype.

Fig. 9 shows the results; at t = 45 ms, the output resistance is increased to twice its nominal value. Notice that the estimation scheme is activated twice, i.e., at t = 45 ms and t = 64 ms, and the current tracking performance is maintained as expected. In Fig. 9, the estimated value of the output resistance is shown in the middle trace, which is labeled R(estimation). Another consideration is about the commutation frequency. In this regard, this scheme operates with variable switching frequency, where the maximum commutation frequency is limited to half the used frequency in the current regulation strategy. The average

Fig. 7. Output current regulation test. (Top trace) Output voltage. (Middle trace) Reference current and measured current. (Bottom trace) Tracking error.

commutation frequency is determined by the operating point and by the frequency at which the capacitor voltage regulation is executed, and it is also affected by the input voltage

1734


frequency for the current control loop is fixed at 20 kHz. Notice that the sampling frequency used in the capacitor voltage control strategy greatly influences the average switching frequency.

V. C ONCLUSION

Fig. 8. Expanded view of the output current regulation test. (Top trace) Output voltage. (Middle trace) Reference current and measured current. (Bottom trace) Tracking error.

Fig. 9. Performance under load change with output resistance estimation. (Top trace) Output voltage. (Middle traces) Estimated output resistance and output current. (Bottom trace) Output current tracking error.

In this paper, a control scheme based on two PNs has been proposed to control the capacitor voltages and the output current of an FCMC. The proposed scheme combines the capacitor voltages and output current regulation using a set of two cascaded PNs. The first PN determines the needed voltage level for the output current regulation, and the second PN defines the converter switching state such that the required voltage level and the capacitor voltage regulation are ensured. Furthermore, from a Lyapunov analysis, sufficient conditions ensuring the stability of the closed-loop system have been established. Then, from this analysis, the commutation rules (i.e., the PN firing conditions) have been obtained. Moreover, the proposed scheme using PNs combines continuous and discrete variables, resulting in a compact system representation that does not require an exhaustive state enumeration as will be required by a classical state machine approach or by a PN approach using only one PN to represent all the possible converter states. Additionally, some practical issues such as the output current ripple, capacitor voltage ripple, and switching frequency have been studied. Finally, the control scheme has been implemented in a laboratory prototype for a five-level converter, and experimental results have been obtained to illustrate the control scheme performance under several operation conditions. R EFERENCES

Fig. 10. Average switching frequency for i∗ = 7 + 6 · sin(2πf0 · t) using two different sampling frequencies for the capacitors voltage regulation loop; fp2 = 20 kHz (solid line), and fp2 = 10 kHz (dotted line).

dynamics and load characteristics. Fig. 10 shows the average commutation frequency for nominal load, and a sinusoidal reference current is defined as i∗ = 7 + 6 · sin(2πf0 · t) with f0 = 10, 20, . . . , 100 Hz using two different sampling frequencies for the voltage regulation loop, whereas the sampling

[1] B. P. McGrath and D. G. Holmes, “Enhanced voltage balancing of flying capacitor multilevel converter using phase disposition (PD) modulation,” IEEE Trans. Power Electron., vol. 26, no. 7, pp. 1933–1942, Jul. 2011. [2] R. H. Wilkinson, T. A. Meynard, and H. du Toit Mouton, “Natural balance of multicell converters: The general case,” IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1658–1666, Nov. 2006. [3] S. Thielemans, A. Ruderman, B. Reznikov, and J. Melkebeek, “Improved natural balancing with modified phase-shifted PWM for single-leg fivelevel flying-capacitor converters,” IEEE Trans. Power Electron., vol. 27, no. 4, pp. 1658–1667, Apr. 2012. [4] Z. Lim, A. I. Maswood, and G. H. Ooi, “Modular-cell inverter employing reduced flying capacitors with hybrid phase-shifted carrier phase-disposition PWM,” IEEE Trans. Ind. Electron., vol. 62, no. 7, pp. 4086–4095, Jul. 2015. [5] W. Li, Q. Jiang, Y. Mei, C. Li, and X. He, “Modular multilevel DC/DC converters with phase-shift control scheme for high-voltage DC-based systems,” IEEE Trans. Power Electron., vol. 30, no. 1, pp. 99–107, Jan. 2015. [6] A. Ghias et al., “Single-carrier phase-disposition PWM implementation for multilevel flying capacitor converters,” IEEE Trans. Power Electron., vol. 30, no. 10, pp. 5376–5380, Oct. 2015. [7] V. Dargahi, A. K. Sadigh, M. Abarzadeh, S. Eskandari, and K. A. Corzine, “A new family of modular multilevel converter based on modified flyingcapacitor multicell converters,” IEEE Trans. Power Electron., vol. 30, no. 1, pp. 138–147, Jan. 2015. [8] M. F. Escalante and J.-C. Vannier, “Direct approach for balancing the capacitor voltages of a 5-level flying capacitor converter,” in Proc. 8th EPE Power Electron. Conf., Sep. 7, 1999, vol. 776, pp. 1–8. [9] C. Feng, J. Liang, and V. G. Agelidis, “Modified phase-shifted PWM control for flying capacitor multilevel converters,” IEEE Trans. Power Electron., vol. 22, no. 1, pp. 178–185, Jan. 2007.


[10] L. Xu and V. G. Agelidis, “Active capacitor voltage control of flying capacitor multilevel converters,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 151, no. 3, pp. 313–320, May 2004. [11] M. Khazraei, H. Sepahvand, K. A. Corzine, and M. Ferdowsi, “Active capacitor voltage balancing in single-phase flying-capacitor multilevel power converters,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 769–778, Feb. 2012. [12] A. Ghias, J. Pou, V. G. Agelidis, and M. Ciobotaru, “Voltage balancing method for a flying capacitor multilevel converter using phase disposition PWM,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6538–6546, Dec. 2014. [13] T. J. Vyncke, S. Thielemans, and J. Melkebeek, “Finite-set model-based predictive control for flying-capacitor converters: Cost function design and efficient FPGA implementation,” IEEE Trans. Ind. Informat., vol. 9, no. 2, pp. 1113–1121, May 2013. [14] J. Amini, “An effortless space-vector-based modulation for N-level flying capacitor multilevel inverter with capacitor voltage balancing capability,” IEEE Trans. Power Electron., vol. 29, no. 11, pp. 6188–6195, Nov. 2014. [15] A. Ghias, J. Pou, M. Ciobotaru, and V. G. Agelidis, “Voltage-balancing method using phase-shifted PWM for the flying capacitor multilevel converter,” IEEE Trans. Power Electron., vol. 29, no. 9, pp. 4521–4531, Sep. 2014. [16] P. R. Kumar, R. S. Kaarthik, K. Gopakumar, J. I. Leon, and L. G. Franquelo, “Seventeen-level inverter formed by cascading flying capacitor and floating capacitor H-bridges,” IEEE Trans. Power Electron., vol. 30, no. 7, pp. 3471–3478, Jul. 2015. [17] A. Ghias, J. Pou, V. G. Agelidis, and M. Ciobotaru, “Optimal switching transition-based voltage balancing method for flying capacitor multilevel converters,” IEEE Trans. Power Electron., vol. 30, no. 4, pp. 1804–1817, Apr. 2015. [18] J. Druant, T. Vyncke, F. De, P. Sergeant, and J. Melkebeek, “Adding inverter fault detection to model-based predictive control for flyingcapacitor inverters,” IEEE Trans. Ind. Electron., vol. 62, no. 4, pp. 2054–2063, Apr. 2015. [19] G. Gateau, M. Fadel, P. Maussion, R. Bensaid, and T. A. Meynard, “Multicell converters: Active control and observation of flying capacitor voltages,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 998–1008, Oct. 2002. [20] S. Choi and M. Saeedifard, “Capacitor voltage balancing of flying capacitor multilevel converters by space vector PWM,” IEEE Trans. Power Del., vol. 27, no. 3, pp. 1154–1161, Jul. 2012. [21] F. Defa, A. M. Llor, and M. Fadel, “A predictive control with flying capacitor balancing of a multicell active power filter,” IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3212–3220, Sep. 2008. [22] F. Defa, A. M. Llor, and M. Fadel, “Direct control strategy for a four-level three-phase flying-capacitor inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2240–2248, Jul. 2010. [23] R. Davoodnezhad, D. G. Holmes, and B. P. McGrath, “A hysteresis current control for single-phase multilevel voltage source inverters: PLD implementation,” IEEE Trans. Power Electron., vol. 29, no. 11, pp. 6100–6109, Nov. 2014. [24] M. Khazraei, H. Sepahvand, M. Ferdowsi, and K. A. Corzine, “Hysteresisbased control of a single-phase multilevel flying capacitor active rectifier,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 154–164, Jan. 2013. [25] D. G. Holmes and B. P. McGracth, “Hysteresis current regulation of three phase flying capacitor inverter with balanced capacitor voltages,” in Proc. IEEE Power Electron. Motion Control Conf., Jun. 2012, pp. 47–52. [26] A. Shukla, A. Ghosh, and A. Joshi, “Hysteresis current control operation of flying capacitor multilevel inverter and its application in shunt compensation of distribution systems,” IEEE Trans. Power Del., vol. 22, no. 1, pp. 396–405, Jan. 2007. [27] C. G. Cassandras and S. Lafortune, Introduction to Discrete Event Systems. Cambridge, MA, USA: Harvard Univ. Press, 1999. [28] A. Giua and F. DiCesare, “Blocking and controllability of Petri nets in supervisory control,” IEEE Trans. Autom. Control, vol. 39, no. 4, pp. 818–823, Apr. 1994. [29] P. J. Antsaklis, X. D. Koutsoukos, and J. Zaytoon, “On hybrid control of complex systems: A survey,” Eur. J. Autom. APII-JESA, vol. 32, no. 9/10, pp. 1023–1045, Dec. 1998. [30] I. Demongodin and N. T. Koussoulas, “Differential Petri net models for industrial automation and supervisory control,” IEEE Trans. Syst., Man Cybern. C, Appl. Rev., vol. 36, no. 4, pp. 543–553, Jul. 2006. [31] D. Lefebvre and E. Leclercq, “Control design for trajectory tracking with untimed Petri nets,” IEEE Trans. Autom. Control, vol. 60, no. 7, pp. 1921–1926, Jul. 2015.

1735

[32] M. Zhou, F. DiCesare, and A. A. Desrochers, “A hybrid methodology for synthesis of Petri net models for manufacturing systems,” IEEE Trans. Robot. Autom., vol. 8, no. 3, pp. 350–361, Jun. 1992. [33] H. Hu and M. Zhou, “A Petri net-based discrete-event control of automated manufacturing systems with assembly operations,” IEEE Trans. Control Syst. Technol., vol. 23, no. 2, pp. 513–524, Mar. 2015. [34] F. Basile, P. Chiacchio, and J. Coppola, “A hybrid model of complex automated warehouse systems. Part I: Modeling and simulation,” IEEE Trans. Autom. Sci. Eng., vol. 9, no. 4, pp. 640–653, Oct. 2012. [35] S. Carmeli, E. Cosatto, A. Monti, and C. Penno, “Software design methodology for power electronics applications,” in Proc. IEEE Workshop Comput. Power Electron., Jul. 1998, pp. 27–33. [36] V. K. Parachuri, A. Davari, and A. Feliachi, “Hybrid modeling of power system using hybrid Petri nets,” in Proc. IEEE SST, Mar. 2005, pp. 221–224. [37] K. L. Lo, H. S. Ng, and J. Trecat, “Power systems fault diagnosis using Petri nets,” Proc. Inst. Elect. Eng.—Gener., Transmiss. Distrib., vol. 144, no. 3, pp. 231–236, May 1997. [38] Z. Rong, F. Shengfang, and C. Jian, “Hybrid modeling techniques for power electronics based on Petri net,” in Proc. IEEE Elect. Mach. Syst. Conf., Oct. 2008, pp. 3850–3853. [39] B. Amghar, M. Darcherif, J.-P. Barbot, and D. Boukhetala, “Modeling and control of series resonant converter for high voltage applications,” in Proc. IEEE Energy Conf., May 2014, pp. 216–221. [40] B. Amghar, M. Darcherif, and J.-P. Barbot, “Z(TN)-observability and control of parallel multicell chopper using Petri nets,” IET Power Electron., vol. 6, no. 4, pp. 710–720, Apr. 2013. [41] B. C. Florea, D. A. Stoichescu, and V. Stefanescu, “A Petri net approach to multicellular chopper control,” in Proc. IEEE Int. Symp. Des. Technol. Electron., Oct. 2011, pp. 227–230. [42] B. C. Florea, “Petri net modeling for hybrid systems control. Application for a multicellular converter,” in Proc. IEEE Int. Symp. Adv. Topics Elect. Eng., May 23–25, 2013 pp. 1–4. [43] F. Salinas, M. Ghanes, J.-P. Barbot, M. F. Escalante, and B. Amghar, “Modeling and control design based on Petri nets for serial multicellular choppers,” IEEE Trans. Control Syst. Technol., vol. 3, no. 1, pp. 91–100, Apr. 2014.

Fernando Salinas received the B.S. degree from the Universidad Nacional Autónoma de México, Mexico City, Mexico, and the M.S. and Dr.Eng. degrees from the Universidad Autónoma de Nuevo León (UANL), San Nicolás de Los Garza, Mexico. Since 2013, he has been a Professor with the Facultad de Ingeniería Mecánica y Eléctrica, UANL. His current research interests include control of multilevel power converters in applications of electrical machines and power systems.

Mario A. González received the B.S. and M.S. degrees from the Universidad Autónoma de Nuevo León, San Nicolás de Los Garza, Mexico, where he is currently working toward the Ph.D. degree. His current research interests include power electronics and multilevel converters, applied electrical machines, and electrical vehicles’ traction systems.

1736


Miguel F. Escalante (M’04) received the B.S. and M.S. degrees from the Instituto Tecnológico de Chihuahua, Chihuahua, Mexico, in 1987 and 1996, respectively, and the Dr. Eng. degree jointly from the Université de Paris VI, Paris, France, and the École Supérieure d’Électricité, Gif-sur-Yvette, France, in 2001, all in electrical engineering. Since 2003, he has been a Professor with the Facultad de Ingeniería Mecánica y Eléctrica, Universidad Autónoma de Nuevo León, San Nicolás de Los Garza, Mexico. His research interests include power electronics and multilevel power converters applied to electrical machines and power systems.

Jesús de León Morales received the Ph.D. degree in automatic control from Claude Bernard Lyon 1 University, Villeurbanne, France, in 1992. Since 1993, he has been a Professor of electrical engineering with the Universidad Autónoma de Nuevo León, San Nicolás de Los Garza, Mexico. He is currently working on applications of control theory, electrical machines, nonlinear observers, and power systems.