Control of Dc-Dc Converters by Direct Pole Placement

Control of Dc-Dc Converters by Direct Pole Placement and Adaptive Feedforward Gain Adjustment Anthony Kelly

Karl Rinne

Analog Devices Limerick, Ireland [email protected]

Department of Electronic & Computer Engineering University of Limerick Limerick, Ireland [email protected]

Abstract— A direct pole-placement control strategy is introduced, and applied in the design of a buck type, dc-dc converter. The solution involves a feedforward component in the control strategy, to eliminate steady-state errors. The value of the feedforward gain which completely eliminates steady-state error, is dependant upon the gain of the plant, which may not be known exactly. In this design the feedforward gain is determined adaptively, so as to drive the steady state error to zero. Keywords– pole-placement, digital control, dc-dc converter, LMS, sigma-delta.

I.

INTRODUCTION

Digital control of dc-dc converters is an active research topic in power control. Many controllers have been demonstrated [1-8]. Whilst the controllers differ in several aspects, the control strategies center around PD, PI, PID control; and compensation strategies generally incorporate classical methods such as gain and phase margin, root-locus. The designs incorporate both discrete-time emulation of an analog controller, and direct-digital design. In this paper, we apply an alternative controller design strategy to a buck converter; that is, design by direct pole placement. Direct-pole placement allows us to specify the location of the closed-loop poles, and therefore the closed-loop dynamics, as a design requirement. The direct-pole placement method used, is the polynomial approach, which involves the solution of Diophantine equations in order to calculate the required controller parameters. It will be seen that the solution U(z)

V(z) β ( z) α ( z)

B( z ) A( z )

Figure 1. Model of the control system

involves a feedforward component to eliminate steady-state errors. The value of the feedforward gain which completely eliminates steady-state error, is dependant upon the gain of the plant, which may not be known exactly. In this design the feedforward gain is determined adaptively, so as to drive the steady state error to zero. This paper will demonstrate that direct pole-placement is a feasible strategy for dc-dc converter design, allowing the selection of a simple complex conjugate pair of closed-loop poles, and to introduce a novel method to achieve a zero steady-state error.

II.

DIOPHANTINE EQUATIONS

Consider the control system of Figure 1. The plant may be described, in discrete time, by polynomial functions in z; B(z) and A(z), (1) and (2), where A(z) is monic:

A( z ) = z n + a1 z n −1 + .. + a n −1 z + a n

(1)

B ( z ) = b0 z n + b1 z n −1 + .. + bn −1 z + bn

(2)

Similarly, the controller may be described as:

α ( z ) = α 0 z n −1 + α 1 z n − 2 + .. + α n − 2 z + α n −1

(3)

β ( z ) = β 0 z n −1 + β 1 z n − 2 + .. + β n − 2 z + β n −1

(4)

Examining the controller of Figure 1, its closed loop transfer function may be written as:

G( z) =

B( z ) β ( z ) A( z )α ( z ) + B( z ) β ( z )

(6)

Thus, we may write a Diophantine equation to describe the relationship between the closed-loop characteristic equation of (5) and the desired characteristic equation (6):

D ( z ) = α ( z ) A( z ) + β ( z ) B ( z )

III.

deg α = deg β = n − 1

(11)

deg D = 2 n − 1

(12)

Therefore:

Since the desired closed loop characteristic equation involves the placement of n closed loop poles; D(z) may be decomposed in to two polynomials (13) in which Dd(z) is of degree n, describing the desired closed loop poles; and Do(z) is of degree n – 1, and is an arbitrary, stable, polynomial.

Dd ( z ) Do ( z ) = α ( z ) A( z ) + β ( z ) B ( z )

(7)

(13)

The polynomial Do(z) may be thought of as an observer of the desired characteristic polynomial Dd(z). Given that deg Dd = n, and only its output is observable, it makes sense the deg Do = n – 1.

CONSTRAINTS ON THE FORMULATION OF THE DIOPHANTINE EQUATION

In solving the Diophantine equation (7), we wish to solve for the controller polynomials, α(z) and β(z), given a desired characteristic polynomial D(z), and plant described by B(z) and A(z). A solution exists if B(z) and A(z) are relatively prime. We need to examine the degree of the polynomials in the Diophantine equation. If we decide that the degree of the monic polynomial A(z) is of degree n ( deg A = n ) , then for simplicity we may also make deg B = n. If the actual degree of B(z) is less than n, then the coefficients of the higher degrees will be zero. The degree of B(z) cannot be greater than n in a causal system. If α(z) and β(z) are solutions of (7), then (8) and (9) are also solutions, where Q(z) is an arbitrary polynomial.

α ' ( z ) = α ( z ) + Q( z ) B( z )

(8)

β ' ( z ) = β ( z ) − Q( z ) A( z )

(9)

Therefore, in seeking the minimum degree solution for β(z), from (9) we can see that there is always a solution in which deg β < deg A, and so we can always find a solution in which the deg β is at most n – 1. A similar argument can be applied to α(z). We have:

(10)

(5)

The denominator of the closed loop system (5) is of the following form (6). It may be thought of as describing the dynamic behaviour which we want the closed-loop system to exhibit.

D ( z ) = d 0 z 2 n −1 + d1 z 2 n − 2 + ... + d 2 n − 2 z + d 2 n −1

deg A = deg B = n

IV.

SOLUTION OF THE DIOPHANTINE EQUATION

In order to solve the Diophantine equation (13), for the unknown polynomials, α(z) and β(z), we must solve the set of simultaneous equations described by (13). This is conveniently achieved in matrix algebra [9], by formulating a 2n square, Sylvester matrix, E, from the coefficients of the known polynomials, B(z) and A(z); and vectors of the coefficients of D(z), D, and α(z) and β(z), M. Thus, the following equation must be solved for M:

EM = D

(14)

The Sylvester matrix is formulated as follows:

E=

an an −1 . a1

0 an an −1 .

1 0 . 0

a1 1 . 0

0

0

. . . .

0 0 0 0

bn 0 bn −1 bn . bn −1 b1 .

. . . .

. an . an −1 . . . a1

b0 0 . 0

b1 b0 . 0

. bn . bn −1 . . . b1

.

0

0

.

1

0 0 0 0

b0

(15)

B( z ) 6.882 × 10 −4 z + 6.887 × 10 −4 = A( z ) z 2 − 1.997 z + 0.9979

and:

M = [α n −1 .. α 0

β n −1 .. β 0 ]T

D = [d 2 n −1 .. d 0 ]

T

(16)

(17)

As an example of (14) for n = 2:

a2 a1 1

0 a2 a1

b2 b1 b0

0 α1 d3 b2 α 0 d = 2 . b1 β1 d1

0

1

0

b0

β0

(18)

In the second step, we choose the desired closed-loop poles to be simple, second order complex conjugate, such that the closed-loop dynamics exhibit a natural frequency which is twice that of the plant, with a 0.7 damping factor. This should yield a fast, nicely damped response, without overly aggressive controller actions which may result in saturation. Converted to discrete time, via zero-pole matching, the desired closed-loop transfer function is:

Gd ( z ) =

1.726 × 10 −3 ( z + 1) z 2 − 1.916 z + 0.9194

(22)

d0

We may solve (14) for the controller parameters in vector M by (19).

M = E −1 D

(19)

Thirdly, we must design a controller such that the poles of the closed-loop transfer function match those which are required. Recall, the proposed controller will be of the form shown in Figure 1, where β and α are polynomials in z which describe the controller; B and A describe the plant; and the closed-loop transfer function of the controller is (5); repeated below for clarity:

G( z) = V.

(21)

B( z ) β ( z ) A( z )α ( z ) + B( z ) β ( z )

THE DESIGN PROCESS

(5)

Having reviewed the formulation and solution of the relevant design equations, we would now like to examine its application in the design of a dc-dc buck converter.

Recall also, that our goal is for the characteristic equation (poles) of the closed-loop controller, to be equal to the characteristic equation of our desired closed-loop system. From (13); repeated below for clarity:

The first step in this direct digital design process, is to obtain a model of the plant in discrete time. To a first order, the plant may be described in the s-domain, as:

Dd ( z ) Do ( z ) = α ( z ) A( z ) + β ( z ) B( z )

H v (s) =

1 LC s + s RC + 1 LC 2

(20)

Conversion to the z-domain is performed, in this case, as a zero-order hold equivalent, which by definition, takes into account the control delay associated with conversion from discrete controller output values to continuous time. The final plant model for the prototype component values in discrete time, assuming a 1MHz sampling frequency, is (21). The characteristic polynomial is of degree 2; so n = 2.

(13)

Equation (13) states that the closed-loop characteristic equation (5), should equal the desired characteristic equation Dd(z), of order n, combined with a minimum order (n-1), observer Do(z). Our desired characteristic equation is second order, so the minimum order observer should be first order; we simply define it as:

D0 ( z ) = z

(23)

Substituting (23) and the characteristic coefficients of (22) into (13), we have:

Vos

Multi-bit Digital Sigma-Delta Modulator

β ( z) α (z)

L=33µH R 22Ω

ADC

C 22µF

LowResolution DPWM PWM

IL(t)

Figure 2. Buck dc-dc converter as designed.

z 3 − 1.916 z 2 + 0.9194 z = α ( z ) A( z ) + β ( z ) B( z )

Equation (19) yields:

(24)

M T = [0.0399 1.0 − 57.914 59.705]

With n = 2, we must solve (19) with:

0.9979 E=

− 1.997 1 0

0

0

Thus, the controller is:

0

6.882 × 10

−4

0

− 1.997 6.887 × 10

−4

6.882 × 10 − 4

0.9979 1

6.887 × 10

0

(27)

(25)

β ( z ) 59.705z − 57.914 = α ( z) z + 0.0399

−4

(28)

and,

D = [0 0.9194

− 1.916 1]

T

(26)

AD1991

L=33µH IL(t)

Vi=10V

We may set the pole of the controller to zero without any significant error, so the controller to be designed is:

Vo(t)

C 22µF

DPWM ADSP21992 d(n)

Figure 3. Buck dc-dc converter, as prototyped.

Digital Controller

R 22R

ADC

Figure 4. Experimental 25% - 75% positive load step; L=33µ µH, C=22µ µF, fs=1MHz, Vin=10V, Vo=2.5V, DPWM resolution=200 mV Trace1: 50mV/div vertical scale, 100µ µs/div horizontal scale.

14bits is easily achievable using this simple technique.

(z − 0.96) β ( z) = 59.7 α ( z) z

(29)

The controller of (29) is a discrete PD controller. As such, the control loop contains no integral property, and therefore the closed-loop steady state error will not be zero. Zero steadystate error is generally a required property for dc-dc converters, so a feedforward element is introduced into the control strategy. The control system, shown in Figure 2, comprises of a controller, a feedforward element, a multi-bit digital sigmadelta modulator, a low-resolution DPWM, a power train, and an ADC. The purpose of the multi-bit digital sigma-delta modulator [10], in this context, is to shape the quantization noise so that a low resolution DPWM, e.g. 50 level, can exhibit much higher effective resolution. An effective resolution of

Vos

β ( z) α ( z)

VI.

The prototype converter, which is the subject of this design, is shown in Figure 3. It shows the component values for the plant, and that the controller was prototyped using an ADSP21992 DSP processor with integrated DPWMs and ADCs. The power stage is seen to incorporate an integrated power switch and MOSFET drivers, the AD1991, with built-in over-current and thermal protection. The maximum rated output current was 1A. The transient load regulation characteristics of the prototype system are shown in Figure 4. The max rated current is 1 Amp. The measured over/undershoot is less than 80mV for a 0.5 A step, and recovers completely in around 50 µs. This

Multi-bit Digital Sigma-Delta Modulator L=33µH

γ/(z-1) ADC

PROTOTYPE

R 22Ω

C 22µF

LowResolution DPWM PWM

IL(t)

Figure 5. Buck dc-dc converter, including adaptive feedforward gain adjustment

Figure 6. Figure 7, shows that zero steady-state error is achieved.

0.9 0.8

VIII. CONCLUSION

0.7 0.6 0.5 0.4 200

400

600

800

1000

1200

time (micro-seconds)

1400

1600

1800

Figure 6. Adaptation of the feedback gain compares favorably with commercially available dc-dc converters based upon conventional controller design strategies.

REFERENCES [1] A. V. Peterchev, J. Xiao, and S. R. Sanders, "Architecture and IC implementation of a digital VRM controller," IEEE Transactions on Power Electronics, vol. 18, pp. 356-364, 2003.

VII. FEEDBACK GAIN CORRECTION In order for the steady-state error to be exactly zero using this feedforward technique, the feedback gain needs to be determined exactly. As this is not possible, we adapt the feedback gain using least-mean-square (LMS) techniques, so that the control error is driven to zero. The LMS adaptive filtering algorithm uses a point-estimate of a cost-function gradient, related to the mean square of the error between the desired filter output and the actual filter output, such that the filter tap-weights are adjusted in order for the error to be minimized [11]. In this case, the error is the control error, but the state to be processed by the LMS algorithm is also the control error; therefore simplifications can be made which lead to the circuit of Figure 5, where the feedback gain of this controller is set by the integral of the control error. Thus, a feedback gain is arrived at, which sets the steady-state error to zero. The adaptation of the feedback gain may be seen in -3

1

A direct pole-placement design technique has been demonstrated for a buck dc-dc converter implemented by a discrete-time controller. This technique allows direct placement of the closed-loop poles, as desired. The performance on a prototype compared very favourably with standard design methods. Adaptation of the feedback gain, using LMS techniques, was shown to be effective in driving the steady-state control error to zero.

[2] A. Prodic, D. Maksimovic, and R. W. Erickson, "Design and implementation of a digital PWM controller for a high-frequemcy switching dc-dc power converter," presented at IECON'01: The 27th annual conference of the IEEE Industrial Electronics Society, 2001. [3] A. Prodic and D. Maksimovic, "Digital PWM controller and current estimator for a low-power switching converter," presented at The 7th workshop on computers in Power Electronics, 2000. [4] A. M. Wu, J. Xiao, D. Markovic, and S. R. Sanders, "Digital PWM control: applications in voltage regulation modules," presented at Power Electronics Specialists Conference, 1999. PESC 99, 1999. [5] S. Bibian and H. Jin, "High Performance Predictive Dead-Beat Digital Controller for DC Power Supplies," IEEE Transactions on Power Electronics, vol. 17, pp. 420 - 427, 2002. [6] J. Chen, A. Prodic, R. W. Erickson, and D. Maksimovic, "Predictive Digital Current Programmed Control," IEEE Transactions on Power Electronics, vol. 18, pp. 411 - 419, 2003. [7] A. Prodic, D. Maksimovic, and R. W. Erickson, "Digital controller chip set for isolated DC power supplies," presented at Applied Power Electronics Conference and Exposition, 2003. APEC '03., 2003.

x 10

0.5

0

[8] A. Dancy and A. Chandrakasan, "A reconfigurable dual output low power digital PWM power converter," presented at Low Power Electronics and Design, 1998, 1998.

-0.5

[9] K. Ogata, Discrete - Time Control Systems, 2nd ed. Upper Saddle River, N.J.: Prentice Hall, 1994.

-1 500

1000

1500

2000

time (micro-seconds)

2500

3000

Figure 7. Loop error-voltage behaviour during adaptation

[10] A. Kelly and K. Rinne, "Sensorless current-mode control of a digital dead-beat DC-DC converter," presented at Applied Power Electronics Conference and Exposition, 2004. [11] S. Haykin, Adaptive Filter Theory, 4th ed. New Jersey: Prentice-Hall, 2002