Coplanar Integration of Lattice-Mismatched Semiconductors with

Journal of The Electrochemical Society, 151 共7兲 G443-G447 共2004兲

G443

0013-4651/2004/151共7兲/G443/5/$7.00 © The Electrochemical Society, Inc.

Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding GeÕSi1Àx Gex ÕSi Virtual Substrates Arthur J. Pitera,z G. Taraschi, M. L. Lee, C. W. Leitz,* Z.-Y. Cheng, and E. A. Fitzgerald Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding Ge/Si1⫺x Gex /Si virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator 共GOI兲 have been identified and solved, resulting in the transfer of epitaxial Ge/SiO2 to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using H2 -induced layer exfoliation 共Smartcut™兲 and a buried Si0.4Ge0.6 etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of ⬍15 nm rms as measured on a 25 ⫻ 25 ␮m scale and a 1 ⫻ 1 ␮m scale roughness of ⬍1.4 nm. Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. 关DOI: 10.1149/1.1757462兴 All rights reserved. Manuscript submitted July 14, 2003; revised manuscript received January 16, 2004. Available electronically May 19, 2004.

The overwhelming success of silicon in modern microelectronics can be attributed to its high-quality native oxide. This eventually led to complementary metal oxide semiconductor 共CMOS兲 circuit topology, dense digital integrated circuits 共ICs兲, and large diameter wafers and manufacturing infrastructure. Advances in IC performance are currently achieved through dimensional scaling of device geometries. However, this trend cannot continue indefinitely since device features will soon approach atomic dimensions. Fundamental material properties of silicon including its low carrier mobility and indirect bandgap are becoming limiting factors in further improvement of integrated circuit functionality and performance. CMOS functionality can be vastly improved through monolithic integration of high-performance materials such as Ge and III-V semiconductors with Si. The monolithic approach allows these materials to be co-processed on the same substrate, eliminating expensive back-end hybrid integration of independently processed Si and III-V devices. Such a method can be realized using Si, Ge, or III-V substrates. However, in order to take advantage of state-of-the-art CMOS fabrication facilities and preserve the economics of fabrication on large diameter substrates, it is necessary to integrate these materials on the Si platform. The ⬃4% lattice mismatch between Si and GaAs or Ge precludes direct growth of the mismatched material on Si without nucleation of a high (⬎108 cm⫺2 ) density of threading dislocations.1 These defects behave as carrier recombination centers and have a deleterious effect on performance, particularly for minority carrier devices. Although optoelectronic devices, including lasers, have been demonstrated on GaAs grown directly on Si,2-5 their poor reliability makes them commercially unfeasible. One technique to reduce the threading dislocation density 共TDD兲 is the growth of compositionally graded buffers.6 During graded buffer growth, a large lattice constant mismatch is diluted over many low-mismatch interfaces thereby controlling the nucleation rate of threading dislocations. Compositional grading of relaxed Si1⫺x Gex layers of increasing Ge fraction can be used to create an arbitrary lattice constant ranging from that of Si to Ge on a bulk Si substrate. Such a structure is termed a virtual substrate. Ge virtual substrates can be used to integrate III-V materials with Si7 since the lattice mismatch between Ge and GaAs is only 0.07%. These have enabled fabrica-

* Electrochemical Society Active Member. z

E-mail: [email protected]

tion of compound semiconductor lasers8,9 and an optical circuit10 utilizing an LED emitter, waveguide, and detector monolithically integrated on a Si wafer. Despite its ability to produce latticemismatched epitaxy of unprecedented quality, the virtual substrate approach requires growth of a thick graded buffer to ensure complete relaxation of the individual mismatched layers. In the case of Ge virtual substrates which are compositionally graded from Si to Ge, the buffer thickness is typically greater than 10 ␮m. Such thick layers complicate subsequent device integration with the underlying Si since the device levels are not coplanar and must be co-processed across a deep step. Wafer bonding and layer transfer11,12 is another approach that can be used to integrate low-defect, lattice mismatched materials with Si. In the direct bonding method, a Si handle wafer and a mismatched seed wafer are brought into contact and annealed to produce a strong bond. A thin, monocrystalline layer of material is then transferred from the seed to the handle wafer by a variety of techniques including grind and etch-back13 or layer exfoliation by hydrogen ion implantation, i.e., Smartcut.14 However, conventional wafer bonding using bulk wafers has two serious limitations. First, the different coefficients of thermal expansion 共CTE兲 of Si (2.57 ⫻ 10⫺6 K⫺1 ) 15 relative to GaAs (6.03 ⫻ 10⫺6 K⫺1 ) 16 and Ge (5.90 ⫻ 10⫺6 K⫺1 ) 15 require a low thermal budget during bond annealing. Thermal stress17 arising from CTE mismatch will cause the bonded pair to separate after annealing at high temperature.18 The thermal stress problem between thermally mismatched wafers can be handled using the Smartcut approach where a thin layer of material is transferred from bulk GaAs19 or Ge20 to Si prior to cooling the bonded pair to ambient. A more serious issue is the wafer size difference between Si and III-V or Ge wafers. Films transferred to Si from III-V-sized wafers limit their use to outdated fabrication facilities running small diameter Si wafers for low-end CMOS applications. Although a limited supply of Ge bulk wafers are available in large diameters, their current production volume is too small to sustain the CMOS industry. The advantages of virtual substrates and layer transfer using wafer bonding can be combined by bonding virtual substrates rather than bulk wafers. By transferring epitaxially grown layers from virtual substrates, Ge or III-V films can be fabricated in close proximity to a Si substrate while taking advantage of the full diameter of modern Si wafers. This approach also eliminates the thermal stress that arises during bulk wafer-bonding since both seed and handle wafers are bulk Si.

G444

Journal of The Electrochemical Society, 151 共7兲 G443-G447 共2004兲 Experimental

Virtual substrate growth.—The virtual substrates used in this work were prepared starting from double-side polished 共DSP兲 Si wafers with an orientation of 共100兲 off-cut 6° towards a 兵111其 plane. An off-cut orientation is used for two reasons. First, dislocation interactions are reduced when growing graded buffers on off-cut wafers, thereby lowering the crosshatched surface roughness and TDD.21 The TDD of our Ge virtual substrates is 1-2 ⫻ 106 cm⫺2 as determined by etch-pit density measurements that have been correlated with plan-view TEM 共PVTEM兲. Second, antiphase boundaries 共APBs兲 are suppressed during growth of GaAs on off-cut virtual substrates.22 In this work, only transfer of Ge from virtual substrates is investigated. However the process described here is adaptable to other semiconductors such as III-Vs, and future work will involve growth of APB-free GaAs on Ge for III-V transfer. The Si1⫺x Gex buffer layers were grown in a hot-walled ultrahigh vacuum chemical vapor deposition 共UHVCVD兲 reactor using SiH4 and GeH4 and a growth pressure ranging between 1-25 ⫻ 10⫺3 Torr. The growth temperature varied between 650-900°C, depending on the Ge content of the growing film. Since film growth occurs on both sides of the wafer in a hotwalled CVD system, use of DSP substrates is a simple but effective way to reduce wafer curvature induced by thermal stress. The wafer deflection of our Ge virtual substrates grown on single-side polished wafers is ⬎35 ␮m across a 100 mm wafer making the wafers difficult to bond. However, DSP wafers yield wafer deflections ⬍15 ␮m allowing easy conformation between seed and handle wafers necessary for bonding. Ge virtual substrate planarization.—Virtual substrates have surface roughness with a crosshatched pattern characteristic of graded buffer growth. Figure 1a illustrates the typical surface morphology of a Ge virtual substrate before planarization. The as-grown surface roughness of these substrates is 10-15 nm rms as measured by atomic force microscopy 共AFM兲 on a 25 ⫻ 25 ␮m scan area. In order to have efficient mating of the wafer surfaces during bonding, this roughness must be reduced to less than ⬃0.5 nm.23 Si1⫺x Gex virtual substrates with a Ge fraction of x ⭐ 0.5 can be readily planarized using a standard oxide CMP process consisting of a KOHstabilized colloidal silica slurry.24 However as the substrate composition is increased to pure Ge, the material removal rate 共MRR兲 decreases to less than 5 nm/min, making planarization of Ge highly inefficient. This decrease in polish rate with increasing Ge fraction is shown in Fig. 2. To complicate matters, anisotropic etching by the chemical component of the polishing slurry leads to surface pitting 共Fig. 1b兲 without complete removal of the crosshatch roughness after long 共⬎30 min兲 CMP times. The density of these surface pits is 5 ⫻ 105 cm⫺2 and roughly corresponds to the sample’s TDD, suggesting that they are caused by etching of threading dislocations intersecting the Ge surface. Bulk Ge CMP techniques cannot be easily applied to Ge virtual substrates since these generally have a strong chemical component and require removal of a large amount of material to achieve the required surface roughness. Unfortunately, the thickness of the uniform composition cap of our Ge virtual substrates is limited by thermal stress and generally does not exceed ⬃2 ␮m. Furthermore, the inhomogeneous strain fields emanating from the underlying misfit array of the graded buffer cause surface roughening during chemical etching. Therefore, a CMP process with a dominant chemical component will only enhance the crosshatch roughness and cannot be used to planarize virtual substrates. Rather than developing a new CMP process for Ge virtual substrates, planarization can be facilitated through an intermediate CMP layer consisting of deposited Si or SiO2 . Modern CMP processes allow polishing of such layers with high planarization rates while minimizing material removal. Furthermore, since Ge is incompatible with most CMOS wet cleaning chemistries, the CMP layer also serves to protect the underlying Ge from prebonding cleaning steps.

Figure 1. AFM surface scans showing Ge virtual substrate surface morphology before and after CMP. 共a兲 Before CMP, the characteristic crosshatch pattern with a 25 ⫻ 25 ␮m crosshatch roughness of 12 nm is visible. 共b兲 After 30 min of CMP using a KOH-based slurry chemistry, the roughness is reduced to ⬍5 nm at the expense of surface pitting caused by anisotropic etching.

In this work, a low temperature oxide 共LTO兲 was used as the CMP layer. The LTO was deposited on the virtual substrate and planarized using an oxide CMP process yielding a (1 ⫻ 1 ␮m) rms surface roughness of ⬍0.5 nm. Wafer bonding and layer transfer.—The most common methods used for the transfer of wafer-bonded films are mechanical grind and etch-back and the layer exfoliation process. The grind and etch-back technique requires a chemical etch-stop layer to selectively etch the seed wafer while stopping on the transferred film. Heavily p-doped Si has good etch stopping properties both in KOH and tetramethylammonium hydroxide 共TMAH兲 etch solutions, and can be used to fabricate SOI using the etch-back approach.25 Similar etch selectivity is seen between Si and Si1⫺x Gex with x ⬎ 0.2,26,27 thus allowing fabrication of Si0.75Ge0.25 alloys on insulator using relaxed


G445

Figure 2. MRR as a function of Ge fraction in Si1 ⫺ x Gex alloys using a KOH-based CMP process. The MRR decreases by over two orders of magnitude over the entire composition range and is reduced to ⬍5 nm/min for Ge.

Si0.75Ge0.25 as a natural etch-stop.28,29 However, there is no known etch that exhibits such selectivity to Ge across the entire Si1⫺x Gex composition range. Some alternative solutions for removal of the remaining buffer are timed etching or oxidation.30 In this work, we have implanted31 Ge with H2 ⫹ and used the layer exfoliation process to transfer our Ge films from virtual substrates. During layer exfoliation, the transferred film is mechanically damaged along the cleave plane, rendering it useless for subsequent device fabrication. This damage can be readily removed with a CMP step in Si-on-insulator 共SOI兲32 or SiGe-on-insulator 共SGOI兲33 wafers prepared in this manner. However, current CMP techniques are difficult to implement with thin Ge layers. To solve this problem, we have developed a novel process for the removal of exfoliation damage in Ge films using a peroxide etch and a strained Si0.4Ge0.6 etchstop layer. A cross-sectional TEM micrograph of the as-grown Ge virtual substrate incorporating the etch-stop layer is shown in Fig. 3. The transfer structure is grown on relaxed Ge and is composed of a

Figure 3. Cross-sectional TEM of the Ge transfer structure grown on a relaxed Ge/Si1⫺x Gex /Si virtual substrate. The transfer structure consists of a 6.5 nm layer of strained Si0.4Ge0.6 and a 140 nm layer of relaxed Ge capped with a 7 nm surface passivation layer of Si to protect the Ge from subsequent processing steps.

Figure 4. Schematic of the Ge transfer process. 共a兲 Preparation of the virtual substrate: growth of Ge transfer structure on a relaxed Ge/Si1⫺x Gex /Si virtual substrate using UHVCVD followed by SiO2 CMP layer deposition using LPCVD. 共b兲 Planarization of the SiO2 CMP layer and subsequent H2⫹ implantation. 共c兲 Wafer bonding the virtual substrate to a Si handle wafer. 共d兲 Anneal and exfoliation of the SiO2 , Ge, and Si0.4Ge0.6 etch-stop layers to a Si handle wafer. 共e兲 Selective etching in H2 O2 to remove the damaged Ge surface. 共f兲 Selective CMP to remove the Si0.4Ge0.6 etch-stop layer.

6.5 nm strained Si0.4Ge0.6 etch-stop buried by a 140 nm relaxed Ge transfer layer. The structure is capped with a 7 nm Si passivation layer to protect the Ge during subsequent chemical processing steps. Both the etch-stop and Ge transfer layers were grown at 450°C on a relaxed Ge virtual substrate after graded buffer growth in our UHVCVD reactor. The critical thickness of the Si0.4Ge0.6 etch-stop layer buried in relaxed Ge is 11 nm, but a small degree of relaxation occurs during growth, before the etch-stop is buried by the Ge transfer layer. Plan-view transmission electron microscopy reveals that the relaxation is only 0.2% and did not cause nucleation of new threading dislocations in the structure. By combining an etch-stop with the Smartcut process, the exfoliation-damaged Ge can be removed by selective chemical etching rather than CMP. H2 O2 has excellent 共⬎100:1兲 Ge etch selectivity relative to strained Si0.4Ge0.6 and can therefore be used to selectively etch the damaged Ge using a very thin 共⬍10 nm兲 etchstop layer. The inverse selectivity of our KOH-based CMP process can be subsequently used to remove the etch-stop layer relative to the underlying Ge, leaving behind a damage-free Ge surface. An added benefit of combining an etch-stop with layer exfoliation is the possibility for future ultrathin Ge-on-insulator 共GOI兲 structures,

G446


Figure 5. Cross-sectional TEM of transferred GOI structure after selective etching. 7 nm Si passivation layer is seen buried between LTO and Ge. Selective CMP can be subsequently used to remove the remaining etch-stop layer at the surface.

since the thickness of the transferred Ge layer is defined epitaxially and not by post-Smartcut CMP. Figure 4 illustrates our Ge film transfer process incorporating the etch-stop and oxide CMP layer. After growth of the virtual substrate and Ge transfer structure, a 750 nm SiO2 layer was deposited at 400°C using low pressure CVD and densified at 650°C in N2 ambient 共Fig. 4a兲. The wafer was then CMPed reducing the oxide thickness to 250 nm and implanted with H⫹ 2 to a dose of 4 ⫻ 1016 cm⫺2 at 200 keV 共Fig. 4b兲. Prior to bonding the virtual substrate of a Si handle wafer 共Fig. 4c兲, both substrates were chemically cleaned in 3 H2 SO4 : 1 H2 O2 for 10 min followed by a DI water rinse and spun dry, leaving both surfaces hydrophilic. Next, the wafers were direct bonded at room temperature and annealed at 250°C for 12 h to strengthen the bond. Layer exfoliation was carried out at 450°C for 30 min, transferring the SiO2 , Ge, and etch-stop layers to the Si handle wafer 共Fig. 4d兲. Finally, the transferred film structure was selectively etched in H2 O2 to remove the damaged Ge surface, stopping on the buried Si0.4Ge0.6 layer 共Fig. 4e兲. A selective CMP step could finally be applied to remove the remaining etch stop layer 共Fig. 4f兲. The Si0.4Ge0.6 etch-stop layer places an upper limit on the annealing temperature for our film-transfer process. Annealing experiments revealed that the buried Si0.4Ge0.6 layer is lost to interdiffusion after a 650°C anneal for ⬎6 h, after which it no longer exhibits etch-stopping behavior. It was therefore necessary to tailor our layer transfer process to stay within the bounds of this thermal budget. Results and Discussion

Figure 6. AFM surface scans showing the transferred GOI surface morphology before and after selective etching. 共a兲 Highly damaged Ge surface after layer exfoliation with surface roughness of 50 nm rms. 共b兲 After selective etching, the surface roughness is reduced to ⬍15 nm, and the crosshatch pattern of the original virtual substrate is revealed.

Figure 5 shows a cross-sectional TEM micrograph of the GOI structure after layer transfer and selective etching. This is the first demonstration of high-quality epitaxial Ge transfer from a virtual substrate to a Si handle wafer. Using an etch-stop layer, the surface damage induced by the Ge exfoliation process was removed using a selective etch rather than a CMP process, allowing for precise control of the transferred Ge thickness. The thickness of the transferred Ge is defined by the etch-stop layer, which is located at the surface of the structure in Fig. 5. The selectivity of our CMP process to Si-rich SiGe alloys could then be used to remove the etch-stop relative to the underlying Ge device layer, leaving a damage-free Ge surface suitable for device fabrication. Recall that our virtual substrates were capped with a thin Si passivation layer to protect the Ge surface during wafer processing. Because this layer is epitaxially grown directly on Ge, it contains a high density of defects resulting from the 4% lattice mismatch between Si and Ge. After bonding and film transfer, this passivation layer is incorporated within the GOI structure between the Ge and

LTO layers, as seen in Fig. 5. The effect of the Si layer will be device-specific and is expected to have the greatest influence on devices with an active region close to the Ge/Si interface. Although devices have not yet been fabricated on these GOI substrates, we can speculate that since the defects are confined to the Si they will only have a small, if any effect on devices fabricated on the Ge device layer. This is analogous to the virtual substrate where the large dislocation density in the graded region is inconsequential to devices fabricated in the uniform composition cap, where the defect density is low. In any case, for the purpose of surface passivation an alternate material such as Si3 N4 instead of epitaxial Si could be used for future GOI fabrication schemes if required for devices fabricated on these substrates. The surface morphology of the transferred film before and after selective etching is shown in Fig. 6. Figure 6a shows the surface of the as-transferred Ge film, which is heavily damaged from the ex-

Journal of The Electrochemical Society, 151 共7兲 G443-G447 共2004兲 foliation process. The roughness of the GOI at this stage of processing is ⬎50 nm rms, measured over a 25 ⫻ 25 ␮m area. After selective etching in hydrogen peroxide, the surface roughness is reduced to ⬍15 nm rms, and the crosshatch pattern of the original virtual substrate is revealed as shown in Fig. 6b. It is interesting to note that the re-emergence of the crosshatch is not caused by anisotropic etching but is a result of the Si0.4Ge0.6 etch-stop layer being grown prior to planarization of a crosshatched surface. When the peroxide etch reaches the etch-stop layer, an inverted version of the original crosshatch pattern is delineated in the transferred film. Comparing the surface morphology of the original virtual substrate with the transferred and etched Ge layer, we note that the sharp peaks of Fig. 1a correspond to the narrow valleys of Fig. 6b. On the short length scale, the surface roughness is reduced from 30 to 1.4 nm rms, as determined from an average of ten 1 ⫻ 1 ␮m AFM scans. The exceedingly high surface roughness of the as-transferred film is attributed to the large stopping distance associated with the 200 keV energy used to implant H2 ⫹ for layer transfer. This exfoliation-induced roughness is completely removed after selective etching; however lower implant energies could be used to minimize the surface damage. This is particularly achievable if the thickness of the oxide CMP layer is reduced or removed entirely. The latter requires direct CMP of the Ge virtual substrate which, if done prior to growth of the etch-stop and Ge transfer layers, will result in a crosshatch-free surface morphology in the transferred Ge film. However, this optimal solution will not be possible until planarization techniques for Ge virtual substrates are perfected. Conclusions In this work we have demonstrated a specific process for integrating Ge layers directly on large diameter Si wafers. However, we can envision a number of variants to this approach which could yield an assortment of engineered substrates. The structure fabricated in this work could be used as-is for integration of Ge photodetectors or subsequent growth of GaAs for III-V integration. The combination of layer exfoliation and Ge-selective etching could also be useful for ultrathin strained SiGe/Ge layers integrated directly on the insulator. Strained SiGe/Ge layers have been shown to have greatly improved hole mobility over conventional Si.34-36 Further benefits could be gained by fabricating such layers on insulator. Since this process does not require CMP of the device layer, the thickness of the transferred film is defined entirely by epitaxy thus allowing for the fabrication of ultrathin layers directly on the insulator. III-V compounds could be similarly integrated directly on a Si substrate by growing GaAs on a Ge virtual substrate and transferring it to Si by wafer bonding and layer exfoliation. The GaAs device layer could then be used as an etch-stop to selectively remove the Ge with a hydrogen peroxide etch. Extending this process to other III-V compounds, it is possible to compositionally grade in the Inx Ga1⫺x As system for integration of semiconductor materials with lattice constants larger than Ge. These include materials such as InP and InAs which have useful electronic and optoelectronic applications. Ultimately, wafer bonding of virtual substrates will offer the flexibility to integrate virtually any material directly on large diameter Si wafers, thus eliminating the limitations of Si and dramatically increasing the functionality of CMOS for high performance electronics and optoelectronics applications. Acknowledgments We gratefully acknowledge the funding support of the Singapore-MIT Alliance, ARO contract no. DAAG55-97-0-0111,

G447

and the MARCO Interconnect Focus Center. This work made use of the Shared Experimental Facilities supported in part by the MRSEC Program of the National Science Foundation under award no. DMR 02-13282. Discussions with T. Langdo of Amberwave Systems are gratefully acknowledged. Massachusetts Institute of Technology assisted in meeting the publication costs of this article.

References 1. H. Kroemer, T.-Y. Liu, and P. M. Petroff, J. Cryst. Growth, 95, 96 共1989兲. 2. T. H. Windhorn and G. M. Metze, Appl. Phys. Lett., 47, 1031 共1985兲. 3. R. Fischer, W. Kopp, H. Morkoc, M. Pion, A. Specht, G. Burkhart, H. Appelman, D. McGougan, and R. Rice, Appl. Phys. Lett., 48, 1360 共1986兲. 4. R. D. Dupuis, J. P. van der Ziel, R. A. Logan, J. M. Brown, and C. J. Pinzone, Appl. Phys. Lett., 50, 407 共1987兲. 5. S. Sakai, T. Soga, M. Takeyasu, and M. Umeno, Appl. Phys. Lett., 48, 413 共1986兲. 6. E. A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Mickel, Y.-J. Mii, and B. E. Weir, Appl. Phys. Lett., 59, 811 共1991兲. 7. E. A. Fitzgerald, Y.-H. Xie, D. Monroe, P. J. Silverman, J. M. Kuo, A. R. Kortan, F. A. Thiel, and B. E. Weir, J. Vac. Sci. Technol. B, 10, 1807 共1992兲. 8. M. E. Groenert and A. J. Pitera, J. Vac. Sci. Technol. B, 21, 1064 共2003兲. 9. M. E. Groenert, C. W. Leitz, A. J. Pitera, V. Yang, H. Lee, R. J. Ram, and E. A. Fitzgerald, J. Appl. Phys., 93, 362 共2003兲. 10. V. K. Yang, M. E. Groenert, G. Taraschi, C. W. Leitz, A. J. Pitera, M. T. Currie, Z.-Y. Cheng, and E. A. Fitzgerald, J. Mater. Sci.: Mater. Electron., 13, 377 共2002兲. 11. J. C. C. Fan, J. Phys. (Paris), 43, C1 共1982兲. 12. J. Haisma, B. Spierings, U. Biermann, and A. van Gorkum, Appl. Opt., 33, 1154 共1994兲. 13. G. L. Kuhn and C. J. Rhee, J. Electrochem. Soc., 120, 1563 共1973兲. 14. M. Bruel, Electron. Lett., 31, 1201 共1995兲. 15. G. A. Slack and S. F. Bartram, J. Appl. Phys., 46, 89 共1975兲. 16. S. Adachi, in Properties of Gallium Arsenide, 2nd ed., M. R. Brozel and G. E. Stillman, Editors, p. 23 INSPEC, The Institution of Electrical Engineers, London 共1996兲. 17. J. F. Klem, E. D. Jones, D. R. Myers, and J. A. Lott, J. Appl. Phys., 66, 459 共1989兲. 18. V. Lehmann, K. Mitani, R. Stengl, T. Mii, and U. Go¨sele, Jpn. J. Appl. Phys., Part 2, 28, L2141 共1989兲. 19. E. Jalaguier, B. Aspar, S. Pocas, J. F. Michaud, M. Zussy, A. M. Papon, and M. Bruel, Electron. Lett., 34, 408 共1998兲. 20. J. M. Zahler, C.-G. Ahn, S. Zaghi, H. A. Atwater, C. Chu, and P. Iles, Thin Solid Films, 403-404, 558 共2002兲. 21. S. B. Samavedam and E. A. Fitzgerald, J. Appl. Phys., 81, 3108 共1996兲. 22. S. M. Ting and E. A. Fitzgerald, J. Appl. Phys., 87, 2618 共2000兲. 23. T. Abe and J. H. Matlock, Solid State Technol., 33, 39 共1990兲. 24. M. T. Currie, S. B. Samavedam, T. A. Langdo, C. W. Leitz, and E. A. Fitzgerald, Appl. Phys. Lett., 72, 1718 共1998兲. 25. J. B. Lasky, Appl. Phys. Lett., 48, 78 共1986兲. 26. J. T. Borenstein, N. D. Gerrish, M. T. Currie, and E. A. Fitzgerald, in Etch Selectivity of Novel Epitaxial Layers for Bulk Micromachining, A. H. Heuer and S. J. Jacobs, Editors, 546, p. 69, Materials Research Society Symposium Proceedings, Boston, MA 共1999兲. 27. K. Wu, M.S. Thesis, Massachusetts Institute of Technology, Cambridge, MA 共1997兲. 28. G. Taraschi, T. A. Langdo, M. T. Currie, E. A. Fitzgerald, and D. A. Antoniadis, J. Vac. Sci. Technol. B, 20, 725 共2002兲. 29. Z.-Y. Cheng, M. T. Currie, C. W. Leitz, G. Taraschi, E. A. Fitzgerald, J. L. Hoyt, and D. A. Antoniadis, IEEE Electron Device Lett., 22, 321 共2001兲. 30. T. A. Langdo, A. Lochtefeld, M. T. Currie, R. Hammond, V. K. Yang, J. A. Carlin, C. J. Vineis, G. Braithwaite, H. Badawi, M. T. Bulsara, and E. A. Fitzgerald, in IEEE International SOI Conference Proceedings, p. 211, Piscataway, NJ 共2002兲. 31. Q.-Y. Tong, K. Gutjahr, K. Hopfe, U. Go¨sele, and T.-H. Lee, Appl. Phys. Lett., 70, 1390 共1997兲. 32. H. Moriceau, C. Maleville, A. M. Cartier, B. Aspar, A. Soubie, M. Bruel, and T. Poumeyrol, in IEEE International SOI Conference Proceedings, p. 152, Piscataway, NJ 共1996兲. 33. Z.-Y. Cheng, G. Taraschi, M. T. Currie, C. W. Leitz, M. L. Lee, A. J. Pitera, T. A. Langdo, J. L. Hoyt, D. A. Antoniadis, and E. A. Fitzgerald, J. Electron. Mater., 30, L37 共2001兲. 34. G. Ho¨ck, E. Kohn, C. Rosenblad, H. von Kanel, H.-J. Herzog, and U. Konig, Appl. Phys. Lett., 76, 3920 共2000兲. 35. M. L. Lee, C. W. Leitz, Z. Cheng, A. J. Pitera, T. A. Langdo, M. T. Currie, G. Taraschi, and E. A. Fitzgerald, Appl. Phys. Lett., 79, 3344 共2001兲. 36. C. W. Leitz, M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis, and E. A. Fitzgerald, Appl. Phys. Lett., 79, 4246 共2001兲.