mismatches are flash ADCs [3], current steering digital-to- .... IDS+IOS. (b). Fig. 2. Transistor pairing arrangements and the effects of mismatches on the.
Correlation Controlled Sampling for Efficient Variability Analysis of Analog Circuits Javid Jaffari and Mohab Anis ECE Department, University of Waterloo, Waterloo, ON, Canada N2L 3G1 {jjaffari,manis}@vlsi.uwaterloo.ca Abstract—The Monte Carlo (MC) simulation is a well-known solution to the statistical analysis of analog circuits in the presence of device mismatch. Despite MC’s superior accuracy compared with that of the sensitivity-based techniques, an accurate analysis that involves traditional MC-based techniques requires large number of circuit simulations. In this paper, a correlation controlled sampling technique is developed to enhance the quality of the variance estimations. The superiority of the developed technique is verified by variability analysis of the input-referred offset voltage of a comparator, the frequency mismatch of a ring oscillator, and the AC parameters of an operational transconductance amplifier.
I. I NTRODUCTION Due to the rapid increase of device mismatches in scaled CMOS technologies, analyzing their impact on analog circuits is an essential step toward designing a robust VLSI circuit and trading-off among performance, power, noise, and accuracy [1]. Most of the analog/mixed signal devices are designed with pairs of identical transistors. Mismatches of the electrical and physical parameters of identically designed transistors, e.g. threshold voltage, oxide thickness, effective width and length, due to ionization, CMP, and lithography variations may lead to the malfunction of a device [2]. Some examples of ananlog and mixed-signal circuits, extremely vulnerable to transistor mismatches are flash ADCs [3], current steering digital-toanalog converters [4], SRAM sense amplifiers [5], and ring oscillators [6]. Mismatch analysis can be performed by either sensitivitybased [7], [8] or Monte-Carlo (MC) based methods. In contrast to sensitivity-based techniques, where only the linear relation between mismatch and circuit parameters are taken into account, the MC simulation is the most straightforward and reliable technique for the analysis of analog circuit mismatches. Such a technique can be utilized for any form of analysis (DC,AC, and TRAN) with any number of process parameters as the convergence rate of the MC technique is independent of the problem dimension (number of the process and mismatch parameters). However, the MC analysis requires a large number of samples/simulations, typically thousands, to produce a reasonably accurate estimation. The precision of an estimation is defined in terms of the statistical confidence interval in which the actual parameter of interest lies. Unfortunately, in the crude-MC method, the confidence interval convergence rate is slow, O(N −1/2 ). This means that to achieve an estimation with times higher precision (shorter interval range), the number of samples should be boosted by 2 times increasing the design-cycle cost which consists of several analysis and redesign iterations.
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The motivating question for this research follows, if the analog circuit mismatch analysis problem is linear enough which can be analyzed through sensitivity-based techniques with an acceptable error, how can this linearity be used in the MC simulations to attain more accurate and reliable results with a lower number of samples? II. A DVANCED S AMPLING T ECHNIQUES AND THEIR W EAKNESS FOR VARIABILITY A NALYSIS In this section, we briefly review the advanced sampling techniques that have been adopted for VLSI statistical circuit analysis. It will be shown that these technique are not efficient for variance and yield analysis of high dimensional problems, like the ones frequently used in the variability analysis of analog circuit due to the curse of dimensionality. To achieve a reasonably precise estimation of the yield, a large number of samples (simulation iterations) is required is the traditional MC sampling is used. As a result, advanced sampling techniques such as, the stratified sampling, Latin Hypercube Sampling (LHS), and Quasi Monte Carlo (QMC), have been recently attracted the designers to achieve a faster convergence rate in MC-based timing analysis of digital circuits [9], [10]. A hybrid LHS-QMC SSTA method is proposed for the first time in [9], while a method is developed in [10] to generate low 2-D discrepancy QMC Sobol samples in order to further improve the convergence rate of the variance estimations. LHS method samples each dimension (process parameter) by partitioning its domain into equi-probable subranges, hence it improves the uniformity of the samples in one-dimensional projections. Whereas, the QMC utilizes lowdiscrepancy sequences to provide uniformity in higher than 1-D projections. However, the convergence rate of the QMC method is dependent to the problem dimension, and it is found to be only asymptotically superior to MC [11], unless the problem is effectively low dimension in superposition sense [12], [13]. The problem of finding the the expected value of a function of process parameters, E[f ], is effectively 1-D in superposition sense if f (p) can be mainly decomposed into sum of functions of each of the parameters alone, as d f (p) ≈ f0 + (1) fi p(i) . i=1
However, in contrast to the some of the financial computation problems that have shown superior performances using the QMC method in 90s [14], the analog circuit variability analysis is more about finding the variance of f rather than the expected value. It can be then concluded that, even if f itself is
effectively 1-D, the problem of finding the variance will be effectively 2-D, since the variance is nothing but E[f 2 ] that is composed of pairwise multiplications of the decomposed fi terms. However, the QMC sampling techniques provide a reasonably uniform 2-D projections only if a large number of samples (thousands) are used for very small number of process parameters (e.g. less than 20) [15]. In [10] a technique is proposed to improve the 2-D projection uniformity of Sobol samples. However, the confidence interval of the estimations which determines the required samples only becomes noticeably better than the traditional-MC when a very large number of samples (thousands) is used. Therefore, a runtime gain can only be obtained when a very small confidence interval is needed which is not usually the case especially for the early stage circuit analysis. In other words, no significant improvement of confidence interval is seen for small number of samples (a few hundreds). The same problem also exists for the LHS-base analysis of variability, except that for a LHS to beat MC, the problem must be effectively one dimension and not more, so its efficiency is even worse than QMC. This, in fact, does not contradict with some reported fair improvement analog circuit’s yield analysis quality using LHS in [16] where very few process parameters exists. This is because the notion of the effective dimension is only valid for high dimensional problems (e.g. more than 10) where the samples can not effectively cover the super-cubes of the problem space. For details on the curse of dimensionality and effective dimension please refer to [12]. Important sampling is another variance reduction technique adopted for efficient MC-based yield (rare-event) estimation [17], [18], [19]. However, these solution are also prone to the curse of dimensionality, and they are only effective for low dimensional problems (analog blocks with few < 10 process parameters and SRAM cells). The gain of the important sampling-based techniques vanishes rapidly as the dimension exceeds a few parameters [17] since the important regions of random variables can not be identified easily. Finally, the control variate technique is adopted in [20] for a variancereduced circuit yield estimation. Control variate is known as a promising variance reduction technique when an auxiliary model (control variable) is available. However, generating and training a secondary function that models the performance metric requires many runs of circuit simulation and should be repeated each time the circuit is modified. III. T HE P ROPOSED M ETHOD As stated earlier, one of the promising non-MC based variability analysis methods is based on analyzing the linear sensitivity of performance metrics with respect to mismatch parameters and calculating the total metric variance as the sum of the square of each linear component. However, performing extensive circuit simulations is inevitable considering the complex secondary effects in the scaled MOS transistor characteristics to obtain accurate estimation of such sensitivity measures. Moreover, the linear models may not capture the whole variation effects of the process variations on performance metrics.
In this section, an MC-based analysis technique is proposed which improves the accuracy of the traditional LHS by reducing the confidence interval range (or variance of the estimation error). This is achieved by preprocessing the samples and reducing the linear cross correlation between each pair of the process parameters inspired by the linearity of performance metrics with respect to mismatch parameters. The magnitude of the variance reduction is proportional to that of the linearity of the circuit performance metric. The more linear a metric is, the greater the variance reduction is achieved by the proposed MC technique. A. Process Variation and Assessing the Performance Metrics’ Linearity In this part, circuit examples and formulations are provided to justify the close-to-linear relations between performance metrics and process parameters. The fact that most of the metrics have close to linear relation with the process parameters are then used as an inspiration to apply a correlation controlled sampling method for the metric’s variance analysis. Suppose f (p) is the performance metric under statistical analysis. Let’s assume a least square linear regression model is constructed for f as fL (p) = a0 +
d
ai p(i) ,
(2)
i=1
2 that minimizes the error of Rd (f (p) − fL (p)) ϕ (p) dp for the process parameters with the given density of ϕ (p). The linearity of f can then be identified as [21] d 2 2 ai σp(i) σf2 . (3) l= i=1
where l < 1 so that the closer the l is to one the more linear is f . However, considering the fact that the standard deviation of each process parameter is around or less than 10% of its nominal value [2], one may consider the first order Taylor approximation of the performance metric as a sufficiently accurate approximation of the metric, leading to a close to linear, l ≈ 1, performance metric. For illustratrative purposes, the drain current of an industrial 90nm-technology NMOS is depicted with respect to its gate length varaition in Fig. 1. Although the current is an extremely non-linear function of the gate length, the curve can be approximated fairly linear around the nominal point of 100nm. In the case of σ L = 10nm, l = 72.7%, while for the σL = 5nm, l is increased to 93%. In practice, the more complex source of variation in analog circuits is through the mismatches of the identically-sized transistors imbalancing the DC drain-source currents or gatesource voltages of two symmetrical transistors as depicted in Fig. 2. The current and voltage mismatches of such arrangements can be formulated using the first order Taylor approximation, as follows [1], [22]: β2 −β1 − (VT H2 − VT H1 ) VOS,in = IgDS β m 1 − g IOS = IDS β2 −β m (VT H2 − VT H1 ) . β
(4)
Measurement
ID (uA)
120 ıL = 5nm
320
Regression for ıL = 5nm 240 Regression for ıL = 10nm
160
80 ıL = 10nm
80
40
0 70
80
90
100
110
120
0 130
Probability Density of Gate Length
160
generating samples with zero linear cross correlation. In fact, the Pearson correlation coefficients of samples decay with the rate of O(N −0.5 ) as N increases. This is also the fact when generating Latin hypercube samples. The consequent of this non-zero cross correlation is a higher estimation error, if the samples are used to determine the expected value of a function that contains interaction terms [24]. In other words, if g the function under expected value estimation has the following additive form with major Pearson product terms,
Gate Length (nm)
Fig. 1. Assessing the linearity of the drain current as a performance metric with respect to gate length variation. VDD R
R
VDD R
R
VOS,in M1
VCM,in
M2
VGS
M1
VCM,in
M2
VGS Ibias
Vbias IDS+IOS
(a)
IDS
(b)
Fig. 2. Transistor pairing arrangements and the effects of mismatches on the DC operating points: (a) current biasing: the mismatches causes the VGS to vary and (b) voltage biasing: the mismatches causes the IDS to vary. TABLE I L INEARITY OF SOME PERFORMANCE METRICS WITH RESPECT TO PROCESS PARAMETERS
Circuit Two Stage Folded Cascade OTA Technology 180 nm 24 Transistors Regenerative Comparator Technology 90 nm 9 Transistors Five-stage differential ring oscillator Technology 90 nm 45 Transistors
Metric Gain Bandwidth GBW-Product Phase Margin Power Offset Voltage
Linearity 0.973 0.971 0.946 0.941 0.997 0.946
Period
0.91
Table I lists the linearity measures of the performance metrics of three different circuits designed for 90nm and 180nm industrial technologies. The gate length, width, threshold voltage, and the oxide thickness of all transistors are varying, and their standard deviation are set as suggested by the technology. As can be seen, the linearity of the OTA parameters are high, while the comparator’s input-referred offset which should be relatively more linear than the OTA’s GBW-Product has the same linearity simply because of the higher variation in the 90 nm technology. B. Correlation Controlled Sampling The procedure of generating Gaussian random samples starts with using a pseudo-random number generator to generate uniform random samples and then applying the uniform samples numbers to the inverse of the normal cumulative function to render the samples normally [23]. However, generating independent samples does not necessarily mean
g (p) ≈ g0 +
d
gi p(i) + ajk p(j) p(k) .
i=1
j p + 1.
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