Course Syllabus

26 Aug 2008 ... Mini-project with discrete components: 25,. Main Project in VHDL: 65 (VHDL Skills: 10 + Design & Test Skills: 30 + Documentation 10 + ...

EENG 2910 Digital System Design Fall 2008 Instructor: OluwayomiAdamo - B 208 Phone: 940-891-6874, [email protected] Class Hours : Tue. 1:00 PM - 3:50 PM Office Hours: Tues. & Thurs. 3:50 AM - 4:50 PM Teaching Assistant: TBD Office Hours: TBD Prerequisite: Digital Logic Design (EENG 2710) Reference Textbooks Fundamentals of Digital Logic with VHDL Design, 2nd Ed., Stephen Brown and Zvonko Vranesic, McGraw Hill Science/Engineering/Math, 2004, ISBN: 0072499389. FPGA Prototyping by VHDL Examples, 1st Ed., Pong P. Chu, John Wiley & Sons, ISBN: 9780470185315 Course Objectives The main objectives of the course are to facilitate the students to achieve the highest levels in the Bloom's 6-level Learning Taxonomy so that they, at the end of the course, will be able toKnow what the system requirements are. Comprehend what the verbal statements on requirements mean by proper requirements analysis. Apply the knowledge of digital logic to make a feasibility study and use-case (scenario) analysis to obtain a mapping of the requirements onto system functions. Analyze the given digital system and decompose it into logical blocks involving both combinational and sequential circuit elements. Synthesize a given system starting with problem requirements, identifying and designing the building blocks, and then integrating blocks designed earlier Validate the system functionality and evaluate the relative merits of different designs. Learning Outcomes Student will: 1. Learn how to apply concepts and methods of digital system design techniques as discussed in class through hands-on projects. [a] 2. Design combinational and sequential digital systems starting from a word description that performs a set of specified tasks and functions.[c] 3. Analyze the results of logic and timing simulations and to use these simulation results to debug digital systems.[b] 4. Develop skills, techniques and learn state-of-the-art engineering tools (such as VHDL, Xilinx tools) to design, implement and test modern-day digital systems on FPGAs [i] 5. Learn through hands-on experimentation on Xilinx tools for FPGA design as well as the basics of VHDL to design and simulate digital systems. [k]

General Policy • A perfect attendance is recommended for those aspiring to get good grades because there will be constant evaluation of skills. • It is the responsibility of the students with certified disabilities to provide the instructor with appropriate documentation from the Dean of Students Office (see http://www.unt.edu/oda). • Please visit http://www.unt.edu/csrr/ for your rights and responsibilities. Grading Policy Hands-on-Exercises: 10 Mini-project with discrete components: 25, Main Project in VHDL: 65 (VHDL Skills: 10 + Design & Test Skills: 30 + Documentation 10 + Defense: 15). Topics (Tentative) 1. Introduction to project III 2. Project : Introduction to simple processor I 3. Introduction to VHDL -Intro to VHDL 4. Introduction to Xilinx design tools – software and hardware -xilinx-vhdl 5. Combinational logic design with VHDL-combinational 6. Sequential logic design with VHDL-sequential 7. Project : Introduction to simple processor II 8. State Machine design with VHDL 9. Memories 10. System design with emphasis on modularity 11. I/O Modules – UART, SRAM, VGA, Keyboard, and Mouse 12. Testing and Testability 13. Picoblaze Microcontroller overview 14. Assembly 15. I/O interface and Interrupt Interface 16. Introduction to Verilog 17. How to Write Reports-Report Writing

Tentative Schedule – Subject to change by the instructor Date 08/26/2008

09/02/2008 09/09/2008 09/16/2008 09/23/2008 09/30/2008 10/07/2008 10/14/2008

10/21/2008 10/28/2008 11/04/2008 11/11/2008 11/18/2008 11/25/2008 12/02/2008 12/09/2008

Topics • Course Introduction ( syllabus, policy, safety) • Engineering Design • Review of Logic design, Introduction to VHDL, FPGA & Xilinx design tools • Introduction to Main & Mini Project • Hands-On-Exercise : - Full Adder design, simulation & implementation • Combinational logic design using VHDL • Sequential logic design using VHDL • State Machine design using VHDL • Main Project • Memories • System design with emphasis on modularity • I/O Modules – UART, SRAM, VGA, Keyboard, and Mouse • Picoblaze Microcontroller overview • Assembly • I/O interface and Interrupt Interface • Testing and Testability • Introduction to Verilog • Main Project • Main Project Final Presentation

Resources Intro. To Digital system Design, Safety, Engineering Design, main project Tutorial

Assignment 1 Mini Project