Feb 23, 2011 ... CH03: Boolean Algebra and Combinational Logic. □ Boolean ... In other words,
if your draft final score is below 60 and you seldom appear in ...
Digital Logic Design 數位邏輯設計 Syllabus Spring, 2011 February, 23, 2011 Instructor：Lih-Jen Kau 教師：高立人 1/9
2011/02/23
Dept. Electronic Engr. National Taipei Univ. of Tech.
About the Instructor Instructor
Name： Lih-Jen Kau（高立人） Office hours: Wed. 3,4, Thur. 8,9, and Fri. 3,4 Office: 綜科 311-1 E-mail:
[email protected] Phone Number: Ext. 2242 Mobile Phone: 0933-996072
2011/02/23
2/9
Dept. Electronic Engr. National Taipei Univ. of Tech.
About the Class Class
URL: http://www.ntut.edu.tw/~ljkau Text book:
Digital Design with CPLD Applications and VHDL, 2nd Edition. by Robert K. Dueck, THOMSON DELMAR LEARNING
Reference books Digital Design, 4th Edition, by M. Morris Mano and Michael D. Ciletti, Pearson Digital Systems Design using VHDL, by Charles H. Roth, Jr. and Lizy Kurian John, THOMSON Logic and Computer Design Fundamentals, 4th Edition, by M. Morris Mano, and Charles R. Kime, Pearson Education Often selected as the textbook in NTU, NCTU, NTHU, etc Dept. Electronic Engr.
2011/02/23
3/9
National Taipei Univ. of Tech.
Lectures（1/2）
CH01: Basic Principles of Digital Systems
CH02: Logic Functions and Gates
Boolean algebra, Logic function simplification, etc.
CH04: Introduction to PLDs and Quartus II
Basic logic gates, Demorgan’s theorem, etc.
CH03: Boolean Algebra and Combinational Logic
Number system, Number representation, Truth table, etc.
PLDs, e.g., PEEL18CV8, and the Integrated Design Environment (IDE) of Quartus II, etc.
CH05: Introduction to VHDL
2011/02/23
Fundamentals of Very High speed Hardware Description Language. 4/9
Dept. Electronic Engr. National Taipei Univ. of Tech.
Lectures（2/2）
CH06: Combinational Logic Functions
CH07: Digital Arithmetic and Arithmetic Circuits
Basic combinational logic circuits, e.g., MUX, Demux, Decoder, and the usage of VHDL for the implementation of these circuits. Adder, subtracter, and their VHDL implementation.
CH08: Introduction to Sequential Logic
Latch, and basic Flip-Flops.
CH09: Counters and Shift Registers
CH10: State Machine Design CH11: Logic Gate Circuitry
State diagram, excitation table, and counter implementation.
Fan out, delay, power dissipation, and related issues. 5/9
Dept. Electronic Engr. National Taipei Univ. of Tech.
Grading Policy Grading:
Homeworks: 30% Midterm exam: 35% Final exam: 35%
Something
2011/02/23
you should be aware of:
The attendance rate will be taken into consideration whenever your draft final score lies just below 60. In other words, if your draft final score is below 60 and you seldom appear in the class, then you definitely will fail in this course, and must come again next year. On the contrary, if you are doing well in the class, and your draft final score is just below 60, then you may have the possibility passing this course. 6/9
Dept. Electronic Engr. National Taipei Univ. of Tech.
