Cryogenic MOS Transistor Model - arXiv

GENERIC COLORIZED JOURNAL, VOL. XX, NO. XX, XXXX 2018

1

Cryogenic MOS Transistor Model

arXiv:1806.02142v1 [cond-mat.mes-hall] 6 Jun 2018

Arnout Beckers, Farzan Jazaeri, and Christian Enz

Abstract— This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to zero Kelvin as a result of dopant freeze-out in cryogenic equilibrium. Explicit MOS transistor expressions are then derived including incomplete dopant-ionization, bandgap widening, mobility reduction, and interface charge traps. The temperaturedependency of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on a commercially available 28 nm bulk CMOS process. The proposed model provides the core expressions for the development of physicallyaccurate compact models dedicated to low-temperature CMOS circuit simulation. Index Terms— cryogenic MOSFET, cryo-CMOS, freezeout, incomplete ionization, interface traps, low temperature, MOS transistor, physical modeling

I. I NTRODUCTION DVANCED CMOS processes perform increasingly well from room temperature down to deep-cryogenic temperatures (< 10 K) [1]–[4]. At these temperatures the ideal switch with a step-like subthreshold slope comes within reach [5]. Furthermore, cryo-electronics [6]–[8] can provide an interface with superconducting devices on the quest for exascale supercomputing [9]. Ultimately, quantum-engineered devices controlled by cryo-CMOS circuits can bring new functionality to existing computing technologies [10], [11]. Large-scale integration of silicon spin qubits [12], [13] and cryo-CMOS control circuits is envisioned to take solid-state quantum computing to the next level [14]. Digital, analog, and RF CMOS circuits [15]–[17] are then required to operate at millikelvin temperatures for initialization, manipulation, and read-out of the qubits, as well as error correction [18], [19]. Since the cooling power at millikelvin temperatures is reduced, the system could feature a cryogenic temperature gradient, where the control circuits operate at a higher cryogenic temperature than the qubits, e.g. 4.2 K [15]. However, the

A

This project has received funding from the European Union’s Horizon 2020 Research & Innovation Programme under grant agreement No. 688539 MOS-Quito (MOS-based Quantum Information Technology) which aims to bring quantum computing to a CMOS platform. The authors are with the Integrated Circuits Laboratory (ICLAB) at the ´ erale ´ ˆ Ecole Polytechnique Fed de Lausanne (EPFL), 2000 Neuchatel, Switzerland (e-mail: [email protected]).

optimal design of power-hungry and thermal-noise dissipating circuits operating in close proximity to the qubits is yet to be explored. In this context, the main hurdle to overcome is the lack of compact MOS transistor models in circuit simulators, remaining physically accurate below 10 K [15], [17]. II. C RYO -MOS T RANSISTOR M ODELING The low-temperature circuits developed for spacecraft [20], [21], scientific equipment [22], ultra-low-noise detectors [23], cryobiology [24], and others, have been custom-designed relying on a semi-empirical approach. This approach requires laborious and expensive low-temperature measurements to extract model parameters for tuning room-temperature compact models to the target low-temperature [23], [25], [26]. Empirical temperature-scaling laws have been added to the room temperature physics-based MOS transistor model [27], [28] to capture cryogenic operation down to 4.2 K [29]–[31]. However, the discrepancy between the measured value of the subthreshold swing for a long device at 4.2 K (≈ 10 mV/decade) [3], [4], [32], and the theoretical thermal limit, UT ln 10 (≈ 0.8 mV/decade) reveals that something more fundamental is missing. As we will demonstrate along this paper, important physical phenomena at low temperatures such as interface trapping [28], [33] and incomplete ionization [34], [35] have not been properly included to date. Furthermore, the intrinsic carrier concentration, ni , takes on extremely small values below 10 K, causing arithmetic underflow in implemented analytical expressions or convergence problems in computer-aided-design simulations [36]–[38]. Therefore, standard references on semiconductor devices treat only the cryogenic equilibrium condition in bulk semiconductors above 10 K [27], [28], [39]. Analytical device-physics models, starting from the Poisson equation at low temperature, leave a gap unfilled between the zero-Kelvin approximation and 77 K [40]–[43]. In this work, we develop a MOS transistor model valid from room temperature (RT) down to deep-cryogenic temperatures, entirely based on physics principles and validated with experimental results. We start by verifying the continued validity of the Boltzmann statistics down to the deep-cryogenic regime. III. MOS E LECTROSTATICS FROM RT TO 4.2 K We model a long, planar n-channel MOS field-effect transistor in silicon, depicted in Fig. 1. Uniform operation across the width of the transistor is assumed and the gradual channel approximation is adopted. The electrostatics can then be described by the 1D Poisson equation [27], [28].

2


A. Poisson-Fermi equation

G S

D

Merging the 1D Poisson equation with the mobile carrier concentrations, n and p, given by Fermi-Dirac statistics, gives q ∂ 2 ψ(y) (1) =− −n + p − NA− , 2 ∂y εsi where q is the elementary charge, εsi the silicon permittivity, and ψ , (EF − Ei )/q the potential, with EF the Fermi-level and Ei the intrinsic energy level. The first term on the RHS of equation (1) represents the electron contribution, n, the second term the hole contribution, p, and the third term the ionized dopant-contribution, NA− . 1) Incompletely-ionized dopants: Under thermal equilibrium, both at room and cryogenic temperatures, the majority carrier concentration can defer from the implanted doping value, NA , due to incomplete ionization of the dopants. In cryogenic equilibrium, incomplete ionization is strong and known as freeze-out, since thermal dopant-ionization is very low [35]. However, during MOS operation, also field-assisted ionization comes into play. Fermi-Dirac statistics provides a fundamental way to model incomplete ionization which includes both dopant-ionization mechanisms. The concentration of ionized dopants, NA− , is then equal to the total concentration of implanted dopants times the Fermi-Dirac occupation probability of the acceptor energy EA , i.e. NA × f (EA ), or NA− =

NA

=

NA

, (2) ψA −(ψ−Vch ) UT 1 + gA e where the electron quasi-Fermi-level is given by EF,n = EF −qVch . The RHS of (2) is obtained by replacing EA −EF,n with EA − Ei + Ei − EF,n in the exponential term, and by defining an acceptor potential, ψA , (EA − Ei )/q, as indicated in Fig. 1. The channel voltage, Vch , denotes the shift of the quasi-Fermi-potential due to the drain-to-source voltage, VDS . The second expression in (2) highlights the two dopant-ionization contributions, i.e. the potential (fieldassisted ionization [35]) and temperature (thermal ionization). The acceptor-site degeneracy factor, gA , is set to four due to fourfold degeneracy (heavy-light hole, spin up-down) [28], [39]. Note that setting gA to zero is equivalent to assuming complete ionization. 2) Mobile carrier concentrations: Since n and p given by Fermi-Dirac statistics in (1) require numerical integration over energy, this inhibits explicit solutions for the charge densities and current in the MOS transistor. Expressing n and p using Boltzmann statistics allows to obtain such relations. However, the validity of the Maxwell-Boltzmann approximation down to deep-cryogenic temperatures is questionable. It has been reported [38], [42] that semiconductors become strongly degenerate at deep-cryogenic temperatures, preventing its use. This is however inconsistent with the zero-Kelvin limits of the Fermi-level position in the bandgap derived by Pierret [39]. Therefore, in the next subsection we aim to verify the Maxwell-Boltzmann approximation down to deep-cryogenic temperatures. 3) Verification of Boltzmann statistics: We numerically calculate the position of the equilibrium Fermi-level, EF , down to 100 mK relying on Fermi-Dirac statistics in an extrinsic bulk 1 + gA e

EA −EF,n kT

q

E -q

B

-q

4.2 K

Fig. 1. Schematic representation of a long nMOS transistor with annotated band diagram. The drift-diffusion and Poisson equations are solved along the x and y-directions respectively. At 4.2 K, and for NA = 1018 cm−3 , EF lies below EA in the bulk (see Fig. 2a), leading to bulk freeze-out according to (2). When EA bends under EF near the surface, the acceptor dopants become rapidly completely ionized due to field-assisted ionization. The quasi-Fermi potential is not taken into account in this figure.

semiconductor, e.g. p-type silicon. In this case, the Poisson equation imposes the charge neutrality, pp = NA− , where pp is expressed by Fermi-Dirac statistics [28], [39] and NA− by (2). This yields an implicit equation for EF , which is solved numerically at each temperature and doping value using an extension of the arithmetic precision. As illustrated in Fig. 2a, below 120 K, EF remains off the valence band edge with an offset larger than 3kT for doping values below the degenerate limit (i.e. NA = 4 × 1018 cm−3 in Si:B) [28], [39], [45]. Note that this is predicted correctly only when incomplete ionization is taken into account. Complete ionization (gA = 0) would predict an offset smaller than 3kT for NA = 1018 cm−3 , and hence a degenerate semiconductor. It should therefore be emphasized that incomplete ionization maintains the non-degeneracy of a highly-doped semiconductor at temperatures down to 100 mK. Furthermore, near zero Kelvin, EF tends to saturate at (EA − Ev )/2 for all considered doping values. This corresponds to the zeroKelvin limit in Pierret [39] assuming Boltzmann statistics. Using the now validated Maxwell-Boltzmann description for pp , i.e. Nv exp[(Ev − EF )/kT ], in pp = NA− , leads to a quadratic equation in exp [(Ev − EF )/kT ] with as solution, q EA −Ev A kT 1 + 1 + 4gA N Nv Nv e EF − Ev = kT ln + kT ln . NA 2 (3) Considering the temperature dependency of Nv [28], [39], while taking the limit of (3) to 0 K, leads to limT →0K EF = Ev + (EA − Ev )/2. Performing the same numerical EF -calculation for an intrinsic semiconductor, the extremely small value of ni can be verified relying on Fermi-Dirac statistics. The Poisson equa-

BECKERS et al.: CRYOGENIC MOS TRANSISTOR MODEL

4.2 K

3

77 K

RT

0.05

0.8

Conduction band

EA

0.045 12

NA = 10

-3

0.6

complete ionization

cm

Ec ED

incomplete ionization

0.4 18

gD = 2

-3

]Ve[ iE

-

v

-

cm

E

]Ve[

NA = 10

10

0.2

E

E

12

NA = 10

-3

cm

2 18

NA = 10

-3

]

n-type Si

10

10

12

14

10

16

Ei

p-type Si -0.2

gA = 4

3kT

cm

-3

0

F

F

EA - Ev

ND [cm

NA [cm

-3

10

]

12

10

14

10

16

-0.4

0

Ev

18

10

18

EA Ev

-0.6

Valence band -0.8 0

10

20

30

40

50

60

70

80

90

100

110

0

120

50

100

150

200

250

300

350

400

450

T [K]

T [K]

(a)

(b)

Fig. 2. Thermal equilibrium in extrinsic bulk silicon. Right: position of the Fermi-level, EF , in the bandgap as a function of doping and temperature. The EF -position is calculated from RT down to 100 mK using an extension of the arithmetic precision and an EF -resolution of 1 meV. Left: magnified view of the cryogenic regime (below 120 K). When incomplete ionization is taken into account, the distance of EF to the valence-band edge, Ev , stays larger than 3kT , validating the use of the Maxwell-Boltzmann approximation down to millikelvin temperatures. This figure applies to the bulk of the MOS transistor in all regions of operation, and to the whole body of the MOS transistor in the flatband condition. Bandgap temperature dependency is taken from Varshni [44] and a standard, temperature-independent value of EA − Ev = 0.045 eV in Si:B is assumed.

tion then imposes the charge neutrality, n = p = ni , where n and p are given by Fermi-Dirac statistics. As illustrated in Fig. 3, this yields ni -values lying outside the range of IEEE double-precision arithmetic (10−308 − 10308 ), e.g. at 4.2 K, ≈ 10−678 cm−3 . Therefore, an extension of the arithmetic precision will also be used in the remainder of this work based on Boltzmann statistics, since the carrier concentrations are then expressed through ni .

1) Derivation of the electric field at the surface: Introducing (2) for NA− in Eq. (4), and then multiplying (4) on both sides with 2(∂ψ/∂y) gives

∂ ∂y

"

∂ψ(y) ∂y

!2 # =

ψ−Vch 2q − ψ ni e UT − ni e UT εsi

NA

+

1 + gA e B. Poisson-Boltzmann equation Using the Maxwell-Boltzmann approximation of n and p, validated down to deep-cryogenic temperatures in the previous section, we combine the 1D Poisson equation with Boltzmann statistics, which leads to ψ−Vch q ∂ 2 ψ(y) − Uψ − UT (4) =− −ni e + ni e T − NA , ∂y 2 εsi where UT , kT /q is the thermal voltage. The first term on the RHS of equation (4) represents the electron contribution, n, and the second term the hole contribution, p. The intrinsic car√ rier concentration is given by ni = Nc Nv exp(−Eg /2kT ), with Eg the bandgap, and Nc and Nv the effective density-ofstates in the conduction band and valence band respectively. The temperature-dependency of Eg as described by Varshni [44] is used. The extremely small, but finite value of ni at deep-cryogenic temperatures cannot be assumed zero—which would be equivalent to the zero-Kelvin approximation [40] or considering f (E) as a step function—since this leads to zero mobile carrier concentrations independently of the potential. This is irreconcilable with the observed field-effect and correct functioning of the MOS transistor at 4.2 K [3], [5]. For UT small, the exponential factor has a very big dynamic range when ψ changes during MOS transistor operation, large enough to overrule ni in the multiplication.

ψA −(ψ−Vch ) UT

!

(5) ∂ψ . ∂y

Integrating (5) from bulk to surface with E = −∂ψ/∂y and Eb = 0 yields E2s

2q = εsi

Z

ψs

ni e

ψ−Vch UT

− ni e

− Uψ

T

ψb

+

NA 1 + gA e

ψA −(ψ−Vch ) UT

(6)

! dψ.

In (6) the additional potential dependence due to field-assisted ionization of the dopants can be straightforwardly integrated as well, i.e. by replacing NA with NA {1 + gA exp[(ψA − (ψ − Vch ))/UT ] − gA exp[(ψA − (ψ − Vch ))/UT ]} in the numerator of the third term and splitting the resulting integral. This gives an expression for the square of the electric field at the surface, ψ −V ψb −Vch Ψ s ch 2qni UT − Ψs − b e UT − e UT + e UT − e UT E2s = εsi " # (7) 2qNA fs (EA ) + ψs − ψb − UT ln , εsi fb (EA ) where ψb , (EF,b − Ei )/q is the bulk potential and ψs , (EF,s −Ei )/q the surface potential, as indicated in Fig.1. EF,s denotes the Fermi-level at the surface, and EF,b the Fermilevel in the bulk. The logarithmic term in (7) is the contribution

4


of incomplete ionization, where 1

fs (EA ) ,

1 + gA e

EA −EF,s kT

1

= 1 + gA e

ψA −(ψs −Vch ) UT

(8)

the Fermi-Dirac ionization probability at the surface, and fb (EA ) ,

1 1 + gA e

EA −EF,b kT

=

1 1 + gA e

ψA −ψb UT

,

(9)

the Fermi-Dirac ionization probability in the bulk, assuming that Vch is zero in the bulk. Both ionization probabilities are qualitatively shown in Fig. 1. If complete ionization is assumed, then fs (EA ) = fb (EA ) = 1 and the incomplete ionization term cancels in (7), leading to the expression widely-used at RT [27], [28]. The surface-ionization probability fs (EA ) is plotted in Fig. 4 as a function of thermal and field-assisted ionization. Immediately evident is that freezeout at the surface (arbitrarily defined when fs (EA ) < 0.2) is only present when the temperature is below ≈ 50 K and the potential is close to the flatband condition (ψs ≈ ψb ). Above ψb , the ionization probability rapidly transitions to one due to field-assisted ionization. This transition corresponds to the bending of EA under EF at the surface in Fig. 1. Therefore, complete ionization is a valid approximation even at deep-cryogenic temperatures, although the shift in EF due to incomplete ionization (Fig. 2a) should be taken into account since it affects the threshold voltage. This EF -shift can be quantified by using fb (EA ) from (9) in the bulk charge neutrality condition, pp = NA− , which leads to the quadratic equation exp(2ψb /UT ) − (ni /NA ) exp(ψb /UT ) − (gA /NA ) exp(ψA /UT ) with as solution, q ψA 1 + 1 + 4 NnAi gA e UT ni . (10) + UT ln ψb = UT ln NA 2 The second term in (10) is the shift of EF by including incomplete ionization, which is only dependent on temperature and doping. Assuming complete ionization, i.e. gA = 0, the well-known UT ln(ni /NA ) is obtained. 2) Derivation of the charge densities: Applying the Gaussian law over the semiconductor body in Fig. 1, the total semiconductor charge density per unit area, Qsc , is obtained by Qsc = −εsi Es , with Es given by (7). The obtained Qsc is plotted in Fig. 5a at RT, 77 K, and 4.2 K. For 77 K and 4.2 K, small kinks are noticeable close to ψb due to the transition from incomplete to complete ionization when EA bends under EF at the surface (EF,s ), or equivalently, ψs becomes less negative than ψA . Above this transition, fs (EA ) ≈ 1 according to (2). At RT, EF lies above EA in the flatband condition (see Fig.2b) and hence no transitional kink is noticeable. There is however a ψb -shift also at RT due to incomplete ionization according to (10). Note that for complete ionization (dashed lines) no kinks are observed since the logarithmic term cancels in (7). Assuming the charge-sheet and fully-depletion approximations [27], the fixed charge density per unit area, Qf , is given by s 2qNA UT 2qNA fs (EA ) ψs − ψb − ln . (11) Qf = −εsi εsi εsi fb (EA )

Fig. 3. The intrinsic carrier concentration reaches extremely small values at 4.2 K, left: Fermi-Dirac distribution function approaching a step function at 4.2 K, middle: density-of-states in the conduction band, right: overlap between the density-of-states in the conduction band and the Fermi-Dirac distribution function at 4.2 K, 77 K and room temperature (RT). The overlap function gc (E) × f (E) becomes extremely small in magnitude and very peaked at 4.2 K. The area under the overlap function is equal to the intrinsic carrier concentration. Bandgap temperature-dependency used from Varshni [44] and effective mass values from Pierret [39].

Relying on the charge neutrality, the mobile charge density per unit area, Qm , can be obtained from Qm = Qsc − Qf , resulting in Eq.(12). Qm is plotted in Fig. 6a for RT, 77 K, and 4.2 K. As can be observed in this figure, incomplete ionization does not affect the turn-on rate of Qm , but contributes a small decrease in the charge threshold voltage, due to the shift of the EF -position closer towards the conduction-band edge as shown in Fig. 2a and derived in (10). Therefore, from this section we conclude that incomplete ionization cannot explain the offset between the measured subthreshold swing at 4.2 K and the thermal limit. As we will show in the next section, the temperature-dependent occupation of interface charge traps can degrade the subthreshold swing down to 4.2 K. 3) Interface charge traps: Defects and lattice breaking at the oxide-semiconductor interface introduce trap energy levels, Et , in the bandgap which degrade the control of the gateto-bulk voltage, VGB , over the channel. In what follows, the Fermi-Dirac occupation of interface traps, f (Et ), is included in the surface-boundary condition and the effect on the Qm turn-on rate is analyzed at 4.2 K. The surface-boundary condition, i.e. the link between VGB and ψs , is given by VGB = VFB + εsi Es /Cox + (ψs − ψb ) where Cox is the oxide capacitance per unit area, and VFB is the flatband voltage, given by VFB , φms − Qit /Cox [27], [28]. Here Qit is the interface trap charge density per unit area. We consider the summation of the discrete acceptor trap energy levels (all donor states are occupied and neutral during turn-on in nMOS [28]). Each discrete trap-energy-level, Et,j , at position j in the bandgap has its particular N it,j -value assigned to it, where N it is the density-of-interface-traps per unit area. Qit can then PN be expressed as Qit = −q j N it,j fs (Et,j ) where N is the number of interface traps, and 1

fs (Et,j ) = 1 + gt e

Et,j −EF,s kT

1

= 1 + gt e

ψt,j −(ψs −Vch ) UT

, (13)


Qm

5

v v " # " # u u ψb −Vch u 2qni UT ψs −Vch u 2qNA 2qNA fs (EA ) fs (EA ) t UT UT = −εsi −e + e ψs − ψb − UT ln + εsi t ψs − ψb − UT ln εsi εsi fb (EA ) εsi fb (EA )

(12)

is the Fermi-Dirac occupation probability of the trap energy level Et,j . The RHS of Eq. (13) is obtained by defining the trap potentials, ψt,j , (Et,j − Ei )/q [46]–[48]. This leads to the flatband voltage

Therefore, starting from the drift-diffusion equation gives Z Z W Qm,D W ψs,D µn Qm dψ + µn UT dQm . (15) IDS = − L ψs,S L Qm,S

N q X Nit,j VFB = φms + . Cox j 1 + gt exp{[ψt,j −(ψs −Vch )] /UT } (14) Plotting Qm from (12) versus VGB at 4.2 K in Fig. 6b, including four interface traps close to the conduction band, reveals how each interface trap degrades the turn-on of Qm separately, as well as the combined effect of the sum of the interface traps.

Assuming a linearization of the mobile charge density with respect to the surface potential at constant gate voltage [49] in (15), i.e., Qm = mCox (ψs −ψP ), with m , ∂(Qm /Cox )/∂ψs and ψP the pinch-off potential, and integrating, results in an expression for the total drain-source current in saturation, # " Q2m,D − Q2m,S W IDS = µn − +UT (Qm,D − Qm,S ) . (16) L 2mCox

IV. C URRENT DERIVATION To derive the current in the linear regime, this core-model assumes drift-diffusion transport, and does not include ballistic nor quantum transport. To verify the drift-diffusion transportmechanism at cryogenic temperatures, the proposed model for the drain-to-source current will be experimentally validated in Section V. Neglecting the hole-contribution to the current, the expression for total drain-source current is given by IDS = R Vthe DB −µn (W/L) VSB Qm (Vch )dVch , where the electron mobility µn is assumed constant along the channel, and W/L is the device aspect-ratio, as indicated in Fig. 1. In the linear regime, Qm can be assumed independent of Vch . In this case, the total drain-source current is given by IDS = −µn (W/L)Qm VDS . In saturation, the integral over Vch cannot be readily solved.

Fig. 4. Dopant ionization at the surface is an interplay between thermal ionization (T ) and field-assisted ionization (ψs − ψb ). Freeze-out is assumed when 20 % of the dopants are ionized. This happens only when T is below ≈ 50 K and close to the flatband condition (ψs ≈ ψb ). When ψs increases, a rapid transition takes place to complete ionization for all temperatures. In the flatband condition (ψs = ψb ) the ionization probability at the surface is only due to thermal ionization and equals the ionization probability in the bulk, fb (EA ).

Qm,S and Qm,D are obtained from (12), setting Vch to zero and VDS respectively. At cryogenic temperature an improvement in the low-field mobility, µ0 , is observed due to a reduction of the phonon scattering [1], [6]. In addition, the mobility reduces at higher gate voltage due to surface roughness scattering at high vertical electric field [1]. This mobility reduction can be modeled by µn = µ0 /(1 + θVGB ) where θ is the mobility reduction factor. V. E XPERIMENTAL R ESULTS AND DISCUSSION Room temperature and cryogenic measurements were performed on devices fabricated in a 28-nm bulk CMOS process. The full set of measurements, measurement set-up, and characterization were previously reported in [3], [4]. After measuring at RT, the samples were immersed into liquid helium (4.2 K) and liquid nitrogen (77 K) baths with a dipstick. Fig. 7a favorably compares the model with the linear transfer characteristics (VDB = 20 mV) measured at RT and 4.2 K on a long nMOS device with W/L = 3µm / 1µm, in linear and logarithmic scales. The extracted µ0 -values from the model are in accordance with the characterization performed in [3]. Furthermore Fig. 7b analyzes the effect of incomplete ionization, interface traps, and mobility, on the current at 4.2 K. Note that incomplete ionization reduces the threshold voltage, and interface traps can degrade the subthreshold swing (SS) to ≈ 10 mV/decade. The strong increase in the mobility increases the on-state current at 4.2 K. Fig. 8 validates the model for the current in saturation (|VDB | = 0.9 V) using the measurements performed at RT, 77, and 4.2 K on a long pMOS device with W/L = 3µm / 1µm, in linear and logarithmic scales. The metal-semiconductor work function difference, φms , increases in absolute value at lower temperatures according to the change in EF -position (Fig. 2). VI. S UBTHRESHOLD - SWING DERIVATION In this section a SS-expression including incomplete ionization and temperature-dependent interface trapping is derived. Incomplete ionization is included to prove the minimal influence on SS shown in Fig.7b. The temperature-dependency

6


-6

-7

1x10

7x10

18

77

NA = 10

300

Incomplete ionization Complete ionization

6

4.2

0.8

3

-

cm

4.2

]

77

cs

NA = 10

Q|

0.4

mc C[ | fQ|

18

3

-

cm

]

2-

mc C[ |

2-

5

0.6

T [K]: 4.2, 77, 300

4

3 77 K

2

4.2 K

0.2

RT

Incomplete ionization

1

Complete ionization

0

0

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

-0.6

-0.4

-0.2

y (a)

0

y -

Vch [V]

s

s

0.2

0.4

0.6

Vch [V]

(b)

Fig. 5. (a) Total semiconductor charge density, Qsc , and (b) fixed charge density, Qf , at room temperature (RT, red), liquid-nitrogen temperature (77 K, green), and liquid-helium temperature (4.2 K, blue) including incomplete ionization (solid lines) or assuming complete ionization (dashed lines). The potential is swept starting from the bulk potential, ψb , calculated at a given temperature and doping according to (10). Horizontal arrows show the shifts in ψb by including incomplete ionization at a given temperature. Skewed arrows in the insets indicate the kinks at 77 and 4.2 K due to the transition from incomplete to complete ionization when EA bends under EF (Fig. 1). -6

2-

]

f

= -0.7 V

Nit,

= 0

ms

0.6

T [K]

= 0

-|

10

77

300

Q|

m

Incomplete -11

Complete

10

0.2

Q|

-10

10

0.4

-9

-10

10

f

= 10

4.2

j

ms

-2

cm

= -0.7 V

Vch

without traps

y y y y

= 0

gt = 4

m

Q| = |

cs

4.2

11

Nit,

10 mc C[ |

Vch

j

10

0.8

2-

-9

cm

-8

-8

10

-3

18

NA = 10

cm

]

mc C[ | fQ|

10

10

1x10

-3

18

NA = 10 -7

-7

-6

10

-11

10

-12

gA = 4

0.2

0.4

0.6

0.8

1

t, j

t, j

=

0.58 V + 3UT

=

0.58 V + 2UT

=

0.58 V + UT

=

0.58 V

10

-2

Cox = 20 mF m -13

0

10

t, j

sum

4.2 K

-2

Cox =20 mF m

-12

t, j

10 0.72

1.2

0.73

0.74

VGB [V]

VGB [V]

(a)

(b)

0.75

0.76

Fig. 6. Mobile charge density, (a) without interface traps at RT, 77 K and 4.2 K including incomplete ionization (solid lines), and assuming complete ionization (dashed lines). Incomplete ionization yields a small decrease in the charge-threshold voltage, (b) Influence of four single interface traps close to the conduction band, and their combined effect on the turn-on rate of Qm at 4.2 K.

of interface-trap occupation, fs (Et ), allows to obtain the ∆SS -offset of ≈ 10 mV/dec above the thermal limit, UT ln 10, previously observed on long-channel devices [3], [4]. The subthreshold swing, SS, is usually expressed as nUT ln 10, where the non-ideality factor or slope factor, n, is given by (∂VGB /∂ψs ), describing the deviation from the thermal limit. Assuming fs (E t ) from one, (∂VGB /∂ψs ) √ (13) to be √ yields 1 + 2qNA εsi / Cox (2 ψs − ψb ) + qN it /Cox [27], [50]. However, at 4.2 K, and assuming the highest possible doping value below the degenerate limit, a large N it -value in the order of 1013 cm−2 is extracted to accommodate for a SS of ≈ 10 mV/decade [33], [51], since N it becomes multiplied with UT in this expression. However, it should be emphasized that in the used expression for SS, the temperature dependency of interface-trap occupation is not taken into account. Relying Vch on drift-diffusion transport in the linear regime and assuming µ independent of VGB , the subthreshold slope, SS −1 , is given by

The factor (1/Qm )(∂Qm /∂ψs ) is found from (12) by considering Qm Qf or Qsc ≈ Qf in the subthreshold region. After some mathematical manipulation, we find " ψs −Vch 1 ∂Qm 1 = qεsi n i e UT Qm ∂ψs Qm Qf # (18) 1 UT ∂f (EA ) . − 2 NA 1 − Qf f (EA ) ∂ψs Merging (11) and (18), and inverting, gives h i A) 2NA ln 10 ψs − ψb − UT ln ffb(E (EA ) ∂VGB SS = . (19) ψs −Vch Qf ∂ψs UT ∂f (EA ) UT n e −N 1 − i A Qm | f (EA ) ∂ψs {z } (a)

= 0

SS −1 =

1 1 ∂Qm ∂ψs . ln 10 Qm ∂ψs ∂VGB

(17)

The following relation can be derived for (a) in the above equation (see Appendix), h i A) 2NA ψs − ψb − UT ln ffb(E ψs −Vch (E ) Q A m ni e UT = . (20) Qf UT


7

-2

nMOS W/L = 3 µm / 1 µm VDB = 20 mV Cox = 20 mF m

-4

30

2

Measurement

m

Model

Nit,j = 1.2 x 10

-2

cm

f

2

Complete ionization

=

=

1.2 x 10

20

cm 15

Nit,

-7

10

10

q = 0.1

4.2

gt = 4,

18

gA : 4

-3

cm 0

0.5

0.6

0.7

0.8

= 0

0

-8

10 0.4

j

j

5

gA = 4

NA = 10

-8

0.3

Nit,

10

298 -7

0.2

-6

10

I

T [K]

SD

0.78 V

I

SD

= -

ms

-2

]A[

]A[

f

4.2 K

300 cm /Vs 11

Nit,j

ms

10

I

0

= - 0.83 V

SD

m

m

Incomplete ionization

25 -5

10

-6

Measurement

11

-5

10

0

10

750 cm /Vs

=

]Aµ[

-4

10

0.9

10 0.5

0.55

0.6

0.65

0.7

0.75

0.8

VGB [V]

VGB [V]

(a)

(b)

Fig. 7. (a) Linear model validation with measurements at RT and 4.2 K on a long nMOS device (28-nm bulk CMOS process). In the measurements the gate voltage was swept from 0.2 V to 0.9 V with a step size of 1 mV in order to reliably resolve the steep subthreshold slope at cryogenic temperature. The sets of used physical model parameters are shown. Five interface traps are placed at ψt,j = 0.58 V − 2UT : UT : 0.58 V + 2UT , (b) Overview of the phenomena influencing the current at 4.2 K: incomplete ionization (gA = 4) leads to a decrease in the threshold voltage; interface traps (N it,j ) strongly degrade the subthreshold swing, and mobility (µ) increases the on-state current.

-2

pMOS W/L = 3 µm / 1 µm VBD = 0.9 V

Cox = 20 mF m 60

2

Measurement

m

Model

10

f

2

]A[

-6

ms

=

5 x 10

= -

40 -2

cm

0.81 V

30

4.2

I

DS

f

50

130 cm /Vs 10

10

ms

-2

cm

= - 0.87 V

I

=

325 cm /Vs

DS

0

Nit,j

=

11

-5

m

0

Nit,j = 1.2 x 10

T [K]

20

gt = 4

298

]Aµ[

-4

10

-7

10

gA = 4

77

10

q = 0.9 18

NA = 10

-8

-3

cm 0

10 0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VBG [V]

Fig. 8. Saturation model validation with measurements at RT, 77 K and 4.2 K on a long pMOS device (28-nm bulk CMOS process). Four interface traps are placed at ψt,j = 0.58 V − 2UT : UT : 0.58 V + UT . The used physical model parameters for RT and 4.2 K are shown in the figure. For 77 K, the model parameters are: φms = −0.87 V, Nit,j = 1.1 × 1011 cm−2 , and µ0 = 300 cm2 V−1 s−1 .

Plugging this in (19) one finds 1

SS = UT ln(10)

UT

1− h 2

∂fs (EA ) UT 1− f (E ∂ψs s A)

ψs −ψb −UT ln

∂VGB , ∂ψs

fs (EA ) fb (EA )

(21)

i

√

s (EA ) 1 − fsU(ETA ) ∂f∂ψ 2qNA εsi s q Cox 2 (ψ − ψ ) − U ln fs (EA )

s

b

Taking the derivative of (13), (23) becomes √ ∂VGB 2qNA εsi 1 √ =1+ ∂ψs Cox 2 ψs − ψb (24) q 1 X gt exp[(ψt,j − ψs )/UT ] + . N it,j 2 Cox UT j {1 + gt exp[(ψt,j − ψs )/UT ]} Note the appearance of a factor 1/UT in the third term on the RHS of (24). Placing a discrete interface trap, ψt,j , at each ψs -value in the subthreshold region, and assuming a uniform N it,j -value for each trap, leads to √ ∂VGB 2qNA εsi 1 qN it 1 gt √ =1+ + . ∂ψs Cox Cox UT (1 + gt )2 2 ψs − ψb (25) The first two terms in (25) yield the non-ideality or slope factor without interface traps, n0 . The SS-expression becomes SS = n0 UT ln 10 +

where ∂VGB =1+ ∂ψs

follows from the surface-boundary condition derived in Sec. III-B.3. In the subthreshold region, far above the flatband condition, fs (EA ) = 1 can be assumed (Fig. 4), and UT 2(ψs − ψb ), leading to SS = UT ln 10(∂VGB /∂ψs ) with √ ∂VGB 2qNA εsi 1 √ =1+ ∂ψs Cox 2 ψs − ψb (23) ∂fs (Et,j ) q X N it,j . − Cox j ∂ψs

T

fb (EA )

q X ∂fs (Et,j ) − N it,j . Cox j ∂ψs (22)

gt qN it ln 10 Cox (1 + gt )2

(26)

where the second term on the RHS is the sought ∆SS -offset. The non-ideality factor n0 has an upper bound of 2 mainly related to doping. Therefore, at 4.2 K, the first term on the RHS of (26) is limited by 1.6 mV/decade. Note that N it does not become multiplied with UT in (26). Therefore, assuming a reasonable value for N it = 3 × 1011 cm−2 , the second term gives ≈ 9 mV/decade (with Cox = 20 mF m−2 and gt =4).

8


Together they yield the SS-degradation observed on a long nMOS device at 4.2 K. At 77 K, a similar calculation using n0 = 1.08 and Nit = 3 × 1011 cm−2 gives 25 mV/dec, corresponding to the subthreshold swing measured [3] on a long pMOS device at 77 K (Fig. 8). VII. C ONCLUSION A theoretical MOS transistor model is developed valid from room temperature down to liquid-helium temperature. The model relies on Boltzmann statistics, verified in the limit to zero Kelvin, and includes incomplete ionization, interface traps, bandgap temperature dependency, and mobility reduction. It is evidenced that incomplete ionization maintains the non-degeneracy of a semiconductor at deep-cryogenic temperatures, and leads to a decrease in the threshold voltage on top of the overall increase due to Fermi-Dirac distribution scaling. The Fermi-Dirac temperature-dependency of interface-trap occupation degrades the subthreshold swing down to 4.2 K. An expression for the subthreshold swing including incomplete ionization and temperature-dependent interface trapping is derived. The proposed model builds the indispensable physical foundation for future low-temperature CMOS circuit design. A PPENDIX Starting from Qm +Qf = Qsc , we can write (Qm +Qf )2 = with Es given by (7). Solving a quadratic equation for Qm leads to s 2qni UT εsi ψsU−Vch Qm e T (27) = −1 + 1 + Qf Q2f ε2si E2s ,

where we neglected the exponential √ term in ψb /UT . In the subthreshold region (Qm Qf ), 1 + x can be approximated by 1 + x/2 for x → 0. Using (11) for Q2f leads to (20). R EFERENCES [1] F. Balestra and G. Ghibaudo, “Physics and performance of nanoscale semiconductor devices at cryogenic temperatures,” Semiconductor Science and Technology, vol. 32, no. 2, p. 023002, Feb. 2017. [2] M. de Souza, V. Kilchtyska, D. Flandre, and M. A. Pavanello, “Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs,” in 2012 IEEE International SOI Conference (SOI), Oct 2012, pp. 1–2. [3] A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto, and C. Enz, “Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing,” in 2017 47th European Solid-State Device Research Conference (ESSDERC), Sept 2017, pp. 62–65. [4] A. Beckers, F. Jazaeri, and C. Enz, “Characterization and Modeling of 28 nm Bulk CMOS Technology down to 4.2 K,” IEEE Journal of the Electron Devices Society, pp. 1–1, 2018. [5] C. Rogers, “MOST’s at cryogenic temperatures,” Solid-State Electronics, vol. 11, no. 11, pp. 1079 – 1091, 1968. [6] R. Kirschman, “Cold electronics: an overview,” Cryogenics, vol. 25, no. 3, pp. 115 – 122, 1985. [7] E. A. Gutierrez-D, J. Deen, and C. Claeys, Low temperature electronics: physics, devices, circuits, and applications. Academic Press, 2000. [8] F. Balestra and G. Ghibaudo, Device and Circuit Cryogenic Operation for Low Temperature Electronics. Springer US, 2001. [9] D. S. Holmes, A. L. Ripple, and M. A. Manheimer, “Energy-Efficient Superconducting Computing: Power Budgets and Requirements,” IEEE Transactions on Applied Superconductivity, vol. 23, no. 3, p. 1701610, 2013.

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9