Cu Hybrid ... - IEEE Xplore

0 downloads 7 Views 1MB Size Report
High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high ...

High Density 3D LSI Technology using W/Cu Hybrid TSVs. M. Murugesan1, H. Kino2, A. Hashiguchi2, C. Miyazaki3, H. Shimamoto3, H. Kobayashi3, T. Fukushima1, T. Tanaka2, and M. Koyanagi1 1

New Industry Creation Hatchery Center, NICHe; 2Inst. of Biomedical Engineering, Tohoku University; 3ASET 6-6-01AzaAoba,Aramaki,Aoba-ku, Sendai, 980-8579, Japan Phone: +81-22-795-4119; Fax: +81-22-795-6907; E-mail: [email protected]

Abstract High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high density 3D LSIs such as (i) thermo-mechanical stress exerted by W TSVs used for signal lines and Cu TSVs used for power/ground lines in active Si, (ii) external gettering (EG) role played by sub-surface defects in thinned Si substrate, and (iii) effect of local stress induced by P-bumps on device characteristics are discussed. By annealing at the temperature of •300Υ, both Cu (via size ”10Pm) and W (via size ”1Pm) square TSVs induce only compressive stress at small TSV spacing which will seriously affect the mobility in active Si area, and thus device characteristics. Large compressive stress not only leads to extrusion and peeling of TSV metal, but also die cracking, and it will adversely impact on the reliability of 3D-LSIs. Then it was proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI. Sub-surface defects at dry polished (DP) surface well act as potential EG sites for Cu contamination. Influences of mechanical stress induced by P-bumps on device characteristics were also evaluated and ultra-small size In-Au P-bump technology has been developed to minimize the influences of P-bumps on device characteristics. Introduction 3D integration is an enabling technology to realize high-performance and low-cost system on chip by vertically stacking several functional dies that are interconnected by embedded TSVs and P-bumps. Although Cu is widely used for interconnects [1] due to its lower resistance and improved electro migration properties, meticulous care is required not only to keep the contamination risks minimized [2], but also it is difficult to fill sub-micron via (I=0.6~1Pm). High end 3D-LSI die requires more than 104 to 105 P-bumps and TSVs per chip and the die thickness of

Suggest Documents