Advanced Scalable Ultralow-k/Cu Interconnect Technology for 32 nm CMOS ULSI Using Self-Assembled Porous Silica and Self-Aligned CoWP Barrier T. Kikkawa1,3, S. Chikaki2, R. Yagi2, M. Shimoyama2, Y. Shishida2, N. Fujii2, K. Kohmura2, H. Tanaka2, T. Nakayama2, S. Hishiya2, T. Ono2, T. Yamanishi2, A. Ishikawa2, H. Matsuo2, Y. Seino1, N. Hata1, T. Yoshino1, S. Takada1, J. Kawahara2, and K. Kinoshita2 1
MIRAI, National Institute of Advanced Industrial Science and Technology (AIST) 2 MIRAI, Association of Super-Advanced Electronics Technologies (ASET) SCR bldg., AIST-Tsukuba-West, Tsukuba, 305-8569 Japan, Phone: +81-29-849-1569, fax: +81-29-849-1528, 3 Research Center for Nanodevices and Systems, Hiroshima University Higashi-Hiroshima, 739-8527, Japan, Phone: +81-82-424-7879, fax: +81-82-424-3499, E-mail:
[email protected]
Abstract An advanced scalable Cu damascene process was developed using self-assembled porous silica with tetramethylcyclotetrasiloxane (TMCTS) treatment and selective electroless plating of Cu barrier. It is found that the TMCTS vapor treatment could recover process-induced damages after plasma ashing and chemical mechanical polishing, resulting in no line-width dependence of the effective dielectric constant of the porous silica films. Furthermore, the selective electroplating of CoWP on Cu interconnects could suppress Cu drift and improve time-dependent dielectric breakdown of the porous silica film. Introduction The performance of MOS transistors has been improved by introducing the scaling rule to the device dimension [1]. On the contrary, the performance of the interconnects in signal delay has been degraded by scaling multilevel interconnect dimensions due to the parasitic capacitances and resistances [2]. Therefore, the interlayer dielectric films with ultralow dielectric constants (k) are needed for ultrahigh-speed digital integrated circuits and radio-frequency mixed-signal circuits to reduce parasitic capacitances of metal interconnects. However, further reduction in k values requires more porosity in the low-k film, resulting in elastic modulus reduction. To solve the reduction of mechanical strength, we have developed scalable self-assembled porous silica films and tetramethylcyclotetrasiloxane (TMCTS) vapor treatment that could improve the elastic modulus of the porous silica film [3-5]. Ultralow-k porous silica film is also sensitive to process-induced damages caused by plasma ashing and wet chemical processes. It is necessary to develop damage-less processes or recover the process-induced damages in porous silica films [6]. The purpose of this work is to develop an advanced ultralow-k porous-silica/Cu damascene process that can achieve damage-free and scalable low-k properties with self- aligned Cu barrier metal for 32 nm CMOS ULSI.
orthosilicate (TEOS) in ethanol diluted with water. The film was calcined in oxygen or nitrogen atmosphere so that the template surfactant was evaporated, resulting in the formation of non-periodic porous silica film [5, 6]. Fig. 1 shows a schematic diagram of a formation process of an ultralow-k film by use of a self-assembly technology. The pore-wall surfaces in the porous silica film were covered with tetramethyl-cyclotetrasiloxane (TMCTS) at 400°C after calcination [3-6]. Porous silica low-k/Cu damascene structure was formed on a 300 mm Si wafer using ArF photolithography. The thickness of Cu barrier must be reduced according to the scaling rule of the ULSI devices. Conventional barrier metals such as sputtered TaN can not cover the Cu interconnect without alignment and barrier dielectric films such as SiN have higher dielectric constants. Therefore, selective deposition of barrier metal and low-k barrier dielectrics are needed [7]. Selective electroless plating of cobalt tungsten phosphorous (CoWP) on Cu interconnects and divinylsiloxanebis-benzocyclobutene (DVS-BCB) cap layer were developed as scalable Cu barriers [8].
Results and Discussion Small-angle X-ray scattering analyses of the porous silica films with different process conditions were carried out as shown in Fig. 2(a). A sharper distribution of pore sizes was obtained by calcination and ultraviolet (UV) light irradiation at 350˚C in nitrogen atmosphere than calcination in 20%-O2 ambient. The pore size distribution was also controlled by the concentration of the surfactant in the precursor solution. Corresponding relative ionic component of skeletal silica is shown in Fig. 2(b). The elastic modulus of skeletal silica was evaluated by ionic component of dielectric constant for silica, i.e., relative bond ionicity. The ionicity after the 350°C calcinations and UV light irradiation in nitrogen atmosphere was as high as that after the conventional calcinations in the presence of oxygen at 400˚C as shown in Fig. 2(b), indicating that the same mechanical strength was obtained. Fig. 3(a) and 3(b) show dielectric constant versus porosity of Fabrication of Low-k/Cu Damascene self-assembled porous silica and elastic modulus versus A porous low-k silica film was formed by spin-coating of a porosity, respectively. The dielectric constant and elastic precursor solution of nonionic surfactant such as polyoxy- modulus of porous silica can be controlled by molar ratio of ethylene-polyoxypropylene-polyoxyethylene (EO)13(PO)20 surfactant/Si in the precursor solution as shown in the inset. (EO)13 and an acidic silica sol derived from tetraethyl- The dielectric constant of the porous silica changed from 2.75
0-7803-9269-8/05/$20.00 (c) 2005 IEEE
to 2.0 by changing the porosity from 40 to 60%. Correspondingly, the elastic modulus changed from 14 to 4 GPa. Further improvement of the elastic modulus of the film was achieved by increasing the concentration of polymerization promoter of silica oligomer from 0 to 0.13 relative to silica molecule as shown in Fig. 4. Process-induced damages due to He/H2 plasma ashing processes in a remote plasma asher or a parallel plate plasma resulted in the increase of Si-OH bonds in the porous silica films as shown in Fig. 5. The Si-OH bonds significantly decreased after TMCTS treatment. Fig. 6 shows Weibull plot of the dielectric constants of porous silica films derived from interline capacitances in Cu/low-k damascene structures after He/H2 and NH3 plasma ashing processes followed by TMCTS treatment. The dielectric constants of the porous silica films increased from 2.0 to 4.0 and 3.5 after NH3 and He/H2 plasma ashing processes, respectively. The damaged dielectric constants were recovered to 2.5 and 2.0, respectively, by TMCTS treatment. It is confirmed that the dielectric constant of the porous silica low-k film after process-induced damage by plasma etching and ashing can be recovered by the TMCTS gas treatment. Process-induced damages due to CMP processes were also recovered by TMCTS as shown in Figs. 7 and 8. After CMP the leakage current and dielectric constant of the porous silica significantly increased as shown in Fig. 8 due to the increase of Si-OH bond as shown in Fig. 7. The increased Si-OH bond was eliminated by subsequent isopropyl alcohol (IPA) rinsing and TMCTS treatment, resulting in the decrease of leakage current and dielectric constant to the initial values. CH2 bonds were observed after CMP due to its slurry and additives as shown in Fig. 7 and removed out of the film by IPA rinsing. However, the IPA was not effective to recover the initial leakage current level and dielectric constant value. TMCTS treatment was necessary to achieve complete recovery of the leakage current and dielectric constant to the initial values. Mean time to failure of Cu/porous silica low-k damascene as a function of electric field is plotted in Fig. 9. The 10 year lifetime of Cu damascene interconnects with 160nm/160nm line/space could be achieved under the actual device operation condition at 0.37 MV/cm at 125°C. It has been reported that the dielectric constant of the porous low-k film increased with decreasing the space between the interconnect lines due to process induced damages at the sidewall of the damascene structure in the low-k film [9]. This problem can be solved by the TMCTS recovery treatment. Fig. 10 shows the dependences of the interline capacitance and the effective dielectric constant of the porous silica low-k film on the spacing between Cu interconnect lines. The interline capacitance increased with decreasing the space between the Cu lines, however, the effective dielectric constant did not change in the space ranging 250 nm to 80 nm. It indicates that the TMCTS treatment can recover the process damages in the porous silica low-k film and no apparent sidewall damage remains. Consequently, the development of a scalable
low-k/Cu damascene process was achieved. Figs. 11(a) and (b) show micrographs of cross sectional transmission electron microscopy (TEM) of Cu damascene with self-aligned CoWP cap barrier and DVS-BCB cap layer, respectively. The CoWP caps with thicknesses of 10-20 nm were selectively deposited only on the surface of Cu interconnectｓ. Before plating palladium activation treatment was carried out as initiation catalyst of Co alloy deposition. DVS-BCB cap layers with thicknesses of 10-30 nm were deposited on Cu damascene interconnects on a 300 mm wafer by plasma polymerization at 350°C, at 420 Pa and at 50 W. No physical damage in the porous silica interlayer dielectrics was observed at the sidewalls and the bottoms by TEM. Figs. 12(a) and (b) show Weibull plots of time to breakdown of metal-insulator-metal structures with self-aligned CoWP barrier cap and DVS-BCB barrier cap, respectively. Cu ions drifted from positively biased Cu electrode at 4.5 MV/cm at 250°C into SiO2 without CoWP barrier, while. 20 nm thick CoWP prevented Cu ion drift and improved the mean time to failure more than 10 times. As a result, the TDDB lifetime equivalent to the Al electrode under negative bias was obtained for CoWP self-aligned-capped Cu electrodes. The DVS-BCB cap with a thickness of 10 nm showed no dependence of the negative and positive biases at 2 MV/cm and 200°C on the TDDB life time, while SiOC caps under positive bias showed the degradation in the life time. The 10 nm thick DVS-BCB cap prevented Cu ion drift effectively. Conclusion An advanced ultralow-k/Cu interconnect technology for 32 nm CMOS ULSI was developed. It is confirmed that the TMCTS treatment can recover the process-induced damages in the porous silica low-k film with scaled dimensions after plasma and wet chemical processes. Furthermore, a self-aligned CoWP and low-k DVS-BCB barrier caps can prevent Cu ion drift. Consequently, a scalable ultralow-k/Cu damascene process development was achieved, demonstrating that the effective dielectric constant remained unchanged with respect to the interconnect dimensions and the reliability of the Cu/porous silica low-k damascene was significantly improved. Acknowledgement This work was supported by NEDO, Japan. References [1] R. H. Dennard, F. H. Gaensslen, H-N. Yu, V. L. Rideout, E. Bassous and A. R. LeBlanc, IEEE J. Solid-State Circuits SC-9 (1974) 256. [2] H. B. Bakoglu and J. D.Meindl, IEEE Trans. Electron Devices vol. 32, pp. 903-909, 1985. [3] Y. Oku, K. Yamada, T. Goto, Y. Seino, A. Ishikawa, T. Ogata, K. Koumura, N. Fujii, N. Hata, R. Ichikawa, T. Yoshino, C. Negoro, A. Nakano, Y. Sonoda, S. Takeda, H. Miyoshi, S. Oike, H. Tanaka, H. Matsuo, K. Kinoshita, and T. Kikkawa, Tech. Dig. IEEE International Electron Devices Meeting, pp139-142, 2003. [4] K. Yamada, Y. Oku, N. Hata, S. Takada and T. Kikkawa, Japanese Journal of Applied Phys, Vol.42, No. 4B, pp.1840-1842, 2003,. [5] K. Yamada, Y. Oku, N. Hata, Y. Seino, C. Negoro and T. Kikkawa, Journal of Electrochemical Society, 151, F248, 2004. [6] R. Yagi, S. Chikaki, M. Shimoyama, T. Yoshino, T. Ono, A. Ishikawa, N.
Silica oligomer: TEOS
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Fig. 3. (a) Dielectric constant versus porosity of self-assembled porous silica. (b) Elastic modulus versus porosity. Inset is the relationship between the porosity and the molar ratio of surfactant/Si.
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Fujii, N. Hata, T. Nakayama, K. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, K. Kinoshita, and T. Kikkawa, Tech. Dig. IEEE Symp. VLSI Technolgy. pp.146-147 , 2005. [7] X. Wang, A. Owatari, D. Takagi, A. Fukunaga, M. Tujimura, Proc. AMC, pp.809-814, 2004 [8] J. Kawahara, A. Nakano, N. Kunimi, K. Kinoshita, Y. Hayashi, A. Ishikawa, Y. Seino, T. Ogata, H. Takahashi, Y. Sonoda, T. Yoshino, T. Goto, S. Takeda, R. Ichikawa, H. Miyoshi, H. Matsuo, S. Adachi, and T. Kikkawa, Tech. Dig. IEEE International Electron Devices Meeting, pp143-146, 2003. [9] K. Maex, S. Brongersma, F. Lacopi, Y.Travaly, Z.Tokei, C. Bruynseraede and G. Beyer, Proc. The 3rd Hiroshima University COE Workshop, Hiroshima, Japan, pp.10-18, 2004.
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Fig. 11. Cross sectional TEM micrographs of Cu damascene structures. (a) Self-aligned CoWP barrier on Cu interconnect by selective electroless plating. (b) Plasma polymerized blanket BCB barrier cap. (a)
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