Current-Source Cascaded Multilevel Converters based ... - IEEE Xplore

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Current-Source Cascaded Multilevel Converters based on Single-phase Power Cells. Carlos R. Baier *, Pedro E. Melin **, Johan I. Guzman *, Marco Rivera * ...
Current-Source Cascaded Multilevel Converters based on Single-phase Power Cells Carlos R. Baier *, Pedro E. Melin **, Johan I. Guzman *, Marco Rivera *, Javier A. Muñoz *, Jaime Rothen *** Jose Espinoza ***. * Universidad de Talca / Department of Industrial Technologies, Curicó, CHILE ** Universidad del BioBio / Department of Electrical and Electronic Engineering, Concepción, CHILE *** Universidad de Concepción / Department of Electrical Engineering, Concepción, CHILE [email protected], [email protected], [email protected] Abstract— Nowadays the control of medium voltage motors has two main alternatives for its development: voltage source inverters (VSI); or current source inverters (CSI). The cascaded multilevel inverters derive from high voltage, high power quality and high reliability requirements in both development alternatives. Up to now, the cascaded multilevel converters have been implemented using voltage source power cells. However, they can also be implemented using current source units. One factor against CSIs is the large size of the inductive filters needed in the DC links, especially when single-phase inverters are considered. This paper presents a current-source cascaded multilevel converter (CS-CMC), based on single-phase power cells and their implementation alternatives, which enable a reduction in the sizes of the DC-link inductors. It is demonstrated that these sizes can be reduced using magnetic couplings between the DC links of the power cells. These magnetic couplings can eliminate second harmonic currents, as well as other even harmonics of current in the DC link of the power cells. This work asserts that the implementation of a current-source cascaded multilevel converter, based on single-phase power cells, must consider magnetic couplings between its DC links. Design results and the simulation of a development alternative of the system, aim to demonstrate the feasibility of implementing the cascaded multilevel converter. Keywords: cascaded multilevel converters; current source converters; inter-cell magnetic couplings; single-phase power cells.

I.

sources inverters [6]–[7]. However, the single-phase rectifiers and inverters based on H-bridges have the drawback of injecting even harmonics of large amplitudes on the DC link. This is the case of the power cell presented in Fig. 1(a), where the use of a single-phase half or full silicon controlled rectifier (SCR) bridge causes the presence of even harmonics from the AC mains on the DC side (see Fig.1(b) and Fig.1(d)), and where the full-bridge pulse-width-modulation (PWM) singlephase inverter also reflects a large amplitude of even-harmonic voltages from the load side on the DC side (see Fig.1(c) and Fig.1(e)). Therefore, it is necessary to filter out the DC currents to have a minimum distortion on the AC sides. The presence of large even-harmonic amplitudes, seen in Fig 1(b) and (c), involve the necessity of large inductors as filters in the DC links (also called DC chokes). The use of magnetic couplings between power cells is an alternative to remove the second harmonic currents and other even harmonics of currents in the DC link of CMCs. This alternative eliminates the even harmonics of currents, including those generated by diode based rectifiers or SCR rectifiers [8]– [9]. Nevertheless, this solution has the disadvantage of having to add more magnetic elements to the system, which is not desirable in voltage source cascaded multilevel converters (VSCMC) [8]. However, in the case of a cascaded multilevel vtrg mo

INTRODUCTION

From decade to decade, the use of electric energy has increased owing to the population explosion that has affected our planet for more than a century. The electronics and, in particular, power electronics, have allowed an increase in electric power efficiency for industrial processes that require higher voltages, enabling the control of machines and motors through mediumvoltage converters [1]–[2]. Today, when we talk about medium-voltage converters, we cannot avoid thinking about multilevel converters, because they appear as a result of increased demand and the need for high levels of controllable voltage for new industrial processes. Among the various types of multilevel converters the cascaded multilevel converters (CMC) are highlighted [2]–[5]. These converters exploit the possibility of multiple power cells working together, with the aim of achieving better power quality, increased efficiency and greater reliability, without the use of medium-voltage semiconductors [4]. CMCs are based on H-bridges connected in series in order to increase the load voltage with regard to each inverter’s output voltage. These circuits can be implemented using voltage sources or current

978-1-4799-0224-8/13/$31.00 ©2013 IEEE

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iDC

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vr

i DC

vo

Ldc 2

vi Ldc 2

Cf

vo io

[V]

t[sec]

t[sec]

[V]

f

fs

f

fs

Fig. 1. Power cell of a CS-CMC, based on single-phase cells; (a) basic power cell and control scheme; (b) output voltage of rectifier; (c) input voltage to the inverter; (d) spectra of (b); (e) spectra of (c).

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isu

isw



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vru(0)

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vrv(20)

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v91 v12

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idcu viu

iou

vou

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vrw( 20) v89 v91

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Fig. 2. CS-CMC based on single-phase power cells; (a) conventional arrangement of three series inverter; (b) arrangement of power cells coupled magnetically in threes; (c) proposed arrangement with all power cells magnetically coupled.

converter, based on current source power cells (CS-CMC), the use of magnetic couplings is a natural alternative, because the reactors to filter out harmonics, in current source converters, have been used from the beginning. This paper presents a new CS-CMC, based on single-phase power cells (as it seen in Fig.1(a)), where each of these power cells is connected to one other (as seen in Fig.2(a)). To implement this converter, three alternatives are considered; alternative (i), where each cell is a single entity, as shown in Fig.1(a); alternative (ii), where power cells are magnetically coupled in threes, as shown in Fig. 2(b); and alternative (iii), where all DC links of all power cells are magnetically coupled, as Fig.2(c) implies. This paper shows that owing to the resulting size of the DC chokes, alternatives (ii) and (iii) are viable for their implementation, whereas alternative (i) is only theoretical, since for an application of medium voltage very large sizes of DC chokes would be necessary. II.

A NEW CURRENT SOURCE CASCADED MULTILEVEL CONVERTER

A. A Brief Description of the Proposed Converter The CS-CMC presented in this paper (Fig. 2(a)), corresponds to a set of current source power cells with single-phase inputs and outputs (1-input/1-output), where each input is supplied from a single-phase secondary of a multi-pulse transformer, and each output is connected in series to another output to form a phase of the load. Compared with CS-CMC based on 3-input/1-output power cells reported in [6],[7] and [9], the proposed CS-CMC

based on 1-input/1-output power cells has the advantage of requiring 20% fewer semiconductors than its predecessors, and a multipulse transformer that uses nc single-phase secondaries, where nc is the number of power cells of the converter. A power cell of the converter is composed of a single-phase SCR rectifier, which can be full or half-controlled (4 SCR or 2 SCR and 2 diodes, respectively), as shown in Fig.1(a). If the SCR rectifier is fully controlled it can control the DC link current, and also regenerate energy to the AC mains, whereas if it is semi-controlled, it only has the ability to control the current in the DC link. In the same cell there is the PWM inverter that can be based on insulated gate bipolar transistor (IGBT) in series with a diode or integrated gate-commutated thyristor (IGCT) switches, which receive the DC current from the rectifier, and feed the load with a PWM AC current through a capacitive filter Cf in order to reduce the high di/dt in the load. Along with the inverter, this filter behaves as a controlled voltage source, which allows to connect in series to other inverters. For each cell of the converter, a PI (proportional-integral) regulator is used to control the DC current, by means of the firing angle of the SCR rectifier. The reference of the DC current is provided by the output voltage control system, as shown Fig.1(a). The inverter operates with a fixed modulation index. Also a phase-shifted carrier-based PWM technique is proposed, according to [9]. A DC link inductor is connected between the SCR rectifier and the PWM inverter of the cell. This DC choke is used for filtering out the harmonics in order to achieve a low ripple in

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the DC current. For sizing the DC choke, the following aspects in its design should be considered. B. Design of a DC Choke in a Current Source Converter. From previous work [9], it is known that the design of the DC choke Ldc is done as follows:

Ldc 

Vh , 2 f h I dh

(1)

h where V is a harmonic voltage amplitude at the frequency

f h (at harmonic order h), which causes a dominant harmonic h amplitude of current (and desired) I d in the DC choke Ldc . This dominant harmonic amplitude can be expressed as:

Idh  IDC I ph.u ,

(2) h p .u

is the where I DC is the DC current in the DC link, and I desired amplitude of the dominant harmonic current in p.u. Owing to the large second harmonic in the DC side of Hbridges, to achieve a low current ripple, large DC chokes are needed as a filter. One way of reducing the size of each DC choke in the 1-input/1-output power cells is through the use of magnetic couplings between the DC links, as shown Fig.2(b).

DC side of each rectifier that also depends on the firing angle, and s is the angular frequency of the AC mains. Switching functions for the three magnetic coupled PWM inverters in Fig.2(b) may also be written as:    M k sin   2k  1 ωo t     k 1     2     uvw SF    M k sin   2k  1  ωo t  (4)   . 3     k 1     M sin   2k  1  ω t  2    k   o    3     k 1  where Mk is a coefficient of the Fourier series that corresponds to the amplitude of the harmonic order (2k-1) of the switching function, and ω o is the frequency at the load. The output voltages are filtered out by a capacitor in each inverter. If these are considered sinusoidal, they can be written as:  vou  T 2 2   v  , (5)    v V t t t sin(ω ) sin(ω ) sin(ω ) o o o o o    3 3    vow    where Vo is the amplitude of the output voltages of each inverter. Since the input voltage to each inverter is a product of its switching function and its output voltage, from (4) and (5) it is found that these input voltages can be written as:     cos  (2k  2)ωot   cos  2kωot     viu     2   2     v   Vo M k    vi    2  cos  (2k  2)  ωot  3    cos  2k  ωot  3    (6)       viw  k 1          2 2      cos (2k  2) ω t    cos 2 ω k t o o          3  3        

C. Inter-cell Magnetic Couplings in Threes. If magnetic couplings are put between three power cells that are fed from 120° phase-shifted voltages, and which feed different phases of the load (also shifted 120°), as shown in Fig.2 (b), a cancellation of positive and negative sequence harmonics of current in the DC links is caused, whereas zero sequence harmonics cannot be cancelled, and must be mitigated with the DC choke [9]. Cancellation of harmonics in the DC links of Fig. 2(b) can be explained by considering the Fourier series of the output voltages of the three rectifiers as:    DC h2k  Vr ( )   Vr ( ) sin(2k (ω s t ))  k 1   vru(0)       v   DC h2k  vr (0)   Vr ( )   Vr ( ) sin(2k (ω s t  3 ))  , (3) k 1   vrw(0)         DC h2k Vr ( )   Vr ( ) sin(2k (ω s t  ))  3  k 1  u

v

w

where vr (0) , vr (0) and vr (0) are the output voltages of each SCR rectifier, which are supplied from 120° phase-shifted voltages, and where  is the firing angle of rectifiers. The voltage V rDC ( ) is a DC value that depends on the firing

where viu , viv y viw are the input voltages of each inverter of Fig. 2(b). Looking at equations (3) and (6), it is possible to identify the existence of even-harmonic voltages (2dn, 4th, 6th, etc.), depending on AC mains and load frequencies. Since voltage components of the DC links in Fig.2(b) are already known, if a Kirchhoff's voltage law (KVL) is performed around the three DC-links, it can be written as: vru(0)  v31  viu  v12  0  v v (7) vr (0)  v12  vi  v23  0 ,  w w vr (0)  v23  vi  v31  0 where v12 , v23 and v 31 are the common voltages present in each terminal of the magnetic couplings (primary and secondary). From (7) and the common terms, one can find that each DC loop can be represented as:

angle, V rh 2 k ( ) is the even harmonic voltage amplitude on the

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1 u  vr (0)  vrv(0)  vrw(0)  viu  viv  viw   0 . 3

(8)

If each term is replaced with its Fourier representation, found in (3) and (6), then eq. (8) can be written as: 

VrDC ( )   Vrh6 k ( )sin(6kωst )   k 1

 vru( 20)  v91  viu  v12  0  v v  vr ( 20)  v12  vi  v23  0    v v  vr (0)  v45  vi  v56  0 ,    v vr ( 20)  v78  viw  v89  0  w w  vr ( 20)  v89  vi  v91  0

Vo M1  h6 k   Vi cos(6kωot )   0 2 k 1

(9) where Vo M 6k , (10) 2 where Vrh6k is the voltage amplitude of the 6kth harmonic frequency, with respect to the AC mains frequency, and where Vi h6k is the voltage amplitude of the 6kth harmonic frequency, with respect to the load frequency. This implies that the design of the DC choke at each power cell of Fig.2(b) must be done considering the sixth harmonic current (caused by Vrh6 or Vi h6 ) on the DC link. Vi h6k 

where v12 , v23 ,.., v91 , are the common voltages shared by the magnetic couplings in the DC links, as shown in Fig.2(c). From the common voltages, (13) can be reduced to a single equation, which is valid for all nine DC links. This equation can be written as: 1   vruvw( 20)   vruvw(0)   vruvw( 20)   (viu  viv  viw )  0 , (14) 9

D. Inter-cell Magnetic Coupling between all. If all DC links are coupled, as is observed in Fig.2(c), a greater amount of harmonics is removed from the DC link currents. In this case, some zero sequence harmonics, in addition to positive and negative sequence harmonics, are blocked. To describe this mathematically, first, as in eq. (3), the rectifier output voltages fed from the phase-shifted secondaries of the transformer are represented as:     DC h 2k  Vr ( )   Vr ( ) sin(2k (ω s t  9 ))  k 1   vru(20)    5   v   DC h2k  vr (20)   Vr ( )   Vr ( ) sin(2k (ω s t  9 ))  , (11) k 1   vrw(20)       7  DC h2k ))  Vr ( )   Vr ( ) sin(2k (ωs t  9  k 1 

and     DC V ( ) Vrh 2 k ( ) sin(2k (ω s t  ))    r   9  k 1  vru( 20)     7   v  DC h2k  vr ( 20)   Vr ( )   Vr ( ) sin(2k (ω s t  9 ))  , (12) k 1   vrw( 20)        5  DC h 2k Vr ( )   Vr ( ) sin(2k (ω s t  ))  9  k 1 

u

v

w

u

v

(13)

where,

uvw r (20)

and

v

uvw r (20)

v

u r (0)

v

v r (0)

v

w r (0)

(15)

,

(16)

 vru(20)  vrv(20)  vrw(20) .

(17)

Substituting the results of eqs. (3), (6), (11) and (12) in eq. (14), it is found that each DC loop actually has the following voltages: 

VrDC ( )   Vrh18k ( )sin(18kωst )   k 1

Vo M1  h 6 k   Vi cos(6kωot )   0 2 k 1

(18) where Vrh18k () is a voltage amplitude of the 18kth harmonic frequency, with respect to the AC mains frequency. Thus the harmonic currents in the DC link are excited mainly by frequencies that are 6k multiples of AC mains frequency, and 18k multiples of the load frequency. If these harmonic amplitude voltages are known, it is possible to determine which of these voltages can be used in design (1) below. III.

w

If a KVL is performed around the nine power cells of the Fig.2(c), it is possible to write:

 vru(20)  vrv(20)  vrw(20) ,

uvw r (0)

where vr (20) , vr (20) , vr (20) and vr ( 20) , vr ( 20) , vr ( 20) are the output voltages of the rectifiers fed from the phase-shifted secondaries (+20° and -20°) of the multi-pulse transformer.

v v

DETERMINING THE MAIN HARMONIC SOURCE IN THE DC-LINK

The design of Ldc in a power cell, where there are two low h h h order harmonic voltages, Vr and Vi , at frequencies fr and h fi , respectively, must comply with,

Ldc  h

h

Vrh Vi h  2 f rh I rh 2 fi h Iih

(19)

where Ir and Ii are the amplitudes of the harmonic currents h h caused by Vr and Vi , respectively. From (19), one can find that the ratio rrih between the two harmonic currents is a function of the voltages and frequencies involved; i.e.

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rrih 

Irh Vrh fi h  Iih Vi h frh

(20)

This ratio rrih is used to determine between two harmonic voltage sources, which is the voltage source of the dominant harmonic current in the DC link, because if,

rrih  1, h r

the voltage amplitude V

at frequency f

(21) h r

in the rectifier h

output excites the dominant harmonic current Ir in the DClink, whereas if,

0  rrih 1, the voltage amplitude Vi

h

at frequency fi

(22) h

in the inverter h

input excites the dominant harmonic current Ii in the DClink. This ratio allows us to determine easily which harmonic must be considered in design (1), especially when the input and output frequencies of the converter are close. Bearing this in mind, for the converter and its alternatives (i), (ii) and (iii), the inductor design is summarized in Table 1.

TABLE I DIFFERENT DESIGN CONDITIONS FOR LDC IN THE CONVERTER Type (i) Without M.C. (ii) M.C in threes (iii) All M.C.

rrih

Ldc if ( rrih  1 )

Ldc if ( 0  rrih  1 )

Vrh 2 fo Vi h 2 f s

Vrh 2 h2 4 f s I DC I p.u.

Vi h 2 h2 4 fo I DC I p.u.

Vrh6 fo Vi h6 f s

Vrh6 h6 12 f s I DC I p.u.

Vi h6 h6 12 f o I DC I p.u.

1 Vrh18 fi h 3 Vi h6 fs

Vrh18 h18 36 fs I DC Ip.u.

Vi h6 h6 12 f o I DC I p.u.

IV.

with Table I, and as a result, Table II is obtained, where it is possible to see how the size of the DC chokes changes for each of these three implementation alternatives. Alternative (i) requires a huge inductance of 2.3H, which suggests that the development of this design alternative is not viable, while alternative (ii) can perform the same assignment with an inductance of 158mH on each DC link; a size that is technically possible, but is still high. However, alternative (iii) only needs 16.3mH on each DC link, which is 141 times lower than that required in alternative (i), and almost 10 times lower than that in alternative (ii). As seen in Table II, for 25% of full load, a low harmonic distortion in the output voltage (THD < 2.2%) is achieved for alternatives (ii) and (iii), which is highly desirable (see also Fig.3(j) and Fig4(o)). Meanwhile, it is possible to calculate 6.6% of harmonic distortion in the output voltage (Fig.3(e)) of alternative (i). To improve this, it would be necessary to have a dominant harmonic in the DC link near to 1[%] (not 3[%] as proposed and shown), which would increase the size of the inductor. A simulation in steady state for the three alternatives can be seen in Fig.3, where the converter operates with 25% of the full load (40kW), and where input and output frequencies are different (50Hz/30Hz). It is possible to see it on the input currents in a primary line of the transformer of alternatives (i),(ii) and (iii) (Fig.3(a), Fig.3(f) and Fig.3(k) respectively), the input current to a power cell in the three alternatives (Fig.3(b), Fig.3(g) and Fig.3(l)), the DC-link current in a power cell in the three cases (Fig.3(c), Fig.3(h) and Fig.3(m)), and their spectrums using a logarithmic scale (Fig.3(d), Fig.3(i) and Fig.3(n)). The resulting output voltage in a phase, for the three alternatives, is shown in Fig.3(e), Fig.3(j) and Fig.3(o), respectively, where it can be seen how the phaseshifted carrier-based technique ensures a very low distortion of the output voltage. Finally, increasing the power of the load improves the indices at the converter, as seen in Table II. V.

RESULTS AND SIMULATIONS

The three implementation alternatives for the DC link are: (i) without couplings; (ii) coupling in threes power cells; and (iii) coupling all power cells. For each alternative, a different design of DC choke is obtained, for a same condition of load. As an example, a CS-CMC with three power cells by phase has been proposed, as shown the Fig.2 (a), to feed a medium voltage motor of 154kW as a maximum. The design of the DC choke in the power cells of each alternative must be such that for a 25% of full load (40kW - a firing angle α ≈ 90 ° approx.), the amplitude of the dominant harmonic current will not exceed 3% of the DC current component on each DC link. The design for each of the alternatives is performed in accordance

CONCLUSIONS

It is possible to consider the development of a CS-CMC (seen in Fig.2(a)), based on single-phase power cells (as seen in Fig.1(a)). However, owing to the large harmonic components in the DC links of each power cell, it is necessary to add magnetic coupling to the DC link of the power cells (as seen in Fig.2(b) and (Fig.2(c)). Regarding the three development design alternatives for the DC link, a smaller DC choke is achieved when all the power cells are coupled. This allows the elimination of a positive and negative sequence of harmonic currents, and some zero sequence harmonic currents in the DC links. The resulting sizes of the DC chokes in a CS-CMC proposed without magnetic couplings are not considered to be viable. This paper shows that the use of magnetic coupling between the DC links, allows the development of a current source cascaded multilevel converter, based on single-phase power cells with SCR rectifiers.

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[m sec]

[m sec]

Fig. 3. Key waveforms for the different alternatives to implement the DC link in the CS-CMC, based on single-phase power cells; (a) input current in a primary line of the transformer of alternative (i); (b) input current to a power cell of alternative (i); (c) DC-link current in a power cell of alternative (i); (d) spectra of (c); (e) output voltage in phase u; (f) input current in a primary line of the transformer of alternative (ii); (g) input current to a power cell of alternative (ii); (h) DC-link current in a power cell of alternative (ii); (i) spectra of (h); (j) output voltage in phase u; (k) input current in a primary line of the transformer of alternative (iii); (l) input current to a power cell of alternative (iii); (m) DC-link current in a power cell of the alternative (iii); (n) spectra of (m); (o) output voltage in phase u. [5] S. Kouro; M. Malinowski; K. Gopakumar; J. Pou; L.G. Franquelo; Bin ACKNOWLEDGMENTS Wu; J. Rodriguez; M.A. Pérez; J.I. Leon , "Recent Advances and Industrial Applications of Multilevel Converters," IEEE Transactions on The authors would like to thank FONDECYT Initiation Industrial Electronics, vol.57, no.8, pp.2553-2580, Aug. 2010. into Research 2011 11110292 Project for its financial support.

REFERENCES [1]

B. Bose , "Global Warming: Energy, Environmental Pollution, and the Impact of Power Electronics," IEEE Industrial Electronics Magazine, vol.4, no.1, pp.6-17, Mar. 2010.

[2]

J. Rodriguez; S. Bernet; Bin Wu; J. Pontt; S. Kouro , "Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives" IEEE Transactions on Industrial Electronics, vol.54, no.6, pp.2930-2944, Dec. 2007.

[3]

Bin Wu; J. Pontt; J. Rodriguez; S. Bernet; S. Kouro , "Current-SourceConverter and Cycloconverter Topologies for Industrial MediumVoltage Drives" IEEE Transactions on Industrial Electronics, vol.55, no.7, pp.2786-2796, Jul. 2008.

[4]

M. Malinowski; K. Gopakumar; J. Rodriguez ; M.A. Pérez , "A Survey on Cascaded Multilevel Inverters," IEEE Transactions on Industrial Electronics, vol.57, no.7, pp.2197-2206, July 2010.

[6]

P.E. Melin; J.R. Espinoza; N.R. Zargari ; L.A. Moran; J.I. Guzman; , "A novel multi-level converter based on current source power cell," IEEE Power Electronics Specialists Conference, 2008. PESC 2008., pp.20842089, 15-19 Jun. 2008.

[7]

P.E. Melin; J.R. Espinoza; C.R. Baier; J.A. Rohten; R.O. Ramirez; L.A. Moran , "Improved control scheme towards reduced DC link inductors in a Multi-Cell Topology based on Current Source Converters" IECON 2012 - 38th Annual Conference of the IEEE Industrial Electronics Society, pp.488-493, 25-28 Oct. 2012.

[8]

C.R. Baier; J.A. Muñoz; J.I. Guzman; J.R. Espinoza; P.E. Melin , "Reducing harmonics and DC-Link capacitors in cascaded multilevel converters using inter-cell magnetic couplings," IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society, pp.49924997, 25-28 Oct. 2012.

[9]

C.R. Baier; J.R. Espinoza; P.E. Melin; E.Espinoza; J. Munoz , "A novel multi-level CSI based topology with inter-cell magnetic couplings for minimum DC storage components,", 2010 IEEE International Symposium on Industrial Electronics (ISIE 2010), 4-7 Jul. 2010.

TABLE II PARAMETERS AND SIMULATED RESULTS OF DESIGN FOR THE MULTILEVEL CONVERTER (40KW TO 154KW), 5000V LOAD

I s , RMS

THDis25%

THDis100%

THDvo25%

THDvo100%

Result

2340[mH]

1[p.u]

9.5[%]

7.6[%]

10.9[%]

9[%]

Non-viable

158[mH]

1.01[p.u]

9.7[%]

6.6[%]

1.8[%]

2[%]

viable

16.3[mH]

1.01[p.u]

2.2[%]

1.5%

viable

Alternative of Design

Ldc

(i) without M.C. (ii) 3-M.C. (iii) All. M.C.

11.3[%] 6.5[%] Cf =10uF; fs=50Hz; fo=30Hz; fsw=550Hz.

6212

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