Current status and future trends of SiGe BiCMOS technology - Electron ...

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in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001

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Current Status and Future Trends of SiGe BiCMOS Technology David L. Harame, Senior Member, IEEE, David C. Ahlgren, Douglas D. Coolbaugh, James S. Dunn, Gregory G. Freeman, John D. Gillis, Member, IEEE, Robert A. Groves, Member, IEEE, Gregory N. Hendersen, Robb A. Johnson, Member, IEEE, Alvin J. Joseph, Member, IEEE, Seshardi Subbanna, Alan M. Victor, Member, IEEE, Kimball M. Watson, Charles S. Webster, and Peter J. Zampardi

Abstract—The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier migration to advanced CMOS technology generations. Lateral and vertical scaling are used to achieve smaller and faster SiGe HBT devices with greatly increased current densities. Improving both the T and MAX will be a significant challenge as the collector and base dopant concentrations are increased. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. Capacitors and Inductors are two very important passives that must improve with each generation. The trend toward increasing capacitance in polysilicon– insulator–silicon (MOSCAP), polysilicon–insulator–polysilicon (Poly–Poly), and metal–insulator–metal (MIM) capacitors is discussed. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers is counter to the requirements of high Q inductors, potentially requiring a custom last metallization layer. Index Terms—BiCMOS, HBT, SiGe.

I. INTRODUCTION

T

HE SILICON germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of product requirements. SiGe products are now appearing in virtually all analog and high-frequency market segments. SiGe is used in wireless cellular CDMA and GSM standards at 900 MHz and 2.4 GHz, both in handsets and base stations [1]–[3]. Wireless local area network (LAN) chipsets at 2.4 GHz have been announced where the use of SiGe reduced the IC chip count and power consumption by 50% [4]. SiGe is used in high-speed/high-capacity network applications including a 10 Gbps synchronous optical network (SONET) Manuscript received August 30, 1999; revised February 22, 2001. The review of this paper was arranged by Editors P. Asbeck and T. Nakamura. D. L. Harame, D. D. Coolbaugh, J. S. Dunn, A. J. Joseph, K. M. Watson, and C. S. Webster are with IBM, Essex Junction, VT 05452 USA (e-mail: [email protected]). D. C. Ahlgren, G. G. Freeman, R. A. Groves, G. N. Henderson, and S. Subbanna are with IBM, East Fishkill, NY 12533-6526 USA. J. D. Gillis is with IBM, Tewksbury, MA 01876-0353 USA. R. A. Johnson is with Inphi, Westlake Village, CA 91361 USA. A. M. Victor is with IBM, Research Triangle Park, NC 27709 USA. P. J. Zampardi was with IBM, Essex Junction, VT 05452 USA. He is now with Conexant Systems, Newbury Park, CA 91320 USA. Publisher Item Identifier S 0018-9383(01)09070-0.

transmit-and-receive module [5], [6], trans-impedance amplifiers, and 1–2.5 Gb/s Ethernet applications. Other applications include products with lower levels of integration such as LNAs, VCOs, mixers, power amplifiers (PA), and GPS receivers. In addition to applications in the communications market, SiGe also provides product leverage in high-speed test and storage applications for partial response maximum likelihood (PRML) read channels and magneto-resistive (MR) preamplifiers. SiGe HBTs are used in such a wide range of applications because they are superior or equal to conventional homojunction silicon (Si) bipolar devices in every important performance metric. In fact, SiGe with bandgap engineering enables process designers to satisfy product requirements for simultaneous high ), cutoff frequency ( ), maximum oscillation frequency ( ). At the Early voltage ( ), and breakdown voltage ( GHz), Si homojunction highest performance levels (i.e., devices are not very suitable for practical circuit applications. This is supported by the number of corporations with access to advanced silicon bipolar and BiCMOS technologies which have announced their intentions to pursue SiGe for high frequency and low power applications [7]–[10]. Surprisingly, at more modest performance levels (30–40 GHz ) SiGe HBTs can be more cost competitive than Si bipolar devices, as the graded epitaxial base layer allows the NPN device engineer to obtain excellent performance with relatively simple transistor structures [11]. A Si homojunction bipolar transistor requires a much more aggressive and complex (costly) device structure than a SiGe HBT in GHz; order to achieve AC characteristics in the range of but, even with a more complex structure, severely degraded Early and breakdown voltages occur. As today’s most cost-sensitive product applications push for improved performance, it becomes apparent that SiGe HBTs are suitable for this market as well as very-high-frequency applications. Compared to GaAs technologies, SiGe HBTs have several favorable attributes. For example, the minimum noise figures ) are close to those of a 0.5 m MESFET technology ( and better than those of a GaAs HBT technology [12]. The low noise corner in SiGe HBTs make them an excellent technology choice for VCOs and power amplifiers. In addition to allowing very complex custom designs, high speed and high breakdown voltage SiGe HBTs can be merged with high-density CMOS using a mixed-signal ASIC methodology or other CMOS macros such as microcontrollers and embedded SRAM. Using this methodology, SiGe BiCMOS has already demonstrated integration levels several orders of magnitude more than

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GaAs [13]. The ability to combine high-density circuits with high-quality passive components such as high Q inductors [14], MIM capacitors, resistors, and high-value MOS capacitors gives the product designer unprecedented ability to achieve higher levels of integration where there is performance and/or cost leverage. This removes the technical limitations to system partitioning and gives the designer new degrees of freedom for optimizing the performance of the product. In this work we explore the current status and key trends of SiGe BiCMOS to give insight into the future possibilities of the technology. The paper focuses on IBM technology with which the authors are most familiar; but, to give more insight, references are made to other works where appropriate. It also reports advances in process integration of the SiGe epitaxial base, which enables advanced CMOS generations to be leveraged more rapidly; discusses HBT device characteristics across several lithographic generations; describes lateral scaling of the SiGe HBT with a focus on defining the parasitics that do not easily scale; presents a derivative technology example for PA applications; presents an overview of reliability of the SiGe HBT; and discusses important directions in obtaining high Q passives. II. SiGe PROCESS INTEGRATION METHODOLOGY As the application base for SiGe expands into different markets, e.g., wireless, network, storage, etc., the requirements of the technology also expand. Once a technology is qualified in production it is very common to have derivatives, or variations based on the initial technology offering. For example, an application to drive inductive loads may require high-breakdown NPN and high-breakdown FET transistors. In addition, different markets have different cost sensitivities—while one application may emphasize a full suite of support devices, another market may require only a low-complexity nonself-aligned junction isolated HBT added to the base CMOS [11]. The technology integration scheme must be sufficiently modular and robust to support the rapid development of such “derivative” technologies and other low-complexity alternatives. For library and design-system compatibility, it is important that the SiGe BiCMOS technology have as many common steps with the base CMOS process as possible. CMOS logic technology continues to advance by shrinking the device each generation and fully scaling the technology. The thermal cycle variation from generation to generation presents severe problems for developing a SiGe BiCMOS process integration approach that covers these multiple generations of CMOS. Previous IBM SiGe BiCMOS processes used an integration approach that shared layers and thermal cycles to reduce the structural complexity of the process. In this approach, the HBT was fabricated during the CMOS process; therefore, it is referred to as base–during–gate (BDGate). This was also referred to as base gate because the extrinsic base of the bipolar was the same as the gate stack of the CMOS. Sharing layers and thermal cycles worked well in the 0.5 m generation. Sharing the thermal cycle became problematic as SiGe BiCMOS was developed across multiple generations of CMOS which also had significantly different thermal cycles. In a new process approach, the CMOS is formed before the bipolar elements are formed, without sharing silicon layers or thermal cycles; hence,

Fig. 1. Schematic process flow diagram for the 0.5 m Base–During–Gate (BDGate) production technology. The CMOS backbone represents the base CMOS process. Insertion points are shown for analog and bipolar process modules.

it is referred to as the base–after–gate (BAGate) approach. A flow diagram for IBM’s 0.5 m BDGate process is shown in Fig. 1. The diagram depicts a main process flow for the base CMOS process (known as the CMOS backbone) with bipolar and analog element steps that feed into the CMOS backbone. In the 0.5- m generation the base CMOS was used only for digital applications and lacked analog modules. Therefore additional processing modules for resistors and capacitors were added for analog BiCMOS circuits (as shown in Fig. 1). The bipolar blocks formed the n subcollector, deep-trench isolation, the reach-through to the n subcollector, and the self-aligned npn superstructure (ETX). The processing steps to fabricate the ETX structure [15] included patterning a bipolar window where the epi-base will be grown, growing the SiGe epitaxial base, depositing a series of dielectrics, etching the emitter pedestal, self-aligning the extrinsic base implants, converting a surface polysilicon layer to oxide, etching the emitter opening, and finally depositing and patterning the polysilicon emitter [16], [17]. An important point is that the epitaxial base is exposed to all subsequent CMOS thermal steps, such as polysilicon gate oxidation (REOX), CMOS extension anneals, sidewall formation, and CMOS source/drain/gate (S/D/G) anneals. Typical gate REOX processes require high-temperature dry-oxidation conditions to reduce the bird’s beak that is formed at the bottom side corner under the gate; but, in the 0.5 m generation, the temperature can be reduced and the bird’s beak extended without impacting the CMOS. Similarly, nFET arsenic S/D implant anneals significantly widen the intrinsic base and must be avoided. In the 0.5 m BDGate process a low thermal-cycle REOX with phosphorous nFET S/D anneal [18] was used. Emitter drive-in was shared with the final rapid thermal anneal for the S/D/G. Some widening of the base still occurs from the REOX but the graded SiGe profile more than compensates for increased base transit time. In the 0.25 m generation, the CMOS technology had high thermal cycles for the REOX (900 C furnace oxidation) and arsenic-doped nFET extension anneals, which prohibited the BDGate process from being used. Therefore, the BAGate integration approach for the 0.25 m generation was developed to decouple the CMOS thermal cycle from the bipolar (Fig. 2).

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TABLE I COMPARISON BETWEEN 0.25 m SiGe BiCMOS AND THE BASE CMOS TECHNOLOGY FET PARAMETRICS

Fig. 2. Schematic process flow diagram for the 0.25 m and 0.18 m Base– After–Gate (BAGate) production technology. The CMOS backbone represents the base CMOS process. Insertion points are shown for analog and bipolar process modules. Note the reduced number of analog and bipolar blocks compared to the BDGate process.

Due to the structural as well as thermal cycle, decoupling of CMOS and bipolar sections, there are fewer processing blocks, but each contains more steps. Also, the more advanced CMOS logic technology is used for analog as well as digital applications and therefore provides analog elements, such as resistors and capacitors, removing the need for additional analog-element steps. BAGate technology has several advantages over BDGate technology. The CMOS is largely fabricated in one complete block before the SiGe base is deposited; therefore, the base CMOS technology steps can be completely copied without modification. Also, derivative technologies composed of highvoltage FETs in a similar or identical design-rule set can be easily developed from an existing production BiCMOS technology because the FET steps do not need to be modified. The bipolar is fabricated in a complete block after the CMOS without sharing any CMOS thermal cycles except for a final emitter drive-in RTA, making the BAGate an ideal process for the HBT. The concern with the BAGate process is that it is structurally a more complex process because the bipolar layers that are deposited over the CMOS topography must be completely removed. Some key metrics in evaluating the BAGate technology integration flow were to verify that 1) the CMOS parametrics were closely matched to the base CMOS; 2) the CMOS yields were closely matched to the base CMOS; and 3), the bipolar parametrics and yields were equivalent to the 0.5- m-generation technology. The CMOS parametrics for the 0.25- m BAGate SiGe BiCMOS technology are compared to the base CMOS technology in Table I. With the exception of the nFET S/D area capacitance, the bipolar processing did not significantly perturb the CMOS parametrics. The nFET S/D area capacitance was

Fig. 3. (a) CMOS defect monitor yield trend by lot for poly–poly, polysubstrate, and poly-n-well shorts and (b) 154K LSM Static RAM yield data by wafers.

changed because phosphorous diffuses at the low-temperature steps of the bipolar transistor ( 720 C furnace). Because the nFET area capacitance decreased, the change was not considered detrimental to the technology. The CMOS yield was evaluated by measuring defect test structures and a 154 K Logic SRAM monitor (LSM). If the bipolar films or residuals from the bipolar films were not completely removed, then many of the defect tests on specialized test structures (e.g., poly–poly shorts, and gate leakage to adjacent structures) would be adversely affected. In all cases, the SiGe BiCMOS average test values of the defect structures were well within the CMOS specifications. This is demonstrated in Fig. 3(a), which shows the percentage yield to the CMOS specification for over 30 lots of three key defects test structures. The LSM yield is a very sensitive indicator of how closely the process duplicates the base CMOS because it is a large fully functional product-like circuit. The LSM yield was also very close to the base CMOS yield [Fig. 3(b)]. The

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LSM yields were initially low relative to the CMOS technology and it is informative to understand the problem and its solution. Because of the extra topography from the epi-base transistor, the contact dielectric was thickened increasing the aspect ratio of the contact holes. Modern CMOS processes push the contacts to the limit of the technology to achieve the highest density. The increased aspect ratio of the contacts was enough to perturb the process and lead to contact failures. The process was adjusted to compensate for the increased aspect ratio and good yields equivalent to the base CMOS were obtained. We can conclude that the BAGate process has no significant impact on the parametrics or yield of the base CMOS process. Similarly, the CMOS topography has no impact on the bipolar transistor parametrics and yield. Yield is determined from the product of (emitter-base leakage yield) (emitter-col(base-collector leakage yield) lector pipe leakage yield) 2.3 m (emitter area) on 4000 parallel connected 0.42 transistors. The yields of the 0.25- m BAGate and 0.5- m BDGate were equivalent, yielding at more than 85% indicating no impact from CMOS topography. The primary failure mechanism in both technologies was established by building test structures with and without some of the technology components; for example, comparing yield on transistor arrays with and without deep trench. This technique has consistently established shallow trench isolation as the largest source of yield loss. The key to improving yield has been the reduction of defects created by shallow trench stress. The real test for the success of a SiGe BiCMOS technology was being able to design and manufacture highly integrated products with good yield. An example of an integrated circuit in volume production at IBM’s Essex Junction facility is shown in Fig. 4. This read channel chip translates analog signals from a disk drive read head into digital words. The analog data is interpreted using a PRML signal-processing algorithm. The chip was clocked at a rate of 75 MB/sec, which is the fastest PRML chip speed published to date. The trend in SiGe BiCMOS integration is to develop a modular BiCMOS process that includes direct copy of the CMOS process modules. The BAGate process is superior to the BDGate process in being able to leverage the CMOS advancements regardless of the thermal cycles that occur in subsequent CMOS generations. The modularity of BAGate process supports rapidly developing derivatives and low-cost alternative BiCMOS technologies. The base CMOS processes are incorporating more analog elements (capacitors, inductors, and resistors) because of the expanding use of CMOS for analog products. This trend is favorable for BiCMOS technology because fewer processing steps need to be added to the base CMOS to have an analog SiGe BiCMOS process. III. THE SiGe HBT As with the base CMOS technologies, each HBT generation has moved toward smaller dimensions for higher speed and reduced power consumption. In this section we will examine the trends in SiGe HBT technology. The section compares SiGe HBT characteristics across three generations of technology, disand , and focuses on cusses important trends in

Fig. 4. Photomicrograph of an advanced SiGe BiCMOS integrated circuit used in hard drives. The chip is partial-response-maximum-likely-hood (PRML) chip that has been clocked up to 75 MBytes/s. TABLE II HBT COMPARISON FOR 0.5 m, 0.25 m, AND 0.18 m GENERATIONS

vertical and lateral scaling of the IBM SiGe HBT as an example with generalizations for all SiGe BiCMOS technology. A. Comparison of HBT Characteristics Across Generations 2.5 m The NPN transistor characteristics of a 0.5 emitter (0.5 m generation with BDGate process flow), a 0.44 3.0 m emitter (0.25 m generation with BAGate process flow), and a 0.18 0.82 m emitter (0.18 m generation with BAGate process flow) are summarized in Table II. In the SiGe transistor has both a deep and a HBT technology, the high shallow collector implant. By dropping the shallow collector implant, an additional high breakdown device is obtained device as discussed in Section III-E along with the high because the devices have the same vertical profile in the 0.5 and 0.25 m generations, they also have almost identical current gain ( ) of 100 and peak- near 50 GHz. In the 0.18 m, we changed the vertical profile in conjunction with our lateral scaling to optimize device performance as discussed in Section III-C. The common-emitter characteristics of the 0.5 2.5 m (Fig. 5) exhibit excellent Early voltages ( V) ) making the devices and breakdown characteristics (

HARAME et al.: CURRENT STATUS AND FUTURE TRENDS OF SiGe BiCMOS TECHNOLOGY

Fig. 5. Common-emitter characteristics of a 0.5 30 A in 5 A steps.

2 2.5 m

NPN. I = 0 to

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Fig. 7. Unity current gain cutoff frequency versus collector current for various size NPN transistors at V = 1 Volt.

results demonstrate not only a trend toward higher peakfrequencies, but also a trend toward similar speed performance at lower power, making the technologies well suited for the ever-demanding wireless- and wired-communication markets. B. Trends in

Fig. 6.

Gummel characteristics of 0.5

2 2.5 m

and 0.32

2 1.04 m

NPNs.

well suited for the high-frequency circuits needed for wired and wireless communications. Laterally scaled devices with 1.04 m emitter area the same vertical profile and 0.32 were also fabricated in the 0.25 m generation technology to target lower power applications. Fig. 6 compares the Gummel 2.5 m and 0.32 1.04 m characteristics of the 0.5 NPNs. The devices have base and collector currents that are ideal over many decades. The ac performance of several 2.5 m BDGate and NPNs is shown in Fig. 7. The 0.5 3.0 m BAGate (0.25 m technology) devices have 0.44 with peak- near 50 GHz. Also note in Fig. 7 a similar that a laterally scaled 0.32 1.04 m BAGate has a reduced peak- , largely due to increased extrinsic parasitic stemming at from a higher perimeter-to-area ratio, but an increased low current due to an overall reduction in parasitic. Hence, this device is well suited for low-power applications such as circuits operating at IF or baseband frequencies. Also plotted in Fig. 7 are the AC characteristics of a 0.16 5.0 m emitter device, representative of our next generation 0.18 m technology. This device is scaled in both the lateral and vertical dimensions and, hence, has a greatly improved AC performance with peak- near 90 GHz. These results will be discussed in more detail in the sections on lateral and vertical scaling. These

and

As the trend in communications progresses toward ubiquitous connectivity, the requirement for higher operational frequencies and increased bandwidth will continue. Higher frequency operation for the HBT implies lower breakdown voltages and, therefore, lower voltage power supplies, which is an issue for the RF designer because of reduced signal-to-noise levels. Therefore, the tradeoffs need to be very well understood. The peak cutoff frequency ( ), breakdown voltage ) and Early voltage ( ), are three parameters that ( are closely linked in a bipolar transistor. There is a reciprocal and both and . Given relationship between the a transistor design point where the base and emitter profile may be increased either by are assumed constant, the ) or making increasing the collector doping concentration ( the collector shorter (e.g., by decreasing the collector epi-layer thickness); both of which delay the onset of the Kirk effect. Increasing the collector doping, decreases the Early voltage because of the increased base-width modulation; it also increases . The reduction in impact ionization, which lowers collector epilayer thickness also increases the impact ionization due to the higher field from the same voltage supported over and is a shorter distance. This tradeoff between referred to as the “Johnson Limit” [19], [20]. Bandgap engineering techniques in SiGe HBTs provide an extra degree of freedom in their device design [21]. Fundamentally, the strained SiGe layer reduces the base bandgap, increases emitter injection efficiency, reduces emitter charge storage, and reduces the base transit time. Therefore, for an identical emitter/base/collector dopant profile between Si BJT and SiGe HBT, the graded Ge profile in SiGe HBTs increases without degrading . Graded SiGe base transistors without compromising have the added advantage of higher or . The drift field from the graded Ge profile on provides an additional driving force along with the diffusion

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mechanism for carrier transport across the neutral base. The drift-current component is proportional to the product of both minority-carrier concentration and the drift field, which is much less sensitive to basewidth modulation compared to the diffusion component. The Early voltage enhancement from a graded SiGe profile is is the condescribed by Equation (1), in which duction band offset across the neutral base from the graded profile. The theoretically expected exponential dependence of the Early voltage on the band offset across the neutral base has been experimentally verified for IBM SiGe HBTs over a wide temachievable perature range [22]. For most applications, the from the current-generation SiGe HBTs are adequate. However, will the commensurate increase in Ge grading for higher s for future-generation SiGe naturally provide even higher HBTs (1) An additional advantage of SiGe HBTs is that, since the base is formed by epitaxy, the base doping can be made higher [15]. This limits the depletion length into the base at the base-collector junction, decreasing the modulation of the basewidth. Therefore, the Early voltage is not degraded by high collector doping for a graded SiGe base compared to a homojunction device. and in Si Fig. 8 shows some important trends for bipolar transistors by comparing the measured data for conventional ion-implanted base BJT, epi-base Si BJT, and graded-base SiGe HBT in relation to the “Johnson Limit.” While epi-base compared to the implanted base transistors provide higher can be further improved by due to tighter basewidth control, adding graded Ge base without process modification. One can for readily observe that this is indeed the case by comparing with SiGe HBTs having the highest values. a given Notice that the HBT data is very close to the Johnson limit curve product of 200, so it appears calculated with an to be a good predictor. Higher s are being required by circuit designers to satisfy the ever-expanding demand for bandwidth. A conservative rule of thumb [23] is that, for digital parts, the technology must be capable of supporting flip-flops that run at twice the bit rate. Synchronous data transmission on optical media provides some of the highest speed requirements. Synchronous optical network (SONET) standards define a base rate of 51.84 Mbps and a set of multiples of the base rate known as “Optical Carrier levels.” The highest current standards are OC-192 or 9.953 gigabits per second (Gbps, but work is already beginning on 40 Gbps networks. Since the best flip-flop performance possible is approxiof four times the bitrate, mately one-half , this implies an or 160 GHz for a 40 Gbps SONET application! This is of course conservative, with many 40 Gb/s circuits being demonstrated in technologies with significantly lower cut-off frequencies [24], [25]. As pointed out by Rein [24], designers must consider not and , but other technology characteristics such only and per emitter length, number of metal layers, and as transistor-current-carrying capability to achieve optimum circuit performance. SiGe technologies are an excellent choice for

Fig. 8. Unity gain cutoff frequency versus Johnson Limit.

BV

. The line is a plot of the

these applications. With graded SiGe base designs, maintaining will not be a problem; but, for reasonable current a high values will be degraded to 2.0 V as these gains, the ultrahigh cutoff frequencies are approached. C. HBT Scaling and Parasitics Using SiGe epitaxy and bandgap engineering, the bipolar transistor will continue to provide circuit designers with the performance necessary to meet today’s most stringent circuit and systems requirements. In demonstration of this trend, companies are now leveraging the learning from today’s 50 GHz SiGe devices to develop 75 to 90 GHz SiGe devices in their next generation process [26]. Continued trends in process and device design, discussed in this section, will undoubtedly push performance of the SiGe HBT to higher levels in the future. performance is princi1) HBT Vertical Scaling: Higher pally achieved through vertical scaling of dopants and dimensions in the HBT device. Such scaling involves the following: 1) transit time reduction through vertical layer dimension reduction (base and collector transit times decrease), 2) a commensurate increase of Ge grading across the (now thinner) neutral base (base transit time reduction), and 3) an increase in Kirk-effect threshold by increasing collector dopant concentrations (lower charemitter and collector charging times). These effect the acteristics, as illustrated in Fig. 7, by 1) translating the curve upfor a given current and 2) delaying the roll-off ward to higher in to higher currents allowing a higher peak to be reached. Key to vertical dimension reduction is minimization of thermal cycles in post-base deposition processing. This is particularly challenging when the device contains a self-aligned extrinsic base and is integrated with high-performance CMOS. Thus the modular integration trend described in Section II provides one key aspect to obtaining vertically scaled devices. Furthermore, general trends toward rapid thermal processing (RTP) are favorable toward achieving low overall thermal processing. An emerging trend in base-width reduction is the incorporation of carbon into the base epitaxy. At 10 cm concentrations, C incorporation has been shown to significantly reduce B diffusion [27] by lowering the Si self-interstitial con-

HARAME et al.: CURRENT STATUS AND FUTURE TRENDS OF SiGe BiCMOS TECHNOLOGY

centration within the C-rich environment. In prior-generation devices without C, the interstitials have relatively 50 GHz device in the minor effects on performance, but a 90 GHz presence of a large quantity of interstitials may encounter substantial base widening with loss of performance and possible barrier effects [28] Some point out however that the principle concern addressed by C is in the control of the perimeter B diffusion. This will be discussed shortly. Emitter dopant choice is closely linked to device thermal cycles. In SiGe HBT processes reported in the literature, one finds a mix of implanted Arsenic emitters and implanted or in-situdoped phosphorous emitters. Typically, the topography seen by the polysilicon emitter together with difficulties associated with diffusion of the dopant is the prime influence in the choice of emitter dopant. Because thermal cycles required to diffuse and activate Arsenic emitters will adversely impact base widths as thinner bases are used, in-situ-doped Phosphorous emitters will likely become prevalent in future SiGe HBT device designs targeting greater than 100 GHz . Coupled with the vertical layer width reductions is a reduction in the base-collector space-charge region width in order to minimize transit time across this region. It is unavoidable that the space-charge width reduction involves an increase in collector dopant concentrations. With the higher collector dopant concentrations comes the added benefit that the device may be operated at higher peak current densities, and thus achieve higher , due to a delayed Kirk-effect. The increase in collector doping has numerous consequences, not the least of which is the increase in collector-base capacitance within the intrinsic device and in the overlap region of the SIC out-diffusion under the extrinsic base. Reducing the overlap dimension and minimizing collector doping pay off in and lower . Higher doses also reincreased low current sult in process and defect consequences. Substantially higher interstitial and clustered defect concentrations anomalously affect diffusion of base dopants and device yields. Controlling these dopant anomalies with minimal thermal cycles becomes a principle challenge in fabrication of the next generation devices. 2) HBT Lateral Scaling: Wherein transit time performance improvements are obtained through vertical profile scaling, a separate but similarly important set of performance metrics are improved through making the device smaller. The advantages of lateral scaling are well known [29]. Smaller devices contribute lower capacitive loads to the circuit than do larger devices, resulting in reduced RC delays. The key benefit of smaller devices is that they use less current resulting in significant power savings. Furthermore, smaller emitter widths result in lower parasitic resistances (namely base resistance), resulting in a significant noise improvements for RF applications, and higher figures of merit. In addition, the tighter packing densities that follow from the device scaling reduce the circuit wiring parasitics. The complexity of the self-aligned HBT device structure presents numerous lateral scaling challenges. First to be discussed in this section is the prerequisite scaleable device integration scheme. Second, parasitic tradeoffs related to the highly two and three-dimensional structure of the HBTs three junctions are discussed.

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Fig. 9. Comparison of and f for 0.18 and 0.38 m width emitters, demonstrating lack of small emitter effects with a lithographic emitter shrink.

a) Emitter structure lateral scaling: Unlike the more common “double-polysilicon” self-aligned base integration scheme which suffers from nonuniform diffusion of dopants through high-topography emitter polysilicon at small dimensions [30], the single-crystal implanted extrinsic base selfaligned integration scheme employed by IBM [31] appears to scale well below 0.2 m dimensions. Fig. 9 compares and for two devices: one fully design-rule compliant at 0.38 2.4 m emitter dimension from IBM’s production 0.5 m SiGe technology, and another fabricated on the same chip and verified through SEM cross section at 0.15 m physical 2.4 m estimated electrical junction opening and 0.18 area. Both devices are fabricated without process modifications from the 0.42 m nominal emitter width process. The lack of significant current-gain degradation between devices demonstrates the scaleability of this device integration scheme to 0.2 m dimensions. Integration schemes which require significant structural modifications between scaled generations are prohibitive, not only from a development cost standpoint, but also because they tend to introduce elements which are not BiCMOS compatible, such as unique isolation, salicides, and contact etches. Thus a scalable, CMOS-compatible integration scheme is the prerequisite to advancing lateral scaling trends in SiGe BiCMOS. Researchers have recently focused on the sensitivity of the SiGe HBT to perimeter base widening [28]. Of concern are the interstitials resulting from the extrinsic-base implant which enhance the B diffusion at the perimeter of the device, causing performance loss and conduction-band barrier effects. In particular, it has been pointed out that C provides significant leverage in controlling this undesirable diffusion. Extrinsic to intrinsic base link-up resistance reduction and anomalous diffusion effects such as these are challenges to be faced if full scaling of the HBT extrinsic base (i.e., resistance components) is to be achieved. b) Parasitics in lateral scaling: Given the scalability of the device structure without significant detrimental effects, the

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Fig. 10.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001

IBM ETX transistor with parasitic elements noted.

Fig. 11. Comparison of parasitic C and R for 1 m emitter area devices estimated for three IBM SiGe HBT technology generations.

principal concern becomes how the parasitic capacitive and resistive components behave with shrinking feature sizes. A comparison of parasitic contributions as a function of device layout may be obtained through a simple analytic model [32] incorporating component areas and perimeters, shown in Fig. 10, together with dielectric thicknesses, dopant concentrations, or extracted unit area or perimeter capacitances. It is instructive to consider parasitic trends across IBM’s three SiGe technology generations with this analytical model. Shown in Fig. 11 are base resistance and collector-base capacitance estimations based on a minimum-size layout for a 1 m device in each technology. Note that the emitter width varies from 0.42 to 0.30 to 0.18 m across these generations. With the shrinking width the emitter will become longer to compensate for the reduced width and to maintain a 1 m emitter area. The base resistance is significantly reduced, because of the emitter-width in unit - m perimeter) reduction (reducing the intrinsic inand the increase in emitter length for each device. The creases slightly as a result of the extrinsic device’s imperfect scaling (namely, collector pedestal outdiffusion). Thus through lateral scaling alone, two key figures of merit related to base reand (proportional to sistance of an HBT device,

( ) are greatly improved between generations. Furand directly decreases CML gate ther, the reduction of and . delays, independent of 3) Combining Lateral Scaling With Vertical Scaling: Vertical and lateral scaling trends are closely related [33]. Vertical scaling should be accompanied by lateral scaling for the following reasons. proportional to the square root of and 1) With , commensurate improvements in will not accompany improvements in only the intrinsic ). delay ( ) or only the extrinsic parasitics ( 2) Higher current-density operation (e.g., 2–5 between generations), made available by increased collector doping, results in substantially more self-heating. Long narrow devices ameliorate this problem, providing more device perimeter for a given power dissipating area of the device, reducing the device thermal resistance. 3) Due to electromigration concerns, higher current densities also tax the metallization system connected to the emitter and collector of the device. Narrow emitters result in lower net current for a given length of emitter. With the emitter and collector at the ends of the device topology, emitter narrowing then reduces the current-per-unit width of metal wire feeding current perpendicular to the long direction of the emitter stripe. This permits a single level of (CMOS design-rule compatible) metallization to supply the currents required to achieve peak device performance. To be sure that the coupling of the vertical and lateral scaling does not lead to negative consequences, the device design and integration concerns must be carefully balanced. For a fixed emitter-area design, emitter-width reduction increases the perimeter of the device where the overlap of the higher-doped collector and the extrinsic-base doping increases the extrinsic . So, to improve for the constant-area device by increasing the collector implant, a balance must be established and the higher that accompanies it. between a higher This tradeoff must be considered carefully in future devices so that SiGe HBTs can be fully utilized in the many new and exciting application spaces developing for wired and wireless applications. D. Leverage of SiGe HBTs for RF Circuits The SiGe HBT can be applied to many applications that require stringent demands on device performance. SiGe can also provide an exceptional integrated solution to the demanding wireless communications market when combined with RF elements made possible by a good BiCMOS process. High-isolation structures can be realized by combing deep trench (DT), metal layers, and active layers. The availability of an optional solder-bump layer enables high-density flip-chip packaging. Si has high thermal conductivity when compared to GaAs, which allows denser integration, power devices, and higher reliability. Such a process can satisfy the requirements of RF circuits (LNAs, PAs, mixers, modulators, VCOs, etc.), mixed-signal circuits (fractional N synthesizers, analog to digital converters, etc.), and precision analog circuits (operational amplifiers, band gap references, temperature and bias control, etc.). A

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TABLE III PERFORMANCE OF AMPLIFIERS BUILT WITH PLASTIC PACKAGED SiGe HBTS. THE HBTS WERE ASSEMBLED WITH OTHER DISCRETE COMPONENTS ONTO FR4 BOARDS FOR EVALUATION

Fig. 12. Minimum noise figure and associated gain versus frequency for a wafer probed BAGate 0.44 12 m NPN at various current levels ( V).

2

1

V =

Fig. 14. Two-tone intermodulation distortion measurements taken at 1.9 GHz on SGRF0100 RF transistor. Input tone spacing is 20 KHz with 73 dB harmonic signal. Intercept points based on these measurements result in OIP3 in excess of 26 dBm and an IIP3 value of 12 dBm.

0

+

(a)

(b)

V V

Fig. 13. Example of statistical device models showing (a) histogram of for 0.5 1.0 m HBT at 10 A Ie. (b) Illustrates a probability plot for comparing measured hardware (approximately 200 samples) and device model to a normal distribution (line).

2

single-chip radio, conceivably comprised of all these circuit types, can leverage the strengths of a SiGe BiCMOS process. The most significant feature of the SiGe BiCMOS process is the HBT; it has the desired performance in the areas of matching, and linearity. The good gain and gain, noise, linearity offer current savings—an important aspect of portable electronics that are powered by batteries. Battery life is one of the top selling features of these products. Fig. 12 shows NFmin and the associated gain (GA) of the on-wafer BAGate HBT cell. The high gain of a SiGe HBT has the effect of a reduction in current by requiring less gain stages or amplifiers per a given system and/or stages that use less current to achieve the same matching to gain. The HBT needs to have a high degree of enable, for example, precision current mirrors used in biasing, the reduction of offset voltage in operational amplifiers (op amps), and, in general, to increase product yields. The process to meet these circuit of the SiGe HBT ensures consistent demands (Fig. 13). The inherent linearity of the HBT device [34] can also result in lowered power consumption. For example, an RF driver amplifier in the transmit chain of a digital handset may require a certain linearity, usually specified by adjacent power channel ratio (ACPR). Using a more linear device can allow the spec-

+

ification to be met at a lower current. To demonstrate the performance of the SiGe HBT, several circuits were constructed using packaged HBTs and printed circuit board material and discrete surface mount components similar to what is used in handsets. These circuits, several amplifiers and several mixers, are described in the following paragraphs. To evaluate gain, linearity, and noise figure, packaged SiGe HBTs (0.5 m generation BDGate devices, emitter area 62.5 m ) have been used to produce various amplifiers and tested. The results of these tests are summarized in Table III. The LNA evaluation circuits demonstrate they can meet the typical dc power, linearity gain, and the low noise figure requirements placed on rf amplifiers in wireless handsets [35]. Fig. 14 shows the good linearity as measured by a two-tone test. In this test, two large signals that are closely spaced in frequency are input to the circuit. Nonlinearities in the HBT cause the signals to mix producing products that are close in frequency to the input signals’ frequencies. These products are so close in fact that they tend to be in the same band as the wanted signal and therefore cannot easily be filtered out. These are the third-order products and one can be seen in Fig. 14, albeit at a very low level, demonstrating the high linearity of the HBT LNA. Another evaluation circuit of similar construction, but using discrete baluns and a plastic-packaged quad of SiGe HBTs (0.5 m generation BDGate devices emitter area 50 m ), was successfully used to produce an active mixer. Driven by a 740 MHz LO at 0.0 dBm and biased at 5 mA and 2.85 V, the mixer has a conversion gain of 11.7 dB and a SSB NF of 5.8 dB. An IIP3 of 0.31 dBm at 850 MHz RF input frequency was obtained. The same core, biased at 55 mA, was evaluated

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TABLE IV COMPARISON OF RF DEVICES SUITABLE FOR RF APPLICATIONS

(a)

(b)

Fig. 15. RF parametric histograms for (a) gain (S ) and (b) OIP3 for HBT packaged parts measured on RF production tester.

for use as a 1.9 GHz base-station mixer; it yielded an IIP3 20 dBm, 10 dB SSB noise figure, with a conversion gain of 1.0 dB. Fig. 15 shows manufacturing data for packaged SiGe HBTs (0.5 m generation BDGate devices, emitter area 62.5 m ) that was obtained on a commercially available production RF test system. The data in demonstrates very-well-controlled RF parametrics (illustrated by the gain ( ) and OIP3). Statistical process control data from a sample size of 500 measurements indicate a very high process capability (Cpk 5) for both parameters [36]. These extremely tightly controlled performance benchmarks are key to the wide acceptance of SiGe RF components in the marketplace. To determine how the SiGe HBT compares to other rf capable device technologies, a new figure of merit, the dynamic range merit (DRM) [37], is defined for comparison. The DRM couples linearity efficiency [38] with noise figure and gain via the device noise measure: DMR

Gain

IIP3

NF

All measured parameters are numeric. The noise factor (NF) is the device noise figure converted from dB to numeric; the third-order intercept is converted to power in mW; and the gain is expressed as a numeric for the noise figure and intercept achieved. While no single number can accurately weigh optimal trade off for all RF circuits, the purpose of the DRM figure is to pull together the significant circuit parameters of gain, power dissipation, noise figure and distortion into a figure of merit for technology comparison in an LNA application. Although linearity efficiency is an important factor, the potential degradation of other factors such as noise figure at increased device current, prompted a broader merit function. Limiting the comparison scope to a single device and representative circuit function, such as a RF low noise amplifier, provides a tool to assess performance. Table IV summarizes a comparison of a SiGe HBT device with several other commercially available technologies used in RF design. These devices are packaged components and data is supplied from manufacturer data sheets. These figure-of-merit values indicate that the SiGe HBT device is

capable of state-of-the-art RF performance at costs based on 200 mm wafer silicon CMOS fabrication and with very low power consumption. It should be emphasized that, while the SiGe HBT does not have the highest DRM figure of merit, it is competitive with even the best technologies, and is the only BiCMOS technology providing high levels of integration. Other aspects not considered in the figure of merit are 1/ noise and device matching, which further enhances the SiGe HBTs advantages. The leverage enabled through BiCMOS with high levels of integration make the SiGe HBT extremely attractive as applications merge analog and digital functions. The following circuits use the other elements in the technology in addition to the SiGe HBT. Measured data was taken on two representative RF circuits, an integrated VCO and an integrated receiver, that exemplify the high performance and high integration attainable with SiGe BiCMOS. Both circuits fully leverage the available features of the SiGe BiCMOS process such as the HBT, isolation structures, thick last metal, CMOS devices, and high Q passives. A 3 GHz integrated VCO with a 23% tuning bandwidth has been produced which includes, on chip, the resonator, all bias and logic functions, and varactors [39]. Figs. 16 and 17 show graphs of phase noise at a current of 9.0 mA and a voltage of 2.5 V. The phase-noise results on Si RFIC with on-chip resonator are among the best to date when compared to similar circuits. Another example of an RFIC integrated circuit taking advantage of the high integration capabilities of the SiGe BiCMOS is a recently built differential dual-band image reject receiver [40]. The receiver’s circuits include two LNAs, two planar 4 : 1 baluns, two balanced lumped element transformers, an image filter, two image reject mixers, an IF polyphase filter, an IF amplifier, two divide-by-four frequency dividers and all bias and interface decoder circuitry (Fig. 18). The measured performance is summarized in Table V and is very competitive in terms of image rejection, noise figure, and power consumption [41]. These example circuits demonstrate the ability of SiGe to meet the stringent demands on wireless products today, while showing a clear path toward the highly integrated systems on a chip of the new future. E. High-Breakdown Voltage Technology for SiGe Power Amplifiers The power amplifier is a highly competitive segment of a wireless communication system that is mainly dominated by GaAs-based devices (HEMTs, MESFETs, and HBTs). SiGe

HARAME et al.: CURRENT STATUS AND FUTURE TRENDS OF SiGe BiCMOS TECHNOLOGY

Fig. 16. Phase noise measurement of the integrated VCO at Vtune at 0.3 V. Vtune is the analog fine tune voltage used to tune between the digital tune steps.

Fig. 17. Phase noise measurement of the integrated VCO at Vtune at 2.2 V. Data points on graphs are indicated by markers on traces and are the digital tuned frequency steps.

BiCMOS provides the opportunity to develop state-of-the-art PA performance with fully integrated bias- and power-control circuitry. Furthermore, with SiGe, integration is possible with other low-cost transceiver blocks that are dominated by Si-based technologies. Low-cost RF and mixed-signal technologies capable of combining high performance, low power consumption, and high integration level will be a key to success in the rapidly growing market for wireless products. In high-efficiency handset power amplifiers, the peak voltage seen by the device can be two to three times the supply voltage because of the RF swing in the device. This requires that the SiGe process provide a high-breakdown voltage for the handset power amplifier applications. As discussed above, a high-breakdown device has been demonstrated in GHz, the 0.5 m SiGe BiCMOS process with an V, and V [42]. To benchmark the performance of this high-breakdown device, single-stage amplifiers were fabricated using a plastic-packaged 640 m power device soldered to a soft-substrate with matching components. Power-added efficiency (PAE) is very important for saturated power-amplifier applications, and is defined where output power; input power; dc power. When tuned for maximum efficiency (Fig. 19) the 640 m power device can deliver greater than 70% PAE at 900 MHz, and 63% PAE at 2 GHz; this performance is very competitive

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to other state-of-the-art power-amplifier [43], [44]. For linear modulation schemes such as CDMA, the key figure of merit for a power amplifier is the amount of efficiency the amplifier can achieve while satisfying the adjacent-channel-power-ratio (ACPR) specification. ACPR is defined as the ratio of the distortion power in the adjacent channel to the signal power in the signal bandwidth. When tuned to provide maximum efficiency while satisfying the linearity requirement, (as shown in Fig. 20) the 640 m power device can achieve 44% PAE at ACP 46 dBc, which is very competitive with other PA technologies (as [45]. In addition, since the SiGe BJT has a small compared to GaAs HBT), the PA performance is maintained V and below. The 640 m device can maindown to tain 70% PAE saturated and 44% PAE at ACP 46 dBc for V to V. These results indicate CDMA from that SiGe can provide competitive performance for both saturated and linear handset power amplifiers. While the overall trend for battery voltages is steadily decreasing, the charging voltages for the handset batteries are not scaling proportionally. Higher charging voltages are preferred for more efficient battery-charging. In addition, for less expensive handset solutions, the market trend is moving toward eliminating the circulator. These conditions dictate using of a highly rugged PA that can tolerate high-voltage excursions due to either load mismatch (quantified by VSWR) or charging voltages. The requirements for the HBT breakdown voltage in PAs are in stark contrast to the high-performance ( ) devices, posing significant device-design and integration challenges. However, because Si devices are defined by implants and not by a pre-grown epi-structure, common in the III–Vs, it is possible to have both high cut-off frequency and high-breakdown voltage devices in the same technology offering. This allows some flexibility in tuning the breakdown voltage of the high-breakdown device in the technology. A SiGe HBT (or Si bipolar) has a lower breakdown voltage relative to III–Vs due to higher impact ionization at the collector-base (CB) junction. This is a limitation for output devices that must tolerate (survive) high VSWR conditions; i.e., transmitting under large-output load-mismatch conditions. High VSWR conditions can occur if a cell-phone antenna is touched or pulled off while transmitting a call. Therefore, for a rugged PA design it is preferred (compared to circuit design solutions) that the device support high breakdown voltages with minimal degradation to RF performance. Therefore, it is important to design the SiGe PA device to tolerate high VSWR. To increase the robustness of the power device to high peak voltages, the peak CB electric field must be reduced below the critical field. Thus, to a great extent, the maximum tolerated output peak voltage (hence VSWR) will be governed by the CB breakdown voltage; . Since the peak electrical fields at the CB junction i.e., occur at the intersection of the extrinsic base and the selectively implanted collector (SIC) profiles, one would expect that the . The separation further their separation the higher the is accomplished by increasing the collector epilayer thickness and moving the SIC deeper into the epilayer silicon.liver 44% PAE at an ACPR 46 dBc. on the Fig. 21 shows the expected dependency of epi-thickness and SIC implant depth. The tradeoff, however, is

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Fig. 18.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001

Block diagram of the dual-band receiver IC and supporting off-chip components. (Block diagram of image reject mixer.)

TABLE V LNA/IRM PERFORMANCE SUMMARY V = 2:7 V, Pin = 35 dBm, Plo = 10 dBm, IF = 400 MHz, Rs = 50, Rl = 600

0

f

0

g

Fig. 20. Measured 900 MHz linear-power sweep for 640 m power device tuned for maximum power-added-efficiency under CDMA modulation. Data was taken at V = 3:0 V. The process can deliver 44% PAE at an ACPR = 46 dBc.

Fig. 19. Measured 900 MHz power sweep for 640 m power device tuned for maximum power-added-efficiency. Data was taken at V = 3:0 V. The process can deliver >70% PAE for at 26 dBm.

a slightly reduced peak- due to the Kirk effect and increased quasisaturation due to higher collector resistance (Fig. 22). As discussed in Section III-C1, collector-profile optimization as well as high . A signifiis key in attaining high cant increase to the N-epi thickness to support the power device

Fig. 21. BV dependence on the N-epi thickness and the collector profile (inset). POR represents the reference condition used in the parent technology.

causes detrimental changes to the high device because of increased collector resistance. The first high-breakdown voltage

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Fig. 22. f versus I for both pedestal and nonpedestal NPNs fabricated using the thicker N-epi process. These characteristics are also compared to the device performances in the parent technology.

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Fig. 23. Comparison of 900 MHz PA performance for 640 m power device in V = 14 V and V = 20 V technologies. The higher breakdown technology has nearly equivalent performance to the V = 14 V technology.

TABLE VI COMPARISON OF DC DEVICE CHARACTERISTICS BETWEEN THE PARENT TECHNOLOGY AND ITS DERIVATIVE, BOTH IN 0.5 m SiGe TECHNOLOGY

technology to address this issue is a derivative of the mature 0.5 m SiGe BiCMOS production technology. A key constraint to the integration is the minimal perturbation to other library elements and logic books offered in the parent technology, allowing for design portability. With the exception of the Schottky Barrier Diode (SBD) characteristics which are solely determined by the silicide-subcollector junction, the device elements have been “tuned” to closely match the parent technology (Table VI). Single-stage saturated-power amplifiers developed in this 20 V) have demonhigh-breakdown technology ( strated the ruggedness to survive a 10 : 1 VSWR load mismatch V and full RF power. The increased ruggedness has at been achieved at nearly equivalent power gain, and efficiency (Fig. 23). Which indicates that the intrinsic device is capable of withstanding the high peak-to-peak output voltage swings at the rated output power. Further scaling of the emitter area and optimization of both the device and circuit layouts will provide a single-ended PA that is cost-effective, reliable, and rugged, all key metrics for the drive toward a single-chip phone solution. F. SiGe HBT Reliability Device reliability is a very important factor for achieving widespread acceptance of the SiGe HBT in telecommunications and mixed-signal applications. The SiGe HBT has been subjected to reliability stressing as part of technology and product qualifications at IBM. In particular, SiGe HBT reliability stressing has been conducted in both forward-bias and reverse-bias modes, using the same accelerating stress conditions and analysis techniques developed for previous

Fig. 24. HBT degradation under forward bias stress of 0.5 emitter stressed at 1.3 mA/m current density.

2 2.5 m

implanted-base silicon bipolar technologies [46]. Less than a 5% change in NPN current gain ( ) over a 500-hour stress at 140 C and 1.3 mA/ m (near peak ) was found for the 0.5 m generation SiGe HBTs (Fig. 24). Most GaAs HBT technologies are stressed at currents far less than the peak current [47] which wastes much of the potential device performance. Using empirically determined acceleration factors, the SiGe HBT forward-bias result is equivalent to less than 10% degradation under typical-use conditions (1.25 mA/ m at 100 C) after 100 K power-on-hours (POH). Change in is attributed to electromigration-induced pressure on the emitter contact, causing decreased collector current with stress condition [46]. A consideration for subsequent generations of ( 90 GHz) SiGe HBTs is that the devices will attain higher through a combination of increased collector doping to suppress base push-out, and aggressive lateral scaling to minimize parasitic capacitances. This means that transistors will operate at emitter current densities far greater than today’s devices and will be designed with narrow and thinner metal interconnects. Clearly, future transistor technologies will require interconnect metals with greater immunity to electromigration than today’s aluminum-based metallurgy (copper), or multiple levels of metal will be needed just to support the high current contacts of the NPN. Therefore, the choice of transistor design point will have an influence on the interconnect technology used for a given BiCMOS generation.

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=

Fig. 25. HBT change in (at I 100 A) for reverse bias stress after 500 hour stress performed at 40 C. Degradation is negligible below 2.0 V reverse bias.

0

Reverse emitter/base (EB) bias stress is conducted in order to set HBT-use guidelines for allowed emitter base bias in circuit applications. Since reverse bias degradation is a result of hot electron trapping, this effect is magnified at lower temperatures. Fig. 25 illustrates the degradation of base current at an emitter current of 100 A for 0.5 m generation SiGe HBTs at 40 C for reverse emitter-base bias of 2.0, 2.3, and 2.7 V. With reverse bias of 2.0 V or less, no measurable change in base or collector currents is observed. This hot-electron degradation with reverse bias stress is typical of bipolar junction transistors and is substantially lower for the epi-base devices when compared to ion-implanted base double-polysilicon BJTs [46]. This result is attributed to the reduced of the electric field at the emitter-base junction due to a base doping set back which can be achieved with epitaxial base growth and is expected to be similar with HBT vertical and horizontal scaling. The spacing between the emitter and the self-aligned extrinsic base, however, is one area that cannot be scaled without reliability concerns. Future transistor designers will not be able to scale this aspect of the transistor indefinitely without making the appropriate tradeoff between minimizing base resistance and limiting allowable reverse-bias conditions in circuit applications or, in the extreme limit, accepting base-tunneling current at low emitter-base biases. IV. HIGH Q PASSIVES: INDUCTORS AND CAPACITORS High-Q on-chip passives are required to meet the demanding requirements placed on today’s RF circuits and to achieve the “system-on-a-chip” integration levels that are possible with a SiGe BiCMOS process. In silicon processes, it has been particularly challenging to achieve integrated inductors with adequate Qs. Q values of 15 to 20, or greater, are required for some demanding applications (e.g., VCO phase noise requirements) [48], [49]. To-date Q values of this magnitude have been associated with GaAs processes, as a result of the semi-insulating substrate loss characteristics [50] (and thick gold interconnects) when compared to the high substrate losses inherent in a silicon process. A typical Q value in standard BiCMOS processes is a maximum of about 10 (for inductances of 1 nH).

Fig. 26. Typical spiral inductor cross-sectional schematic and its associated lumped element model.

A. Inductors Inductors integrated in a typical Si or SiGe process use Al/Cu metallization to pattern the spiral and underpass. This metal is to 100 m depending on the inherently resistive (10 m thickness) and, as the level of integration rises, the metal is typically thinned to decrease the achievable line pitch (driven by the base CMOS technology). This thinning of the metal levels and their associated interlayer dielectrics as process technologies advance, creates a fundamental problem when attempting to realize the high Q inductors needed to achieve highly integrated RF IC designs. Substrates used in bipolar/BiCMOS RF processes (including SiGe BiCMOS) typically have a medium substrate resistivity (10–20 -cm), while high performance conventional CMOS processes may be obliged to use a low resistivity epi substrate ( 0.01 -cm) [51]. Due to the interaction of the electric and magnetic fields of the spiral inductor with the substrate, parasitic substrate currents can be established in the substrate material. Parasitic currents that occur from the electric-field interaction with the substrate will cause power losses in the inductor, lowering Q [52]. Parasitic currents that flow because of the inductor’s magnetic field (eddy currents and image currents) will not only cause power losses but will reduce the net inductance of the spiral due to a reduction in the net magnetic field. Eddy and image currents in the substrate typically become significant for substrates with resistivities of less than 5 -cm, or in ground planes with sheet resistances of less than 12 /sq. [53]. 1) Q Optimization: Fig. 26 shows a cross-sectional schematic of a spiral inductor and its associated lumped element model. The three main parasitic elements contributing to Q degradation are: the series resistance in the spiral (R1), the substrate resistance (R2, R3), and the spiral to substrate capacitance (C1, C2). The detrimental effects of these three parasitic elements can be enhanced or diminished through

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Fig. 28. Measured Q improvements observed for single and multi-turn spirals of 5 m and 20 m turn widths.

Fig. 27. Q comparison, POR backend versus POR backend plus thick dielectric (3 m) and thick last metal (4 m).

either layout techniques or process-technology adjustments [54]–[58]: In descending order of effectiveness: 1) the series resistance can be reduced; 2) the effective substrate resistance can be either raised or lowered; and, 3) the oxide capacitance can be decreased. Each technique can be employed singly or in combination, with cumulative results. For example, lowering the series resistance does not preclude the additional advantage obtained when reducing the substrate losses. The highest percentage improvement in inductor peak Q is achieved by reducing the series-resistive losses of the spiral, with increases of more than 100% possible [54]. Decreasing the spiral-metallization sheet resistance to achieve the maximum Q improvement has the least effect on the base CMOS process flow. In the 0.25 m process [31], the maximum Q improvement was achieved by adding a 4 m thick aluminum metallization level above the final metal level in the base CMOS process. The interlayer dielectric between this thick metal layer and the previous “final” metal layer was also increased in thickness from 1.2 m to 3.0 m. This helped offset the detrimental effects of thinner dielectric stack heights seen in the next-generation back-end-of-line processes. The thicker metal also may be used for low loss transmission lines, which cannot be achieved by most of the various techniques employed to enhance inductor Q alone. Power-supply and ground-routing capability is also favorably enhanced, with an important advantage being the ability to create true low-impedance AC grounds. With this process enhancement, peak Q improved by over 90% (Fig. 27). It has been suggested that, due to the skin effect, a point of diminishing returns is reached when thickening the spiral metallization beyond about 2 m [58]. We contend that, due to current-crowding effects caused by adjacent spiral turns, a portion of the current in the spiral tends to flow along one edge of each spiral turn. If this is the case, a thicker metal should allow more vertical sidewall for this “edge current” to flow on to offset some or all of the skin-effect disadvantages. Since a spiral with more turns has more of the overall length subjected to this “edge” current (due to the adjacent turns), it is expected

that a multi-turn spiral will have it’s Q improved more than a one or two turn spiral from thickening the metal. Additionally, spirals with narrow turn widths would be expected to have a greater advantage from thickening the metal since the vertical sidewall comprises a greater percentage of the overall surface area available for current flow. Fig. 28 shows measured Q improvements observed for single and multi-turn spirals of 5 mand 20 m-turn widths. As expected, the greatest Q improvement was observed for the narrow-turn-width (5 m) multi-turn (6.5 turns) spiral, with a 74% peak Q increase attributable to thickening the spiral metallization alone. No additional dielectric under the spiral metal was added in this experiment. While the wide-turn width-(20 m) spiral showed the least improvement, it still achieved a peak Q improvement of 30% when the metal thickness was increased from 2 m to 4 m. The increasing use of copper interconnect in high-end CMOS and BiCMOS processes provides the potential for reducing the series resistance by as much as a factor of two over standard Al/Cu interconnects. This potential is typically not realized, however, because the lower resistivity of copper interconnect has been offset by a proportional thinning of the metallization to achieve tighter line pitches. To realize the full potential of copper interconnect for RF technologies, the copper thickness must be increased, at the expense of packing density, at least in the final metal level. The second approach to optimizing inductor Q, altering the effective substrate resistivity, can yield peak Q improvements of 50% or more [53], [56], [57]. Raising the substrate resistivity (i.e., using float-zone wafers) implies a significant departure from the base CMOS process flow and is therefore not cost-effective. Approaches to lowering the effective substrate resistivity, without allowing magnetic field-induced image and eddy currents to flow, include adding a Faraday shield (patterned ground plane) [53] or the addition of a low resistivity “halo” implant outside of the inductor that forms a broken loop around the spiral [57]. Both approaches concentrate on terminating the parasitic electric field from the spiral in a low-impedance AC ground before it has a chance to flow any great distance in the substrate. We have observed as much as a 35% improvement in peak Q when using a Faraday-shield-type patterned ground plane (and have incorporated this option in our latest SiGe technology offerings). An additional benefit to the Faraday shield approach is that passives using this technique also enjoy a re-

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duction in noise injection or cross-talk [59]. By using a “halo” diffusions in the substrate a 40% improvement was achieved [57]. The Faraday shield approach is gaining acceptance in the industry as designers incorporate this type of inductor in their designs and observe the advantages. However, the increased Q realized with a Faraday shield comes at a cost. The proximity of a low-impedance ground plane under the spiral causes the inductor’s self-resonant frequency to decrease, moving it closer to the desired frequency of operation for the spiral (peak Q frequency). This means that there is proportionately more phase shift in the spiral, at the frequency of operation, when compared to a standard spiral. The increased phase shift causes a reduction in the effective inductance; the effect becomes noticeable at frequencies very close to peak Q. When using the Faraday shield method the designer needs to be aware of the inherent variability of the inductance and needs to weigh that against the increased advantages. The third approach to Q improvement, decreasing the oxide capacitance, yields only about a 20% maximum improvement for a doubling of the dielectric stack height (approximately equivalent to cutting the dielectric constant in half), based on our own data. Because doubling the dielectric stack height implies adding extra metal levels (very thick dielectrics must be applied in stages to reduce warpage), the third approach was deemed not cost-effective. The fabrication of integrated inductors on silicon with Q values approaching 20 enables RF IC designers to realize highly-integrated, low-cost integrated circuits. B. Capacitors Capacitors with high Q’s are an important element for the design of analog integrated circuits. There are fundamentally three kinds of capacitors used in silicon semiconductor technology: 1) polysilicon gated substrate capacitors (MOS caps), 2) polysilicon–dielectric–polysilicon capacitors (poly–poly caps), and Metal–Insulator–Metal (MIM caps). The MOS capacitor consists of an n polysilicon gate top plate, 11 nm thermal oxide dielectric, and single crystal bipolar “reach-thru” region as the bottom plate. Use of the high dose reach-thru implant (25 /Sq.) and the highly doped subcollector (8 /Sq.) in the MOS capacitor structure allows a low series resistance and Qs of approximately 20 are realized [31], [60]. The poly–poly capacitor consists of a n gate polysilicon bottom plate, 20 nm deposited oxide, and Ti-silicided p polysilicon top plate. The MIM capacitor [61] consists of an underlying metal layer, 50 nm deposited oxide, and 200 nm AlCu with TiN over/under. The characteristics of the three different capacitors are summarized in Table VII. The MOS capacitor has the highest capacitance per unit area at 3.1 fF/ m , compared to the poly–poly and MIM capacitors at 1.7 fF/ m and 0.7 fF/ m respectively. Comparing the voltage coefficients shows the poly–poly capacitor has a more linear V–C relationship than the MOS capacnear zero. Although the MIM has itor while the MIM has a the lowest capacitance of the devices outlined, high Q values can be achieved with this device due to the low series resistance and parasitic capacitance of the metal plates [61], [62]. With Q values of 70–80 at 2 GHz, this device is preferred in RF applications where high Qs and low parasitic capacitances are required

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TABLE VII COMPARISON OF VARIOUS CAPACITORS AND THEIR TYPICAL PARAMETRICS

Fig. 29. Time-to-breakdown (log seconds) at 125 C as a function of applied electric field for the MOS, poly–poly and MIM capacitors.

[63]. The MOS and poly capacitors provided are used where higher capacitance devices are needed for applications such as power supply bypass and decoupling. Capacitor reliability is of primary importance when considering technology development and design applications [64], [65]. In Fig. 29 a graph of time-to-breakdown (log seconds) at 125 C as a function of applied electric field for the MOS, poly–poly and MIM capacitors is shown [66]–[68]. Large area capacitor arrays on the order of 100 K m were used for the test. This data is collected at high electric fields to minimize data acquisition time and is projected to use conditions at 100 K power on hours (POH). The data shows the MIM capacitor fails at a lower applied field for a given time to failure than the MOS or poly–poly capacitors. The MIM oxide is a PECVD oxide while the poly–poly capacitor is a high quality CVD oxide and the MOS capacitor a thermally grown oxide. The data shows that the MOS and poly–poly capacitors have equivalent reliability since the time to fail data falls on the same line for both devices. Extrapolating the data to 100 K power on hours shows that all three capacitors are reliable well within the use conditions. The MIM capacitor is used at an applied field of 1 MV/cm, the MOS capacitor at 3.2 MV/cm and the poly–poly capacitor at 2.5 MV/cm. Future challenges associated with capacitor development will include developing higher-capacitance devices with low series resistance for high Q values and low-voltage coefficients. This will involve the use of reliable deposited dielectrics [69]–[71]. As gate dielectrics become thinner, it will be more difficult to make reliable MOS capacitors due to the enhanced growth of gate oxides over highly doped Si. Using thin CVD films as reliable dielectric materials will be an area of much focus.

HARAME et al.: CURRENT STATUS AND FUTURE TRENDS OF SiGe BiCMOS TECHNOLOGY

V. CONCLUSIONS Important trends of SiGe BiCMOS have been presented. The key integration trend in BiCMOS is toward building the bipolar after the CMOS, so that the CMOS process steps can be exactly copied from a base CMOS process and with a modular process. Building the bipolar after the CMOS decouples the SiGe HBT thermal cycle from the CMOS allowing for a more ideal SiGe HBT fabrication process. The SiGe HBT trend is toward smaller faster devices with significantly increased current densities. Scaling the devices and improving both the and will be a significant challenge as the peak base and collector dopant concentrations are increased. A newly proposed figure-of-merit (DRM), which includes the significant circuit parameters of gain, distortion, power dissipation, and noise figure indicates that the IBM SiGe HBT is capable of state-of-the-art RF performance with definite cost advantages. For power amplifiers, it was noted that, although there is pressure to reduce cellular handset voltages, there will still be a need for high breakdown voltage devices, because of VSWR and a desire to simplify designs. It will be more difficult to develop high-voltage derivatives as the parent technology is pushed toward higher performance. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers are counter to the requirements of high Q inductors and capacitors; A custom metallization layer may be required. These interesting trends will provide SiGe BiCMOS technologists with many new challenges to overcome. ACKNOWLEDGMENT The authors would like to thank all of the people in the IBM SiGe effort for help with this work. Special thanks goes to W. Stein and the Burlington Fabrication Facility and the Advanced Semiconductor Technology Center (ASTC) for fabricating of all the hardware discussed to in this work. Special thanks also goes to D. Jadus and ASTC device development group and T. Wilson and the Burlington modeling and design kit groups for help with design, modeling, and measurements of the SiGe HBT BiCMOS technology. REFERENCES [1] Qualcomm Feb. 8, 1999, Press Release. RFR3100™—IF receive device. [Online]. Available: http://www.qualcomm.com/ProdTech/asic/products/rfr3100.html [2] R. Lodge, “Advantages of SiGe for GSM RF front ends,” Electron. Eng., vol. 71, no. 865, pp. 18–19, Feb. 1999. (UK). [3] R. Gotsfried, F. Beisswanger, S. Gerlach, A. Schuppen, H. Dietrich, U. Seiler, K. H. Bach, and J. Albers, “RFIC’s for mobile communication systems using SiGe bipolar technology,” IEEE Trans. Microwave Theory, Tech., pt. 2, vol. 46, pp. 661–668, May 1998. [4] Intersill 9/22/1999 Press Release. Intersil’s newest PRISM WLAN chipset now available for high performance, high speed wireless networking—Half the chips, half the power, 5X the speed. [Online]Posted in Intersil home page. Available: http://www.intersil.com/whatsnew/PRISM/PCS99_2.asp [5] AMCC 10/11/99 Press Release. AMCC introduces the industry’s first 10 Gbps silicon germanium OC-192 SONET/SDH limiting amplifier. [Online]Posted in AMCC Home Page. Available: http://www.amcc.com/Compinfo/PressReleases/S3096pr.htm

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David L. Harame (S’77–M’83–SM’01) was born in Pocatello, ID, in 1948. He received the B.A. degree in zoology from the University of California, Berkeley, in 1971, and the M.S. degree in zoology from Duke University, Durham, NC, 1973. He received the M.S. degree in electrical engineering from San Jose State University, San Jose, CA, in 1976, and the M.S. degree in materials science and the Ph.D. degree in electrical engineering, both from Stanford University, Stanford, CA, in 1984. He joined IBM’s Bipolar Technology Group at the IBM T. J. Watson Research Center, Yorktown Heights, NY, in 1984, where he worked on the fabrication and modeling of silicon-based integrated circuits. His specific research interests at Yorktown Heights included silicon and SiGe-channel FET transistors, NPN and PNP SiGe-base bipolar transistors, complementary bipolar technology, and BiCMOS technology for digital and analog and mixed-signal applications. In 1993, he joined IBM’s Semiconductor Research and Development Center in the Advanced Semiconductor Technology Center, Hopewell Junction, NY, where he was responsible for the development of SiGe technology for mixed signal applications. He managed SiGe BiCMOS technology development at the ASTC through 1997. In 1998, he joined IBM’s Manufacturing Organization, Essex Junction, VT, where he managed a SiGe technology group and installed the 0.5 m SiGe BiCMOS process in the manufacturing line. In 1999, he rejoined the Semiconductor Research Corporation while remaining in Essex Junction, VT and co-managed the qualification of a 0.25 m SIGe BiCMOS as well as 0.18 m SIGE BiCMOS and two derivative SiGe BiCMOS technologies. In May 2000, he became the Senior Manager of the RF Analog Modeling and Design Kit Department. Dr. Harame is a Distinguished Engineer of the IBM Corporation, an Executive Committee member of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), and a member of the Compact Model Council.

David C. Ahlgren received the B.A. degree from DePauw University, Greencastle, IN, in 1973 and Ph.D. in chemical physics from The University of Michigan, Ann Arbor, in 1979. He joined IBM, Hopewell Junction, NY, in 1979, conducting semiconductor process development. His early work was in the area of silicon defects resulting from ion implantation and isolation stress, as well as process integration issues which lead to the development and subsequent production of IBM’s first double polyslilicon bipolar technology in 1983. In 1989, his attention turned to Si/SiGe HBTs as the next step in the advancement of IBM’s bipolar mainframe semiconductor technology. His early device studies, process technology work, and semiconductor production experience has lead him into his current role in the Advanced Semiconductor Technlology Center as a Senior Engineer in device and process development of high performance Si/SiGe BiCMOS technology and its introduction into manufacturing. He has published over 30 papers and holds eight patents in semiconductor device and process technology.

Douglas D. Coolbaugh received the B.S. degree in chemistry from Hobart College, Geneva, NY, in 1980 and the Ph.D. degree in physical chemistry/surface science from the State University of New York, Binghamton, in 1987. He joined IBM in 1980 and his work was primarily focused on packaging and assembly development/manufacturing in Materials Engineering until 1996. He is currently with IBM, Essex Junction, VT, where his research focuses on passive elements and HBT yields for their advanced SiGe BiCMOS technologies.

James S. Dunn received the B.S., M.E., and Ph.D. degrees in materials science and engineering from the University of Utah, Salt Lake City, in 1983, 1989 and 1989, respectively. He joined IBM in Essex Junction, VT in 1989, where he worked on BiCMOS technology development for Analog and Mixed Signal Applications. Since 1992, he has managed a group developing conventional silicon and SiGe based BiCMOS technologies.

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Gregory G. Freeman received the B.S.E.E. degree from the University of Delaware, Newark, in 1984 and the M.S.E.E. and Ph.D. degrees from Stanford University, Standord, CA, in 1986 and 1991, respectively. His dissertation dealt with data analysis for semiconductor process diagnosis. Since 1991, he has been with IBM, East Fishkill, NY, working on the development of advanced semiconductor processes, including DRAMs, logic, and for the last five years, SiGe BiCMOS. His current interests are active and passive device design, integration, and characterization.

John D. Gillis (M’86) received the B.S.E.E. degree in electrical engineering from the University of Massachusetts, Amherst. He spent six years at Raytheon ESD, including one year at Raytheon Research Division designing GaAs MMICs. In 1993, he joined ITT Gilfillan where he worked in the Advanced Systems Group on GaAs modules. In 1995, he joined Raytheon’s Advanced Device Center as a Senior Engineer, where he developed GaAs RFICs for cellular products. In 1998, in joined IBM Microelectronics, RF/Analog Product Development, Tewksbury, MA, where he is a Senior Engineer/Scientist working with SiGe for wireless applications. Mr. Gillis is a member of Eta Kappa Nu.

Robert A. Groves (M’94) received the B.S.E.E. degree from the State University of New York in 1996. He joined IBM Corporation, Microelectronics Division, East Fishkill, NY, in 1989 as a Development Lab Technician, Since 1994, he has worked on SiGe technology development, with an emphasis on high frequency modeling and characterization. His current interest is in microwave passive devices on silicon (interconnect, capacitors, and inductors), particularly integrated spiral inductor optimization and modeling.

Gregory N. Henderson received the B.S. degree in electrical engineering from Texas Tech University, Lubbock, in 1989 and the Ph.D. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1993. Since then, he has worked in device design/engineering, process development, and circuit design for wireless communications applications, with a specific focus on the development of high-performance technologies for power amplifiers. He has worked at M/A-COM and is currently the Design Manager for Power Amplifier development at IBM Microelectronics, East Fishkill, NY. He has over 25 journal and conference papers in the areas of wireless communications and solid-state physics.

Robb A. Johnson (S’90–M’97) received the B.S. degree in 1992, the M.S. degree in 1993, and the Ph.D. degree in 1997, all in electrical engineering, from the University of California at San Diego, LaJolla. His dissertation was on technology development and circuit design with silicon-on-sapphire MOSETs for microwave circuit applications. He is currently with IBM Microelectronics Division, Essex Junction, VT, working on process development and device characterization with SiGe BiCMOS Technology. He has worked on device characterization and high-speed circuit design in AlGaAs/GaAs and InP-based HBT technologies.

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Alvin J. Joseph (M’96) received the B.E. degree in electrical engineering from Bangalore University, India, in 1989, and the M.S. and Ph.D. degrees, both in electrical engineering, from Auburn University, Auburn, AL, in 1992 and 1997, respectively. His doctoral research involved the study of physics, optimization, and modeling of cryogenically operated SiGe HBTs. In 1997, he joined the SiGe Technology Development Group in IBM Microelectronics Division, Essex Junction, VT. He has been involved in various aspects of installing several SiGe BiCMOS technologies into production. He is currently the process integration team leader for qualifying the 0.18 m SiGe BiCMOS technology to production. He has authored and co-authored several technical journal papers and conference publications related to SiGe HBTs. Dr. Joseph has been a member of the Device Physics subcommittee for the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) since 1997.

Seshadri Subbanna received the Ph.D. degree in electrical engineering and materials science from the University of California, Santa Barbara. Since joining IBM, East Fishkill, NY, he has held positions in base technology development, 0.22 m CMOS and SRAM technology development. Currently he is the manager of Silicon–germanium BICMOS technology development.

Alan M. Victor (M’80) was born in 1948 in New York City. He received the B.S. degree in electrical engineering from the University of Florida, Gainesville, in 1971 and the M.S.E. degree in electrical engineering from the Florida Atlantic University, Boca Raton, in 1980. From 1971 to 1986, he was with with the Motorola Communications Division and a member of the Motorola Science Advisory Board. Since 1986, he provided consulting to the wireless industry with emphasis in the auto identification field. He joined the IBM Silicon–Germanium Applications Group at Research Triangle Park, NC, in 1997. He has seven patents in the area of communication circuits and systems. His responsibilities include the characterization, design, and application of SiGe circuits for wireless products. His current interest is design and synthesis of broadband RF circuits. Mr. Victor is a senior member of the Instrument Society of America.

Kimball M. Watson received the B.S. degree in electrical engineering from Worcester Polytechnic Institute, Worcester, MA, in 1969. He then joined IBM, Essex Junction, VT, and is presently an Advisory Engineer specializing in device and product reliability resting and analysis. He has been involved in product reliability prediction, line quality control, bipolar reliability, dielectric integrity, ionic mobility, and hot electron modeling. He has written a number of papers and holds a number of patents in reliability.

Charles S. Webster received the B.A. and M.S. degrees in physics from the University of Vermont, Burlington, in 1981 and 1985, respectively, and the M.S. degree in nuclear engineering sciences concentrating in radiological physics from the University of Florida, Gainesville, in 1995. He is with IBM Microelectronics in Burlington, VT, where he specializes in RF a characterization techniques in the RF/Analog Development Group.

Peter J. Zampardi received the B.E. degree in engineering physics from Stevens Institute of Technology, Hoboken, NJ, in 1986, the M.S. degree in applied physics from the California Institute of Technology, Pasadena, in 1988, and the Ph.D. degree from the University of California, Los Angeles, in 1997. While at Caltech, he performed photoluminescence studies to characterize MBE-grown GaAs and A1GaAs and to examine the use of tellurium clustering in ZnSe : Te for possible use in visible light emitters. From 1988 to 1999, he worked at Rockwell, where he was actively involved in development, modeling, and characterization of devices based on III–V HBT, MESFET, HEMT, BiGET, and RTD technologies. While at IBM, Essex Junction, VT, he was involved in the modeling and characterization of SiGe HBTs and devices for HF/Analog applications. He has authored or co-authored over 50 papers related to circuits and devices. He is now with Conexant Systems, Newbury Park, CA. Dr. Zampardi is currently a Chair of the Device Physics Committee, BCTM.