D converter

Analog Integrated Circuits and Signal Processing 2, 15%163 (1992) 9 1992 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

An 8-Bit Parasitic-Insensitive Switched-Capacitor A/D Converter MAHMOUD FAWZY WAGDY Department of Electrical Engineering, California State University, Long Beach, CA 90840 Received February 15, 1991; Revised September 5. 1991.

Abstract. An algorithmic A/D converter (ADC) is presented which employs switched capacitors. The ADC is insensitive to parasitic capacitances and op-amp offset voltages. Capacitor ratio-mismatch errors and charge injection errors are investigated. System level computer simulations are included to support the theory. The technique is suitable for 8-bit A/D conversion using present CMOS technology.

1. Introduction

Successive approximation algorithmic ADCs have received considerable attention [1]-[4]. Maloberti [1] proposed a parasitic-compensated ADC based on matching the parasitics of two equal capacitors. However, it is very difficult to control this matching. Li et al. [2] realized a 12-bit capacitor ratio-independent technique which requires a conversion time of 6n clock cycles for an n-bit ADC. Less integral nonlinearity (INL) could be obtained with a better offset cancellation technique. Onodera et al. [3] realized a capacitor ratio-independent ADC with a conversion time of 3n clock cycles. The ADC is a cyclic one, with an 8-bit accuracy. Song et al. [4] used a fully differential architecture to realize a E-bit capacitor error-averaging pipelined ADC, with a conversion time of 3n clock cycles. Section 2 presents another parasitic-insensitive ADC. The ADC is op-amp offset insensitive as shown in Section 3. Effects of capacitor ratio-mismatch errors are discussed in Section 4. Charge injection effects are discussed in Section 5. For both Sections 4 and 5 computer simulations for the ADC algorithm were performed using Vax Fortran, and some results are plotted using Matrix-X. 2. The New ADC

2.1. Algorithm The ADC employs a reference processing unit (RPU) as in [5], which keeps dividing the reference voltage VR(O) by 2. This division takes place n times for an n-bit ADC; i.e.,

1

Vn(i) = ~ VR(i - 1),

i = 1, . . . , n

(1)

where VR(O) is set to the maximum allowed amplitude of the input signal, Vin. The second major component of the ADC is the integrator. Its output Vg is changed, and each ADC bit b(i) is decided via a comparator, as follows:

Vg(i) = Vg(i - 1) + ( - 1 ) 1-b(/-1) VR(i)

(2)

where if Vm > Vg(i)

b(i)

=

"-~0

b(O) =

1

(initial value)

Vg(O) =

0

(preset value)

if Vm < Vg(i)

(3)

2.2. Circuit Diagram The analog circuitry of the ADC is shown in figure 1. Op amp 1 and its associated switched capacitors constitute the RPU. Op amp 2 and its associated switched capacitors constitute a noninverting/inverting integrator. Components $3 and C2 pertain to both the RPU and the integrator. Op amp 3 is the comparator. In actual circuit implementation a sample-and-hold circuit is required for the input signal. Also, since both inputs to the comparator are varying, it should have a rail-to-rail common-mode range. In figure 1 it is obvious that all capacitor terminations are connected to ground, op amp outputs, and virtual grounds, i.e., low-impedance nodes. Consequently, the ADC is parasitic insensitive.

158

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lS.tlqt_.

v,(o)

83~02/ ,

-

Via Fig. 1. ADC analog circuit,

2.3. Timing D i a g r a m

Figure 2 shows the timing diagram of the ADC. For an n-bit ADC the conversion time is 3n clock cycles. The clock is two-phase with two nonoverlapping pulses. During the first three clock cycles, which pertain to the most significant bit b(1), $1 closes and the initial value b(0) = 1 is used. Timing of the remaining ADC bits b(i), i = 2 . . . . . n, is automatically repeated. The dashed pulses in figure 2 show the states of $6 and $3 while ~1 and ~b2 are high. Switch $6 is closed before $3 if b(i - 1) = 1, and the opposite is true if b(i - 1) =

0.

When ~b2 is high, the sum of charges on the same capacitors is

During the first phase of clock cycle 1 (CK1) the sum of charges stored at the high-impedance side (sensitive side) of C1 and C2 is VR(i - 1)] + C2Vos,

(4)

During the second phase of CK1 the sum of charges of the two parallel capacitors C1 and C2 is L~c,,c2 = (C1 + C2) [Vos, - VR(i)]

(5)

Since the charge is conserved on C1 and C2, after charge redistribution, then (4) and (5) are equated to give VR(i) = VR(i -- 1)

During the first phase of clock cycle 2 (CK2) C2 is completely discharged. During the second phase of CK2 and the first phase of CK3 there are two possible scenarios, depending on b(i - 1) being 1 or 0. When b(i - 1) = 1, the sum of charges on C and C2 at the virtual ground of op amp 2, when 4>a is high, is given by

(7)

3.1. Offset o f Op A m p s 1 (Vos,)

[Vos , --

3.2. Offset o f Op A m p 2 (Vo&)

a ~C2 ' + a~c' = C2 [Vos2 - VR(i)] + C[Vos2 - Vg(i - 1)]

3. Cancellation of Op-Amp Offset Effects

Qlc, + Qlc~ = C 1

This voltage division is obviously independent of Vo&. It only depends on the accuracy of matching between C1 and C2.

C~

C~ +C2

(6)

c = C2(Vo& - O) + C[Vo& - Vg(i)] (8) Q~c'~ + Q~

Note that C' is not mentioned in (7) and (8) since it is not connected to the virtual ground during ~bz. As mentioned in [1], C' is a slave capacitor used to limit the slewing of the op amp. Now, by equating (7) and (8), we get Vg(i) = Vg(i -

G VR(i) 1) + --~

(9)

When b(i - 1) = 0, the sum of charges on C2, C, and C' at the virtual ground, when ~bI is high, is Q+c'~ + Q*c' + QOc; = C2Vo& + CtVos2 - C'Vg(i - 1)

Vg(i -

1)1 (10)

An 8-Bit Parasitic-Insensitive Switched-Capacitor A/D Converter

159

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Fig. 2. A D C timing diagram.

When ~2 is high, the sum of charges on the same capacitors is QOc~ +aCc 2 + Qo2 c , = C2[Vo& VR(i)] + C[Vo& - Vg(i)] - C'Vg(i - 1)

Equations (9) and (12) illustrate that Vo& has no effect on the integrator output.

-

(11) 3.3. Offset o f Op A m p 3 (Vo&)

By equating (10) and (11), we get Vg(i) = Vg(i - 1) - --C C2 VR(i)

(12)

The switched capacitors associated with the comparator, as shown in figure 1, add the well-known

160

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autozero capability [6]. Consequently, the effect of Vos 3 on the ADC performance will be completely eliminated.

4. Effect of Capacitor Ratio-Mismatch Errors

5. Effect of Charge Injection When an MOS switch is turned off, the charge stored in its channel is injected into the surrounding nodes and presumably split into two halves. The charge injected into one node is given by [2]

The reference voltage division of (1) is accomplished via the RPU employing C1 and Cz thus

Qinj -

Cox (Va - It) + ~ 5 Vs 2

(21)

where VR(i)

-

C1

C1 -F C 2

VR(i -

1),

i = 1,

"

.

"'

n

(13)

Assuming C2 = BC1,

B = 1 + e

(14)

where e is the capacitor ratio-mismatch error, typically about 0.05 % (i.e., 0.0005) to 0.1% (i.e., 0.001) for available MOS technology, then Vie(i) -

vR(i -

1)

(15)

I+B As for the integrator, assuming a = 1 + ee,

C = aC~,

- 1 _< e _< 1

(16)

1) + ( - 1 ) l-b('-1) B VR(i)

(17)

then (2) is rewritten as Vg = V g ( i -

a

When V.m is converted to digital, Va, the maximum conversion error for this ADC does not occur when all bits are ones. Using

1

(1 +

B) i

_ 1 I1 _ 2 ~'__. --1 (1 - i 2 ~ 2i

2i

(18)

it can be shown that the maximum error for an 8-bit ADC occurs when e = -1, b(1) = b(2) = 1, b(i) = O, i = 4, . . . , 7 (19)

Cox = transistor gate capacitance Va = gate voltage, V t = threshold voltage Vs = source or drain voltage The first component of (21) is called the charge injection offset, and the second is the signal-dependent charge injection. In order to study the response of the circuit of figure 1 to charge injection alone, let C, Ca, and C2 be equal. Now, let Qmjk denote the charge injection due to switch K. The timing diagram of figure 2 is then traced phase by phase, and the same approach used in [3] is followed. At the beginning of the MSB phase 3 (i.e., phase 1 of CK2), it can be shown that Vref(1) :

-

2

1 2

gref(0) -

C

[Vref(0) - Vp2] - Ve4

(22)

where Vpk denotes the offset (pedestal) voltage due to switch K, and is Cox (Va - Vt)

Vpk -

(23)

2C

During the MSB phase 5 (i.e., phase 1 of CK3), it can be shown that Vg(1) = Vref(1) + Vplo - (Vp8 + Vp9 + Vp11) (24)

From (3), it is interesting to note that Vg(8) is the input transition level. Using (17), (18), and (19) it can be shown that the maximum integral nonlinearity is INL(max) = 0.285e

As for b(i), i = 2, . . . , n, the circuit is different from the MSB case (i.e., i = 1). At the beginning of phase 3, it can be shown that

(20)

Computer simulations, for e -- 0.001 and E = -1, are shown in figure 3. INL(max) occurs at I'd = 193 through 196 and 225 through 228, which perfectly agrees with (19). The plot shows INL(max) = 0.29A instead of 0.285A, where A is the quantizing step size. The small discrepancy is due to incrementing V.m in steps of 0.01A and not 0.001A during the simulation.

1

Vref(i ) = 2 [Vref(i -

1)

+ V / , 5 ( i - 1) - V p 2 - Vp8]

-

Vp4

(25)

with

V:5 (i- I) =

Vp5

I1 v,o,(i1)-] ~: --,7 VG

vt

d

(26)

An 8-Bit Parasitic-Insensitive Switched-Capacitor A/D Converter

161

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INL (LSB)

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OUTPUT CODE Fig. 3. INL due to capacitor ratio-mismatch errors (e = 0.001). where Vref(i - 1) represents V s of (21). Now let V6 -

(27)

V t = h Vref(O)

With h = 1 for simplicity, which is a reasonable assumption, (26) becomes V~5(i-

1)-- Vp5 I 1 -- Vref(i-1) Ef~-~) 1

(28)

During phase 5, it can be shown that gg(i) = gg(i - 1) d- (--1)l-b(i-1)Vref(i) -]- V~12 -- (gp7 "}- Vp8 "]- Vpll)

(29)

where Vpl2(i-

1) = Vpl 2 F1 -

h

Vg(i-

1)~

Vref(0) A

(30)

Note that only switches 5 and 12 give rise to an additional signal-dependent charge injection component, as illustrated by the second term of (21). Two cases for an 8-bit ADC were investigated via computer simulations. In the first case, all switches were assumed identical and Vpk = Ve = -0.025A. This choice of Vp fulfills cVref(O) - 104 Qinj

which is achievable in present CMOS technology. Figure 4 show INL versus the ADC output. In the second case, switches 5 and 10 were chosen to be four times bigger (i.e., Vp5 = Vplo = 4Vp), whereas switch 12 was chosen to be six times bigger (i.e., Vp12 = 6Vp). The purpose is to partially cancel charge injection effects in (24), (25), and (29). The INL of figure 5 obviously represents an improvement over that of figure 4. For more clock feedthrough cancellation, the technique by Martin [7] can be used. It simply employs switched-capacitor sections connected to the op amp's noninverting inputs, which are functionally similar to what is connected to the op amp's inverting inputs9 More switches are required in this case.

5. Conclusions A new switched-capacitor, successive approximation ADC has been proposed and investigated. The circuit employs a reference processing unit, an integrator, and an autozeroed comparator. The circuit is insensitive to offset voltages of the op amps employed. It is also insensitive to parasitic capacitors. The effects of capacitor ratio-mismatch errors have been investigated mathematically and via simulations. Effects of charge injection

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(LSB) .H

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1ZB

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Z56

OUTPUTCODE Fig. 4. I N L

due to charge injection of switches

(Vp ---

-0.025A).

.E

.H

INL

(LSB)

-.2

-.t

U

6H

t ZB

1 tZ

OUTPUTCODE Fig. 5. INL due to charge injection for different sizes of switches (Vp = -0.025A).

ZSI;

An 8-Bit Parasitic-Insensitive Switched-Capacitor A/D Converter

163

of switches have also been investigated and assessed via computer simulations. The circuit is suitable as an 8-bit ADC.

References 1. E Maloberti, "Switched-capacitor building blocks for analogue signal processing," Electron. Lett., vol. 19, no. 7, pp. 263-265, 1983. 2. P.W. Li, M.J. Chin, P.R. Gary, and R. Castello, ' ~ ratioindependent algorithmic analog-to-digital conversion technique,' IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 828-836, 1984. 3. H. Onodera, T. Tateishi, and K. Tamaru, '~A Cyclic A/D Converter that Does Not Require Ratio-Mismatched Components," IEEEJ. Solid-State Circuits, vol. 23, no. 1, pp. 152-158, 1988. 4. B.S. Song, M.F. Tempsett, and K.R. Lakshmikumar, ' ~ E-bit 1-Msample/s capacitor error-averaging pipelined A/D converter," IEEEJ. Solid-State Circuits, vol. 23, no. 6, pp. 1324-1333, 1988. 5. K. Chen and C. Svensson, '~. parallel A/D converter array structure with common reference processing unit," IEEE Trans. Circuits Systems, vol. 36, no. 8, pp. 1116-1119, 1989. 6. R. Gregorian and G. Temes, Analog MOS Integrated Orcuits for Signal Processing, Wiley: New York, 1986. 7. K. Martin, "New clock feedthrough cancellation technique for analogue MOS switched-capacitor circuits" Electron. Leg., vol. 18, no. 1, pp. 39-40, 1982.

Mahmoud FawzyWagdywas born in Egypt in 1950. He received the B.Sc. and M.Sc. degrees from Cairo University, Egypt, in 1973 and 1977, respectively, and the Ph.D. degree from Kansas State University, Manhattan, KS in 1983. He worked from 1973 to 1976 in the Electronic Industries Research and Development Center in Cairo. From 1977 to 1979 he worked in the Arab Organization for Industrialization in Cairo. During that time he spent four months at Thomson-csfin France. From 1979 to 1983 he was a teaching assistant at Kansas State University. He has worked in Massachusetts as assistant professor of electrical engineering from 1983 to 1986 at Northeastern University in Boston, then from 1987 to 1989 at the University of Lowell. He spent the summer of 1987 with Analog Devices Semiconductor at Wilmington, MA. Since fall 1989, he has been an associate professor of electrical engineering at California State University, Long Beach, CA. Throughout his career he has taught a wide variety of courses in analog/digital electronics, analog electronics for signal processing, circmt theory, signal analysis, probability and statistics, computer engineering, and microprocessor applications. He started his research career with active-R filters, then computer-based vector impedance and phase measurements. His current research interest is analog-to-digital converters which involves quantization, dithering, and switched-capacitor circuit techniques. He has about 30 publications in well-knownjournals and conferences. He won the 1989 best paper award of the IEEE Transactions on Instrumentation and Measurement.