D Converter

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Simple 3-Bit Flash ADC. ADCs are characterized by differential nonlinearity. (DNL) and integral nonlinearity (INL) [1]. Input capacitive loading results from having ...
A 2-GSPS 4-Bit Flash A/D Converter Using Multiple Track/Hold Amplifiers By

Dr. Mahmoud Fawzy Wagdy, Professor And

Chun-Shou (Charlie) Huang, MSEE Department of Electrical Engineering, California State University, Long Beach, CA 90840, U.S.A. ABSTRACT - Flash A/D converters (ADCs) play an important role in many applications, such as radar systems, aerospace applications, etc. A typical flash ADC includes only one track/hold amplifier (THA), however, in this paper a multi-THA topology is presented and investigated, where one THA is connected to every comparator. A comparative study is performed employing a 4-Bit ADC; this includes measuring the integral nonlinearity (INL) for both architectures at different frequencies. Behavioral modeling using Verilog-A is used to quantify the accuracy of the circuits. The ADCs under consideration were implemented using Cadence 0.18µm CMOS process.

of comparators connected to Vin, i.e. a large capacitive load at the input of the track/hold amplifier (THA), thus limiting the ADC speed. For Vref =1V and and a 4-bit ADC, the quantizing step size (1LSB) is 62.5mV. A severe limitation in very high-speed converters is meta-stability [2], which is caused by the finite gain in the comparators. Therefore, it is common to use comparators with a pre-amplifier followed by a regenerative latch. II. FLASH ADC COMPONENT DESIGNS 1. Track-and-Hold Amplifier (THA) The function of the THA is to sample an analog input signal and hold the sample value over a certain length of time for subsequent processing. 1.1. Circuit Operation and Design Values: Fig. 2 shows the schematic of the THA circuit [3]. Design parameters of the transistors M1, M2, M3, and M4 are given in Table 1 below.

I. INTRODUCTION The flash ADC architecture is the fastest one of all ADCs. An n-bit flash ADC consists of 2n-1 comparators. A simple 3-bit flash ADC is shown in Fig. 1. Conversion speed is limited by the sampler (THA) frequency response and the comparators’ input capacitances. Since many comparators are required, ADCs with resolutions higher than 8 bits rarely use the flash architecture.

Fig. 2. Schematic of the THA M1

M2

M3

M4

Vbias

Vdd

W=100µ

W=50μ

W=50μ

W=100μ

1.4V

1.8V

Fig. 1. Simple 3-Bit Flash ADC

Table1. THA Design Values ( with 0.18µm lengths)

ADCs are characterized by differential nonlinearity (DNL) and integral nonlinearity (INL) [1]. Input capacitive loading results from having a large number

1.2. Output Waveforms for an AC Input: Simulations were performed for the THA at various frequencies. Fig. 3 shows the response to a 1GHz sinusoidal input with a 2GHz clock. 1

Fig. 5. Frequency Response of the THA

η

Fig. 3. Simulation Result of THA (Fin=1GHz, Fclk=2GHz) 1.3. Output Waveforms for a DC Input: In order to test the THA accuracy, a DC input is applied. Various DC inputs of 0.3V, -0.3V, 0.9V, and -0.9V were applied with clock frequencies of 10MHZ, 100MHz, and 1GHz. Fig. 4 shows the response to a 0.9V dc input at a 1GHz clock frequency.

η2 Fig. 6. The Proposed Comparator Circuit [4] M1

10μ

M8

50μ

M15

30μ

M22

30μ

M2

10μ

M9

50μ

M16

30μ

M23

10μ

M3

10μ

M10

160μ

M17

10μ

R1

200K

Fig. 4. Simulation Result of THA (DC Input = 0.9V, Fclk=1GHz)

M4

10μ

M11

150μ

M18

10μ

R2

200K

M5

160μ

M12

150μ

M19

20μ

RT

1.5K

1.4. Frequency Response of the THA in the Track Mode: The2 THA must meet the accuracy requirement of ADC, i.e. < 0.5LSB. In a 4-bit flash ADC, the error is (1) < 0.5 (2-4), i.e.