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Abstract—This paper discusses a new DC/DC conversion tech- nique for boosting very low voltage (100 mV) to 650 mV, which is the typical supply voltage for ...

Proceedings of 2014 RAECS UIET Panjab University Chandigarh, 06 - 08 March, 2014

CNFET-Based 0.1 V to 0.6 V DC/DC Converter Aditya Tyagi, Ch Gopi, Prayank Baldi, Vikash Kumar and Aminul Islam Department of Electronics and Communication Engineering Birla Institute of Technology, Mesra Ranchi, Jharkhand, India [email protected], gopi [email protected], [email protected] Abstract—This paper discusses a new DC/DC conversion technique for boosting very low voltage (100 mV) to 650 mV, which is the typical supply voltage for operating circuits in near-threshold and subthreshold region. The converter uses Carbon Nanotube Field Effect Transistors (CNFETs) in a hybrid inductive and capacitive circuit. The converter can boost 100 mV to 650 mV and hence is suitable for low power applications. Keywords—Charge Pump, Energy Harvesting, CNFET, DC/DC Converter.

I.

I NTRODUCTION

The last decade has witnessed tremendous growth in the mobile and handheld portable devices. Most of these devices are battery powered for portability and mobility. Batteries constitute a bulk of these devices weight and dimensions. Batteries run out quickly in most handheld devices. This is especially true if the user is on the move and has no time to charge the battery. The thirst for battery power in new smartphones and tablets is far outpacing improvements in battery technology. Switching to new technologies like 4G is only going to exacerbate the problem. Battery makers are trying to wring the last bits of capacity out of 15-year-old lithium ion technology. It is clear that in near future, one of the limiting factors in the adoption of mobile devices will be the insufficient battery performance of these devices and the frequent charging requirements. This will especially be an issue in areas having an unreliable supply of conventional energy sources. About 1.4 billion people are off-grid or lack access to electricity; the vast majority (85%) lives in rural parts of the developing world. These settings are far from the national electrical grids making charging handset batteries difficult. Though there is an ongoing effort to reduce consumption of power and increase battery life for mobile devices, it may not be able to match the current trend in increase in power consumption. This stresses on the need to develop alternate methods to source energy from nonconventional sources which are fully autonomous and can be integrated in portable devices. Energy is everywhere in the environment surrounding us – available in the form of thermal energy (temperature differential), light (solar) energy, wind energy, mechanical energy (vibrations) and RF energy. However, the energy from these sources is often found in such minute quantities that it cannot supply adequate power for any viable purpose. In fact, until recently, it has not been possible to capture such energy sufficiently to perform any useful work. This has changed recently with the advent of ultralow power architectures that can harvest energy from these sources and convert it into useful form. c 978-1-4799-2291-8/14/$31.00 2014 IEEE

Energy Harvesting is a technique to scavenge power from external sources (solar power, thermal energy, kinetic energy, RF energy, etc.) which are low quality and cannot be used as such to power any commercial devices. Energy Harvesting aims to convert energy from these low quality sources into usable form for driving low power circuits and systems in the near-threshold and sub-threshold regions. The NearThreshold Computing (NTC) is a region of operation of the device in which the circuit retains much of the energy savings of subthreshold operation with substantial performance improvement. The present power consumption problem in the semiconductor industry for mobile platform and stagnated voltage scaling is shifting the mindset of researchers from superthreshold to subthreshold and back to near-threshold for achieving reasonable performance at low energy level. The circuits and systems, operated in these regions, because of their low power requirements, can be powered by energy harvesting systems. Such energy harvesting systems provide a promising alternative to battery-powered systems and create opportunities for architecture and design innovation for the exploitation of an ambient energy source. Many attractive applications of this technique have been investigated such as thermo-electric generators, biomechanical wrist watches and smart sensors. One of the hindrances in employment of such a technique is the low quality of power delivered by such source which is unreliable and generally unusable for any of the above mentioned applications. This requires effective conversion or boosting of low power to suitable levels so that it can be used for commercial devices. Several architecture of low power DC/DC converters are available in [1]–[13] that use low threshold voltage MOS for the design but due to high losses and low conductivity, it is difficult to operate them at voltages lower than 300 mV. Authors in [1], proposed a DC/DC converter, which can boost an input voltage of 200 mV to 1.2 V with an efficiency of 36%. In [2], a 90-nm CMOS based charge pump was proposed which can boost 300 mV RF signals to 1 V producing an output power of 60 µW. Many other circuits which work at input voltages less than 100 mV have also been proposed but require external start-up voltages as high as 650 mV [8] or a mechanical switch [3]. Significant research work has already been carried out in the applications of Carbon Nanotubes based transistors [14]– [21]. Carbon Nanotubes promise to be the next disruptive technology in the field of solid state devices, overcoming the limitations of tradition silicon based designs and extending the growth of electronics industry as predicted by Moore’s Law for years to come. This paper presents a new architecture based

on carbon nanotubes for designing a DC/DC converter. It is to be noted that to the best of our knowledge, no previous work has been reported in the literature on the performance of a CNFET-based DC converter. This paper makes the following contributions: 1)

2)

In view of the above limitations of the aforementioned architectures to operate in ultralow power range, a CNFET based design is proposed that is capable of working at extremely low voltages and offer appreciable boosting to ultralow input voltages. The performance of CNFET based design is evaluated for the first time and suitability of Carbon Nanotubes for energy harvesting applications is presented.

(a) Top view

The rest of the paper is organized as follows. Section II provides an introduction to Carbon Nanotubes based Field Effect Transistors (CNFETs). Section III discusses the proposed architecture and establishes the various parameters of operation. Section IV presents the results and discussion arrived at by extensive simulations. Section V concludes the paper and discusses the future course of action in refining this work.

II.

C ARBON NANOTUBE F IELD E FFECT T RANSISTORS

The past few years witnessed a dramatic increase in nanotechnology research, especially in the nanoelectronics field. Among the nanoelectronic devices investigated till date, CNFET seems to have the brightest prospect as per its better electronic characteristics. Speed enhancement due to scaling down to 16-nm and 10-nm technology node has given the impetus to its use. Leakage current, high field effect, short channel effect and lithographic limit problems associated with MOSFET are largely taken care of in CNFET [14]–[19]. Also fabrication related issues of CNFET have been solved and hence CNFET-based circuit will surely dominate in the industry in future [20]. CNFET is produced by replacing the channel of a conventional MOSFET by an array of semiconducting carbon nanotubes (CNTs) as shown in Fig. 1. CNT is basically a long, thin allotropic carbon tube which provides a single path between source and drain. CNTs are sheets of graphite rolled into hollow cylinders of diameters varying from 0.4 nm to 4 nm. Depending on the direction in which they are rolled (called chirality) a CNT can be semiconducting with distinct bandgap or it can be metallic with no bandgap. The resulting structure is called single-walled carbon nanotube (SWCNT). If several SWCNTs with varying diameter are rolled concentrically inside one another, then the resulting structure is called multi-walled carbon nanotube (MWCNT), its diameter ranging from several nm to tens of nm [14]–[19]. An SWCNT can work as semiconducting or metallic depending on its chirality (n1 , n2 ), the direction in which it is rolled up. The CNT acts as metal if n1 = n2 or n1 − n2 = 3i, where i is an integer. Otherwise, CNT works as semiconductor. The threshold voltage (Vth ) of CNFET is approximated to the first order as half the band gap (Vth ' Eg /2q). Vth is an inverse function of diameter. CNT diameter (DCN T ) and threshold voltage calculations depend on the Chirality (n1 , n2 )

(b) Cross-sectional view

Fig. 1: Carbon nanotube field effect transistor [21] given by following design equations: √ Ch = a n1 + n2 + n1 n2 Ch DCN T = π aVπ √ Vth ' Eg /2q = qDCN T 3

(1) (2) (3)

where Eg is energy gap, q is electronic charge, Vπ = 3.033 eV is the√carbon π–to–π bond energy in the tight bonding model, ˚ is the lattice constant(where d = 1.44 A ˚ is a = 3d = 2.49 A the inter-carbon-atom distance)[14]–[19]. CNFET working principle is similar to that of conventional MOSFET but it has advantage over MOSFET, as it offers higher mobility of charge carriers. This is on account of ballistic transport of electrons across the CNFET. Ballistic transport means that the mean free path for a charge carrier is longer than the device dimensions and hence charge carriers do not collide during their travel from source to drain due to higher mean free path. This leads to higher mobility of carriers in CNFET than in MOSFET. It provides ample space for the improvement of the performance of the CNFET-based circuit such as ultralow threshold voltage for switching and higher drive current than MOSFETs, which have been effectively utilized in this work. III.

P ROPOSED DC/DC C ONVERTER A RCHITECTURE

Various architectures have been proposed earlier for DC/DC conversion. These have been extensively studied in literature [1]–[13] and have their respective advantages and limitations put forward. The design choice is influenced

Fig. 2: Stage I: Block diagram of timing circuit. by factors such as voltage conversion ratio range, the maximal output power, power conversion efficiency, number of components, power density etc. In this work, we have explored inductor based switched mode converters supplemented by capacitive charge pumps. The proposed converter is a three stage circuit which is powered by energy scavenged from low power external sources (80 − 200 mV) e.g. thermophiles. Stage I is a timing circuit which consists of a ring oscillator based clock generator (see Fig. 2). The ring oscillator is essentially a series of 7 to 11 inverters which produce a square wave of frequency of ∼ 1.6 MHz. This clock signal is then fed to a buffer device which decreases the rise and fall time of the pulses. This is necessary as the switched mode converters produce best results when switched with nearly perfect clock cycles. The sanitized square wave is then fed to frequency divider circuit so as to obtain appropriate frequency to drive subsequent stages. This digital circuit is made up of a series of flip flops and NAND gates to produce the required duty cycle of 75%. The duty cycle is chosen to maximize the gain: a large duty cycle forces a large current through the inductors and leads to large output voltages. On the other hand, more current through the switches leads to high power consumption. Hence, a trade-off is made after optimizing the duty cycle to 75%. The next stage of operation is a 4-stage Dickson’s charge pump (see Fig. 3) [6]. Dickson’s charge pump is fairly easy to fabricate and simple in operation. The 10 kHz signal is used for pumping the charge across the diode connected transistors. After N stages, the output of the charge pump is found out to be [6] Vout = Vin + N × (VClk − Vth ) − Vt .

(4)

This output of the charge pump is used to supply an inverter which inverts the 100 kHz wave, thereby almost doubling its amplitude (∼ 170 mV). This 100 kHz clock signal (Clkin) is subsequently used to drive the switched mode converter which is implemented in stage III of operation. Note that the supply VDD in this case comes from the 100 mV input to the circuit. Stage III is shown in Fig. 4. This stage is essentially an inductor based step-up converter. An NCNFET is rapidly switched ON and OFF using the 100 kHz Clkin signal with a duty cycle of 75%. During the ON time of NCNFET, a current is established through the inductor whose maximum value is given by VDD × TON (5) L where VDD is the supply voltage (assumed to be 100 mV) and L is the size of inductor in µH. When the transistor is switched off, the current cannot die instantaneously and a large voltage spike occurs across the inductor given by ILmax =

Vo (t) = VDD + L

di dt

(6)

Fig. 3: Stage II: Clock boosting.

Fig. 4: Stage III: Step-up converter.

This emf forces the current to flow through the diode and the load. A capacitor is placed in parallel to the load to smooth out the ripples. If the duty cycle of clock pulse supplied for switching the transistor is D and the converter is assumed to be lossless, then the output voltage Vo can be rewritten as VDD (7) 1−D It can be seen that as the inductance is increased, ILmax decreases but Vo increases. Also the size of inductor is one of the factors that determine the size of overall circuit as large inductors tend to be bulky external SMD devices. Hence, a compromise needs to be made in choosing the value of L. Optimum value of L is found to be in the range of 37 − 50 µH for the proposed circuit. If the transistors are properly switched for discontinuous mode, it can be shown that with TON as time during which CNFET conducts and diode is off and TOF F being the time during which the CNFET is off and diode conducts due to voltage spike, the output voltage is given by   TON × VDD (8) Vo = 1 + TOF F Vo =

IV.

P ERFORMANCE A NALYSIS

This Section presents estimation of various design metrics which are estimated during simulation on HSPICE using the experimentally validated Stanford CNFET model [18]. The CNFET model has been calibrated to 90% accuracy with experimental data (ac and dc characteristics) from fabricated CNFET circuits [19]. Supply voltage VDD of Stage II is 100 mV and it is also fed by clock signals Clk1(100 kHz) and Clk2(10 kHz). Fig. 5 shows the input signal i.e. Clk1 and output signal Clkin of stage II. The output clock signal Clkin of stage II is then used to feed stage III. The resulting output voltage from stage III across a load resistance of 10 kΩ as a function of time is shown in Fig. 6. The output voltage

TABLE I: P ERFORMANCE M ETRICS OF THE P ROPOSED DC/DC C ONVERTER

Fig. 5: Stage-I output: Clk1(bottom), stage-II output: Clkin(top).

Technology

Carbon Nanotube Field Effect Transistors

Input Voltage Switching Clock Frequency Output Voltage Efficiency Load Current Rise Time

100 mV 100 kHz 650 mV 27% 65 µA 3.8 ms

R EFERENCES [1]

[2] [3]

[4]

Fig. 6: Output voltage versus time.

[5]

saturates at 650 mV which is suitable for driving various nearand sub-threshold circuits and systems. Efficiency of the proposed DC/DC converter is calculated with load resistance R = 10 kΩ using the following formula: ILoad × VLoad η= IVDD × VDD

(9)

The results obtained are promising and efficiency of 27% has been obtained for the aforementioned loading. The rise time of the output has been observed to be 3.8 ms. Various performance metrics of the proposed DC/DC converter are reported in Table I. V.

[6]

[7] [8]

[9]

[10]

C ONCLUSION

This paper explores the application of CNFETs for designing an energy harvesting system without compromising on complexity and performance. The overall design and performance analysis clearly indicates that Carbon Nanotubes have a promising future in such power scavenging systems and can provide a better alternative to CMOS based designs. This converter is the starting point toward the energy efficient and high output voltage design for sourcing circuits in superthreshold application. Further investigation in this direction are already under consideration. Efforts are also being made to optimize the design and improve its efficiency.

[11] [12]

[13]

[14]

[15]

A. Richelli, L. Colalongo, S. Tonoli, and Z. Kovacs-Vajna, “A 0.2 1.2 V dc/dc boost converter for power harvesting applications,” IEEE Transactions on Power Electronics, vol. 24, no. 6, pp. 1541–1546, June 2009. T. Halvorsen, H. Hjortland, and T. Lande, “Power harvesting circuits in 90 nm CMOS,” in NORCHIP, 2008., Nov 2008, pp. 154–157. Y. Ramadass and A. Chandrakasan, “A batteryless thermoelectric energy-harvesting interface circuit with 35–mV startup voltage,” in Digest of Technical Papers of IEEE International Solid-State Circuits Conference (ISSCC), 2010, Feb 2010, pp. 486–487. A. Bertacchini, S. Scorcioni, M. Cori, L. Larcher, and P. Pavan, “250 mV input boost converter for low power applications,” in IEEE International Symposium on Industrial Electronics (ISIE), 2010, July 2010, pp. 533–538. A. Richelli, L. Colalongo, M. Quarantelli, M. Carmina, and Z. M. Kovacs-Vajna, “A fully integrated inductor-based 1.8-6 V step-up converter,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 242– 245, Jan 2004. J. Dickson, “On-chip high-voltage generation in mnos integrated circuits using an improved voltage multiplier technique,” IEEE Journal of SolidState Circuits, vol. 11, no. 3, pp. 374–378, Jun 1976. B. Williams, “Basic dc-to-dc converters,” IEEE Transactions on Power Electronics, vol. 23, no. 1, pp. 387–401, Jan 2008. E. Carlson, K. Strunz, and B. Otis, “A 20 mV input boost converter with efficient digital control for thermoelectric energy harvesting,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 741–750, April 2010. J. Kimball, T. Flowers, and P. Chapman, “Issues with low-inputvoltage boost converter design,” in IEEE 35th Annual Power Electronics Specialists Conference(PESC), 2004, vol. 3, June 2004, pp. 2152–2156. S.-L. Liu, J. Liu, H. Mao, and Y. qing Zhang, “Analysis of operating modes and output voltage ripple of boost DC-DC converters and its design considerations,” IEEE Transactions on Power Electronics, vol. 23, no. 4, pp. 1813–1821, July 2008. D. Grgi´c, T. Ungan, M. Kosti´c, and L. Reindl, “Ultra-low input voltage DC-DC converter for micro energy harvesting,” in Power MEMS, 2009. R. Vullers, R. van Schaijk, I. Doms, C. V. Hoof, and R. Mertens, “Micropower energy harvesting,” Solid-State Electronics, vol. 53, no. 7, pp. 684 – 693, 2009. J. Kimball, T. Flowers, and P. Chapman, “Low-input-voltage, low-power boost converter design issues,” IEEE Power Electronics Letters, vol. 2, no. 3, pp. 96–99, Sept 2004. X. Wang, Q. Li, J. Xie, Z. Jin, J. Wang, Y. Li, K. Jiang, and S. Fan, “Fabrication of ultralong and electrically uniform single-walled carbon nanotubes on clean substrates,” Nano Letters, vol. 9, no. 9, pp. 3137– 3141, 2009. J. Deng and H. Wong, “A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application-Part I: Model of the intrinsic channel region,” IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3186–3194, Dec 2007.

[16]

J. Deng and H. S. P. Wong, “A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application-Part II: Full device model and circuit performance benchmarking,” IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3195–3205, Dec 2007. [17] J. Deng and S. U. D. of Electrical Engineering, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors. Stanford University, 2007. [Online]. Available: http://books.google.co.in/books?id=kyblOwAACAAJ [18] Stanford University CNFET model. [Online]. Available: http://nano.stanford.edu/model.php?id=23

[19]

I. Amlani, J. Lewis, K. Lee, R. Zhang, J. Deng, and H. S. P. Wong, “First demonstration of AC gain from a single-walled carbon nanotube common-source amplifier,” in International Electron Devices Meeting(IEDM), 2006., Dec 2006, pp. 1–4. [20] F. Ali Usmani and M. Hasan, “Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach,” Microelectron. J., vol. 41, no. 7, pp. 395–402, Jul. 2010. [Online]. Available: http://dx.doi.org/10.1016/j.mejo.2010.04.011 [21] A. Imran, M. Hasan, A. Islam, and S. Abbasi, “Optimized design of a 32-nm cnfet-based low-power ultrawideband CCII,” IEEE Transactions on Nanotechnology, vol. 11, no. 6, pp. 1100–1109, Nov 2012.

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