DC Converter With a Full ZVS Range and Reduced

112

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

Soft-Switching DC/DC Converter With a Full ZVS Range and Reduced Output Filter for High-Voltage Applications Il-Oun Lee, Student Member, IEEE, and Gun-Woo Moon, Member, IEEE

Abstract—A new soft-switching dc/dc converter, which can solve the drawbacks of existing phase-shifted full-bridge converters such as narrow zero-voltage-switching (ZVS) range, large circulating current, large duty-cycle loss, and a large output filter in highvoltage applications, is proposed in this paper. The proposed converter is composed of two symmetric half-bridge inverters that are placed in parallel on the primary side and are driven in a phase-shifting manner to regulate the output voltage. At the rectifier stage, two full-bridge rectifiers sharing two low-current-rating diodes are employed. This structure allows the proposed converter to have the advantages of a full ZVS range, no problems related to duty-cycle loss, no circulating current, and a significantly reduced output filter. In this paper, the circuit configuration, operation principle, and relevant analysis results of the proposed converters are presented. Experimental results on a prototype converter realized with the specification of 80-in plasma display panel sustain power module (320–385 Vd c input, 205 Vd c /5 A output) validate the theoretical analysis. Index Terms—No circulating current, no duty-cycle loss, phaseshift, zero-voltage switching (ZVS).

I. INTRODUCTION HE traditional phase-shift full-bridge (PSFB) converter exhibits benefits in medium-to-high-power applications [1]: all primary switches are turned ON under zero-voltage switching (ZVS) without the help of any auxiliary circuits. The switches’ voltage stress is clamped to that of the input voltage. Hence, high-frequency MOSFETs are suitable as main switches for the converter, which can raise the power density of the converter. However, such a converter has several serious problems: first, the ZVS range of lagging-leg switches is very narrow under load variation. For this reason, its conversion efficiency is severely degraded as the load decreases [2]. If the converter is fit for a relatively wide input voltage range due to the design considerations such as the hold-up time requirement, the steady-state duty cycle becomes small and the freewheeling interval lengthens in normal operating conditions. Then, excessive circulating

T

Manuscript received January 27, 2012; revised March 22, 2012; accepted May 8, 2012. Date of current version September 11, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) under Grant 2012-0000981. Recommended for publication by Associate Editor S. K. Mazumder. The authors are with the School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2199520

current appears on the primary side during the freewheeling interval, increasing the primary-side conduction loss and the turn-off switching loss of the lagging-lag switches [3]. In addition, the small duty cycle has detrimental effects on converter performance, such as a large ripple current through the output inductor LO [4]. Especially, in high-output-voltage applications, a very large LO is required to reduce the large ripple current, which results in low power density and high cost. In order to overcome the problems of the traditional PSFB converter, many studies have been conducted. First, to remove the circulating current and reduce the large output inductor, the frequency-modulated FB converter was presented in [4]. The operating range of its switching frequency, however, is very widely changed in a wide-input-voltage range, which leads that it is difficult to design optimally the magnetic components and capacitors. In addition, the converter cannot achieve ZVS in a wide range of load variation. The ZVS range of lagging-leg switches in the traditional PSFB converter can be extended by making the leakage inductance of the transformer very large and/or adding an external resonant inductor with large inductance. However, this approach increases duty-cycle loss, which results in high secondary-voltage stress and primary-conduction losses. Another approach is to reduce the magnetizing inductance of the transformer to achieve a wide ZVS range. However, this significantly increases the RMS current stress and conduction losses on the primary side, because the additional current generated by reducing the magnetizing inductor circulates through all of the switches and transformer at its peak value. In addition, it still has the drawback of a large output inductor in high-outputvoltage applications. The PSFB converter in [5] uses a saturable reactor on the primary side to achieve a wide ZVS range and to reduce the circulating current. However, too much heat is generated on the saturable reactor, thus it becomes bulky. The PSFB converter in [6] uses a resonant inductor to extend the ZVS range of lagging-leg switches and needs two clamping diodes for easy reduction of the secondary-voltage overshoot and oscillation. However, the converter suffers from an increased loss in the duty cycle, and a severe reverse-recovery phenomenon is generated on the additional clamping diodes when there is a light load [7], [8]. In addition, its ZVS operation cannot still be achieved at a very light load and a large output inductor is still required. Many PSFB converters extending the ZVS range without the increase of duty-cycle loss were introduced in [9]–[13]. In the converters, however, the current stress of all the switches is higher than the traditional PSFB converter due to the assistant current source for a wide ZVS range, which leads to the increase

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LEE AND MOON: SOFT-SWITCHING DC/DC CONVERTER WITH A FULL ZVS RANGE AND REDUCED OUTPUT FILTER

in conduction loss. To minimize the increase of current stress, one or two bulky inductors and some coupled inductors with large inductance are additionally required. The PSFB converters with a current-doubler rectifier can also solve the problems. However, the current ripple of two output inductors must be designed to be very large for a wide ZVS range. This results in an increase of RMS current stress in the converters [14], [15]. In [16] and [17], the PSFB converters with two transformers were introduced. Due to the use of two transformers, the ZVS operation in the converters is achieved under entire load conditions. However, the dc bias currents equal to half the primaryreflected load current, which flows through the transformers, reduce the utilization of the transformers. The PSFB converters with ZVS and zero-current-switching (ZCS) operation can provide another solution to the problems. In these converters, leading-leg switches are turned ON with ZVS and lagging-leg switches are turned OFF with ZCS. Thus, MOSFETs as leadingleg switches and IGBTs as lagging-leg switches are generally employed. Because the ZVS operation of leading-leg switches is achieved by the same way as that of the traditional PSFB converter, its range is wide under load variation. Moreover, nearly constant efficiency can be obtained over a wide input voltage range because there is no circulating current in the converters. However, for ZCS operation and countermeasures to side effects such as high secondary-voltage stress and primary-current overshoot, they require many additional components, which results in high cost and a complex structure [18]–[21]. In addition, using IGBTs to suit ZCS operation precludes the use of high switching frequency to realize smaller magnetic components and capacitors [22]–[25]. Also, its large output inductor in high-voltage applications is an additional drawback. In [26] and [27], the PSFB converters with the ZVS capability in a wide load range and reduced output filter were presented, but the primary circulating current is still in the controlled full-bridge inverter. The PSFB converter introduced in [3] can always operate with a maximum duty cycle under all line conditions. This operation minimizes the circulating current and reduces the filter requirement. Yet, two additional main switches in the primary side increase the cost and circuit complexity. In this paper, a new soft-switching dc/dc converter with a full ZVS range and reduced output filter for high-voltage applications is proposed, as shown in Fig. 1. The proposed converter is composed of two symmetric half-bridge inverters (TSHBIs), leading-leg and lagging-leg SHBIs, which are placed in parallel on the primary side and are driven in a phase-shifting manner to regulate the output voltage. At the rectifier stage, two fullbridge rectifiers sharing two lower-current-rating diodes compared with the main rectifier diodes are employed, because a full-bridge rectifier features low voltage stress in high-voltage applications. This structure allows that the proposed converter has the following advantages: 1) All the switches is turned ON with ZVS under entire load conditions without any additional large resonant inductors or circuits, while the conduction loss caused by the assistant current source extending the ZVS range is minimized due to its reduced conduction path.

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Fig. 1. Circuit diagram of proposed phase-shifted pulsewidth modulation converter.

2) The circulating current in existing PSFB converters does not appear in the proposed converter, which contributes to the improvement in the conduction loss. 3) The proposed converter has no problems related to an increase of duty-cycle loss. In addition, the conversion ratio is higher than that of existing PSFB converters. These allow that the turns ratio of the transformers is designed to be better than that of the counterparts. Thus, the voltage stress across the diode rectifier and the load current reflected to the primary side can be reduced, which leads to the improvement in the conduction loss. 4) There is always an input voltage source in the waveform seen by the output LC filter. Thus, the value of output inductor is significantly reduced [26], [27]. 5) A low profile design becomes a possibility due to the use of two small-sized transformers with low height instead of a large-sized transformer with high height. This results in a slim power supply. The operation principle of the proposed converter is presented in Section II. The relevant analysis results are given in Section III. The performance of the proposed converter is confirmed by the experimental results of a prototype converter realized with the specification of an 80-in plasma display panel (PDP) sustain power module (320–385 Vdc input, 205 Vdc /5 A output) in Section IV. The conclusion is made in Section V. II. OPERATION PRINCIPLE Figs. 2 and 3 show the current and voltage notations and key operating waveforms of the proposed converter in the steady state, respectively. All the switches are driven with a constant duty ratio (D = 0.5), ignoring the dead time Tdead . The driving signals of the switches in the leading-leg SHBI lead that of the switches in the lagging-leg SHBI. Here, we call the switches in the leading-leg or lagging-leg SHBIs leading-leg or lagging-leg

114

Fig. 2.


Current and voltage notations in the proposed converter.

switches, respectively. TSHBIs are run by adjusting the phaseshifted time TΦ to regulate the output voltage. Each switching period is divided into two half cycles, t0 –t8 and t8 –t16 . Because the operational principles of two half cycles are symmetric, only the first half cycle is described. This half cycle can be subdivided into eight modes, whose operating circuits are shown in Fig. 4. In order to illustrate the operation of the proposed converter, several assumptions are made: 1) the output inductor LO is large enough to be considered as a constant current source during a switching period; 2) the blocking capacitor CB is large enough to be considered as a constant voltage source of VIN /2; 3) the output capacitor CO is large enough to be considered as a constant voltage source of VO ; 4) the magnetizing inductance Lm 2 of the transformer T2 is large enough to ignore the effect of the magnetizing current during a switching period; 5) the main switches are all MOSFETs with parasitic diodes of Db 1 , Db 2 , Db 3 , and Db 4 ; 6) the output capacitances of all MOSFETs have the same capacitance of COSS ; 7) the transformers of T1 and T2 have the same turns ratio of n = NS 1 /NP 1 = NS 2 /NP 2 . Mode 1 [t0 –t1 ]: Mode 1 begins when switches Q1 and Q3 are in on-state and diodes D1 and D3 are conducting. During this mode, the primary voltages Vp 1 (t) and Vp 2 (t) of the transformers T1 and T2 are the positive and negative halves of the input voltage, respectively. Thus, the magnetizing current iL m 1 (t) increases linearly from its initial value. However, iL m 2 (t) is nearly zero because the magnetizing inductance Lm 2 of T2 is very large. The secondary voltages Vs 1 (t) and Vs 2 (t) of T1 and T2 are the positive and negative halves of the input voltage reflected to the secondary by the turns ratio n, respectively, thus the power is transferred from the input to the output through T1 , T2 , D1 , and D3 . The output voltage of rectifier Vrec (t) becomes nVIN , which is the sum of Vs 1 (t) and −Vs 2 (t). The primary

Fig. 3.

Key operating waveforms of the proposed converter in a steady state.

currents in this mode can be expressed as follows: ip1 (t) = iL m 1 (t) + nisec 1 (t) = iL m 1 (t) + niD 1 (t) = iL m 1 (t) + nIO ip2 (t) = iL m 2 (t)+nisec 2 (t) ≈ nisec 2 (t) = −niD 3 (t) = −nIO . (1) Mode 2 [t1 –t2 ]: Mode 2 begins when Q3 is turned OFF at t1 . Then, the voltage across COSS3 is charged linearly and the voltage across COSS4 is discharged linearly by the energy stored in the output inductor LO . Vp 2 (t) increases from −0.5VIN to


Fig. 4.

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Operating circuits during the first half cycle: (a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5, (f) Mode 6, (g) Mode 7, and (h) Mode 8.

zero and Vp 1 (t) is continuously maintained at 0.5VIN , which increases continuously iL m 1 (t). Vs 2 (t) also increases from −0.5nVIN to zero and Vs 1 (t) becomes 0.5nVIN . Thus, Vrec (t) falls from nVIN to 0.5nVIN . The expressions of primary currents in this mode are the same as in mode 1. The voltages can be expressed as follows: VQ 3 (t) =

nIO (t − t1 ), VQ 4 (t) = VIN − VQ 3 (t) 2COSS

Vp2 (t) = −0.5VIN +

nIO (t − t1 ) 2COSS

Vrec (t) = Vs1 (t) + Vs2 (t) = nVIN −

n2 IO (t − t1 ). 2COSS

(2)

Mode 3 [t2 –t3 ]: Mode 3 begins when Vp 2 (t) becomes zero in mode 2. At the same time, Vs 2 (t) becomes zero and diode Da 2 starts to conduct. Because Da 2 is in conducting state, Vs 2 (t) is maintained at zero during this mode and the resonance of COSS3 , COSS4 , and Llk 2 occurs in the leading-leg SHBI. The voltage across COSS3 or COSS4 is continuously charged or discharged by the resonance, respectively. Vp 2 (t) increases from zero to 0.5VIN with a sinusoidal waveform and Vp 1 (t) is continuously

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maintained at 0.5VIN . The voltages and currents in this mode are given by Vp1 (t) = 0.5VIN , Vs1 (t) = 0.5nVIN , Vs2 (t) = 0

VQ 2 (t) = VIN − zO 2 ip1 (t5 ) sin ωO 2 (t − t5 ) Vp1 (t) = 0.5VIN − zO 2 ip1 (t5 ) sin ωO 2 (t − t5 ) Vp2 (t) = 0.5VIN

Vrec (t) = 0.5nVIN , Vp2 (t) = nIO zO 1 sin ωO 1 (t − t2 )

Vs1 (t) = Vs2 (t) = Vrec (t)

VQ 3 (t) = 0.5VIN + nIO zO 1 sin ωO 1 (t − t2 ) VQ 4 (t) = VIN

= 0.5nVIN − nωO 2 Llk 2 ip1 (t5 ) sin ωO 2 (t − t5 )

0.5VIN − VQ 3 (t), ip1 (t) = ip1 (t2 ) + (t − t2 ) Lm 1

ip2 (t) = −nIO cos ωO 1 (t−t2 ), iD 3 (t) = IO cos ωO 1 (t − t2 ) iD a2 (t) = IO − iD 3 (t), iD 1 (t) = IO

(3)

ip1 (t) = ip1 (t5 ) cos ωO 2 (t − t5 ) ip2 (t) = (nIO + 0.5ΔIripple ) − ip1 (t5 ) cos ωO 2 (t − t5 ) iD 4 (t) = IO − iD 1 (t) = ip2 (t)/n, iD a2 (t) = IO

(6)

where

where ωO 1 = √

1 2Llk 2 COSS

, zO 1 =

Llk 2 . 2COSS

Mode 4 [t3 –t4 ]: Mode 4 begins when Vp 2 (t) reaches 0.5VIN in mode 3. Then, the parasitic diode Db 4 of Q4 starts to conduct and Q4 is turned ON with ZVS. During this mode, Vs 2 (t) is maintained at zero, thus the voltage 0.5VIN appears on the leakage inductor Llk 2 . Due to this voltage across Llk 2 , the commutation between D3 and Da 2 is progressed. Vp 1 (t) and Vrec (t) are continuously maintained at 0.5VIN and 0.5nVIN , respectively. During this mode, the power is transferred from the input to the output through T1 , T2 , D1 , Da 2 , and D3 . The currents in this mode can be expressed as follows: ip1 (t) = ip1 (t3 ) +

0.5VIN (t − t3 ), Lm 1

ip2 (t) = −nIO +

0.5VIN (t − t3 ), iD 1 (t) = IO , Llk 2

VIN TS 4Lm 1 Llk 1 + Llk 2 = . 2COSS

ip1 (t5 ) = nIO + 0.5ΔIripple , ΔIripple = ωO 2 =

1 2(Llk 1 + Llk 2 )COSS

, zO 2

Mode 7 [t6 –t7 ]: Mode 7 begins when Vp 1 (t) reaches −0.5VIN in mode 6. Then, the parasitic diode Db 2 of Q2 starts to conduct and Q2 is turned ON with ZVS. In this mode, all the secondary voltages of the transformers, Vsec1 (t) and Vsec2 (t), are zero, thus Vrec (t) becomes zero. Due to Vrec (t) = 0, the load power is supplied from the energy stored in the output inductor LO at t6 . Because Vp 1 (t) = −0.5VIN , Vp 2 (t) = 0.5VIN , and Vs 1 (t) = Vs 2 (t) = 0 during this mode, the voltage Vlk 1 (t) across Llk 1 equals to −0.5VIN and the voltage Vlk 2 (t) across Llk 2 equals to 0.5VIN . Due to these leakage inductors’ voltages, ip 1 (t) or iD 1 (t) decreases linearly and ip 2 (t) or iD 4 (t) increases linearly. The currents can be expressed as follows:

(4)

ip1 (t) = ip1 (t6 ) −

0.5VIN (t − t6 ) Llk 1

Mode 5 [t4 –t5 ]: Mode 5 begins when the commutation between D3 and Da 2 is completed at t4 and only D1 and Da 2 conduct. In this mode, the primary current ip 2 (t) [or the secondary current isec2 (t)] in leading-leg SHBI is zero, i.e., the power is transferred from the input to the output through only T1 , D1 , and Da 2 . During this mode, the voltages and currents are given by

ip2 (t) = ip2 (t6 ) +

0.5VIN (t − t6 ) Llk 2

iD 3 (t) = IO − iD a2 (t), iD a2 (t) =

0.5VIN (t − t3 ). nLlk 2

Vp1 (t) = Vp2 (t) = 0.5VIN , Vs1 (t) = Vs2 (t) = 0.5nVIN , Vrec (t) = 0.5nVIN , ip1 (t) = ip1 (t4 ) + ip2 (t) = nisec2 (t) = 0.

0.5VIN (t − t4 ), Lm 1 (5)

Mode 6 [t5 –t6 ]: Mode 6 begins when Q1 is turned OFF at t5 . At the same time, diode D4 starts to conduct. Then, the resonance of COSS1 , COSS2 , Llk 1 , and Llk 2 occurs in the primary power path. The voltage across COSS1 or COSS2 is discharged or charged by the resonance, respectively. Vp 1 (t) is decreased from 0.5VIN to −0.5nVIN and Vrec (t) falls to zero. The commutation between D1 and D4 is also progressed. The voltages and currents in this mode can be expressed as follows: VQ 1 (t) = VIN − VQ 2 (t)

(7)

iD 4 (t) = IO − iD 1 (t) = ip2 (t)/n, iD a2 (t) = IO .

(8)

Mode 8 [t7 –t8 ]: Mode 8 begins when the current through D4 , iD 4 (t), reaches the output current IO and D1 is naturally turned OFF. At the same time, Vs 1 (t) becomes zero and Vs 2 (t) becomes 0.5nVIN . Thus, during this mode, the voltage 0.5VIN appears on Llk 1 , and the commutation between D2 and Da 2 starts. Vrec (t) equals to 0.5nVIN . The currents in this mode can be expressed as follows: ip1 (t) = ip1 (t7 ) −

0.5VIN (t − t7 ), ip2 (t) = nIO , Llk 1

iD 4 (t) = IO , iD 2 (t) = IO − iD a2 (t) =

0.5VIN (t − t7 ). nLlk 1

(9)

At the end of this mode, iD 2 (t) reaches the output current IO and Da 2 is naturally turned OFF. Then, the power is transferred from the input to the output through T1 , T2 , D2 , and D4 . Mode 9–16 [t8 –t16 ]: The operations from mode 9 to mode 16 are the same as previous modes except for the direction of powering path.


Fig. 6.

Fig. 5. Simplified rectifier output waveform: (a) in the proposed converter and (b) in the traditional PSFB converter with small leakage (or resonant) inductor.

III. RELEVANT ANALYSIS RESULTS A. Input-to-Output Relationship Since the durations of modes 2, 6, and 8 are very narrow in the proposed converter and hence they can be neglected, then, the rectifier output voltage can be shown as in Fig. 5(a). Averaging the voltage waveform Vrec (t) in Fig. 5(a) give the dc conversion ratio of the proposed converter as follows: M (D) =

VO = n(D + 0.5), D = (Tφ − 2Tdead )/TS (10) VIN

where TS is a switching period. Fig. 5(b) shows the rectifier output voltage waveform in the traditional PSFB converter with small leakage (or resonant) inductor. From the figure, we can obtain the dc conversion ratio of the converter as VO = 2nD, D = (Tφ − Tdead )/TS . (11) M (D) = VIN Normalized M(D) (supposing n = 1) is shown in Fig. 6. From the figure, it is noted that the gain of the proposed converter is higher than that of the traditional PSFB converter. Therefore, the turns ratio n of the proposed converter can be lower than that of the traditional PSFB converter at the same operating duty cycle, which will contribute to the improvement in power loss. B. ZVS Condition As described in the previous section, the ZVS of leading-leg switches is achieved by two resonant phases. At first, during mode 2, the voltage across the leading-leg switches is decreased linearly from VIN to 0.5VIN by the energy stored in the output inductor or the load current. Then, the remaining voltage on

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Normalized dc conversion ratio versus duty cycle.

the output capacitor of the switches is fully discharged by the leakage inductor Llk 2 during mode 3. The ZVS condition of leading-leg switches is obtained mathematically from (3) as VIN COSS nIO zO 1 sin ωO 1 Tdead − (12) ≥ 0.5VIN . nIO In the view of energy, (12) can be represented as 1 4 Llk 2 (nIO )2 ≥ COSS (0.5VIN )2 . 2 3

(13)

As seen in (12) or (13), the remaining energy in the output capacitors of the leading-leg switches, which should be discharged by Llk 2 , is half the total energy. Therefore, the ZVS of leadingleg switches is easily achieved with a small Llk 2 in a wide load range. If the current ripple of Lm 2 is used to ensure the ZVS at a light load condition, the ZVS condition is modified as follows: VIN COSS zO 1 (0.5ΔIripple + nIO ) sin ωO 1 Tdead − 0.5ΔIripple + nIO ≥ 0.5VIN or 1 4 Llk 2 (nIO + 0.5ΔIripple )2 ≥ CE (0.5VIN )2 2 3

(14)

is the current ripple of Lm 2 . where ΔIripple at a light Since the energy that is discharged by ΔIripple is load condition is also half the total energy, a small ΔIripple required. The ZVS condition of lagging-leg switches is obtained mathematically from (6) as

zO 2 (0.5ΔIripple + nIO ) sin ωO 2 Tdead ≥ VIN .

(15)

In the view of energy, (15) can be represented as 1 4 2 (Llk 1 + Llk 2 )(0.5ΔIripple + nIO )2 ≥ COSS VIN . 2 3

(16)

From (15) or (16), it is noted that although the energy discharge on the lagging-leg switches’ output capacitors is dependent only on the energy stored in the leakage inductors, the ZVS can be easily achieved in a wide load range due to the terms of

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Fig. 7.


Simplified primary-operating waveforms of: (a) traditional PSFB converter with small magnetizing inductance and (b) proposed converter.

Llk 1 + Llk 2 and the current ripple of iL m 1 (t), ΔIripple . However, since the large leakage inductances affect the duty-cycle loss, a tradeoff between the leakage inductances and ΔIripple should be made in optimally designing the proposed converter. Until now, the ZVS condition of the proposed converter has been analyzed. To extend the ZVS range of lagging-leg SHBI, the magnetizing inductor Lm 1 (or ΔIripple ) can be used as well as the two leakage inductors. This allows that the proposed converter can realize the ZVS with only small leakage inductors in a wide range of load variation. In addition, because the assistant current of Lm 1 , which extends the ZVS range of lagging-leg SHBI, never flow through switches Q3 , Q4 , and transformer T2 in the leading-leg SHBI, the RMS current stress and conduction losses in the leading-leg SHBI does not increase. This is contrast to the fact that in the traditional PSFB converter, using a small magnetizing inductance for a wider ZVS range increases the conduction losses in all the switches and the transformer, as shown in Fig. 7(a) and (b). Additionally, the primary RMS current stress in the lagging-leg SHBI in spite of using a small magnetizing inductance of T1 is much lower than the traditional PSFB with a small magnetizing inductance, because the average value of the magnetizing current of T1 is zero within a half-switching period, and its contribution to the total RMS current at large loads is negligible. Also, it is much lower compared to the traditional PSFB with a large magnetizing inductance due to the lower turns ratio as described in the previous part. These are confirmed from the analysis result of the primary RMS current stress in Fig. 8. Consequently, in spite of using a small magnetizing inductance of T1 , the primary conduction losses in

the proposed converter become lower than that of the traditional PSFB converter. C. Duty-Cycle Loss In general, it is widely known that utilizing large resonant inductor for extending ZVS range reduces the effective duty-cycle (or increases the duty-cycle loss). To compensate this, the turns ratio n of the transformer is designed to be higher, thereby increasing the primary-conduction losses and secondary-voltage stress. However, the ZVS range in the proposed converter is extended using only the magnetizing inductance of the transformer in lagging-leg SHBI, while minimizing the additional conduction loss. Thus, the proposed converter has no problems related to the duty-cycle loss. D. Circulating Current There is the circulating current in the traditional PSFB converter, as shown in Fig. 7(a), which flows through the transformer and switches although the primary voltage Vprim ary (t) of the transformer is zero. This increases the conduction losses. On the other hand, in the proposed converter, all primary voltages of the transformers are in phase with the primary currents, thus, there is no circulating current. In addition, the area of the reverse current of leading-leg switches as well as its current stress is much smaller than that in the traditional PSFB converter, which results in the improvement in the conduction and turn-off switching losses. These are shown in Fig. 7(b).


Fig. 8.

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Primary RMS current stress at a full load. Fig. 9.

E. Filter Requirement

Required output filter inductance for IP P = 1 A.

The output filter inductor can be designed from the rectifier output voltage in Fig. 5 using (10), (11), and (17) IP P (17) ΔT where IPP is the peak-to-peak value of the current flowing through the output inductor LO and V is the voltage applied to LO during the time ΔT. For the proposed converter V = LO

LO =

prop osed

VO 0.5 1− (1−Mnorm ailized (D))TS . (18) IP P Mnorm ailized (D)

For the traditional PSFB converter VO LO PSFB = (1 − Mnorm ailized (D))TS . 2IP P

(19)

Fig. 10.

Center-tap-type rectifier for the proposed converter.

TABLE I COMPONENTS LIST

For a quantitative analysis, the following parameters are used: 1) output voltage: VO = 205 V; 2) IPP = 1 A; 3) switching frequency: fS = 100 kHz. Fig. 9 shows the required filter inductance in function of the normalized dc conversion ratio. From Figs. 6 and 9, it is noted that the output inductance of the proposed converter is much smaller than that of the traditional PSFB converter at the same operating duty cycle. F. Center-Tap-Type Rectifier for Low Voltage Applications The rectifier structure shown in Fig. 1 is a kind of full-bridge rectifier. In general, two types of rectifiers are widely used, i.e., full-bridge rectifiers and center-tap rectifiers. Although a fullbridge rectifier employs four diodes, compared to a center-tap rectifier, it offers benefits when it comes to transformer size and voltage stresses on the diodes for high voltage applications. On the other hand, in the case of a center-tap rectifier, only two diodes are employed and there is only one diode in the secondary current path, resulting in less conduction loss for low voltage applications.

A center-tap-type rectifier suitable to the proposed configuration for low voltage applications is presented in Fig. 10. The primary structure is the same and only the secondary structure is changed. Each transformer has two secondary windings and they are connected in series by turns. D1 and D2 are the main diodes, and Da 1 and Da 2 are the auxiliary diodes. The operational principle of the proposed configuration with the centertap rectifier is identical to that with the full-bridge rectifier in Fig. 3.

120


Fig. 11. Key experimental waveforms of the proposed converter at the nominal input voltage, i.e., 385-V and a full load of 5 A. (a) V p 1 (t), ip 1 (t), V p 2 (t), and ip 2 (t) and (b) V p 1 (t), V p 2 (t), and V se c (t).

Fig. 12.

ZVS waveforms of lagging-leg SHBI under different load conditions: (a) at no load, (b) at 20% of full load, (c) at 50% of full load, and (d) at full load.

Fig. 13.

ZVS waveforms of leading-leg SHBI under different load conditions: (a) at no load, (b) at 20% of full load, (c) at 50% of full load, and (d) at full load.


121

current in the leading-leg switches of the conventional PSFB converters does not appear on that of the proposed converter. B. Efficiency Fig. 14 shows the efficiency measured using a power analyzer (PPA2520, KinetiQ) at different load conditions when the input voltage is 385 V. As shown in Fig. 14, the proposed converter has the maximum efficiency of 95.76% at a full load and achieves a significant improvement in the efficiency as compared with its counterparts. This is originated from the proposed converter’s operation with ZVS under entire load conditions while having no effect of duty-cycle loss and no circulating current. V. CONCLUSION Fig. 14.

Efficiency under different load conditions.

IV. EXPERIMENTAL RESULTS The proposed converter and the converters for comparison are realized with the specifications of an 80-in PDP sustain power module given as follows: 1) input voltage: VIN = 320–385 V; 2) output voltage: VO = 205 V; 3) maximun output current: IO ( m ax ) = 5 A; 4) switching frequency: fS = 100 kHz. The prototype converter for the experiment was built and tested to verify the operational principle, advantages, and performances of the proposed converter using the components, as shown in Table I. In order to alleviate the voltage overshoot and oscillation, the snubber circuit (R = 15 kΩ/2 W, C = 1 μF/630 V, D = UF4004) introduced in [28] is employed. The conventional PSFB converters built for the comparison with the performance of the proposed converter are designed in such a way that the ZVS operation is achieved in the range of 50–100% of full load. This is because to ensure the ZVS operation under light load conditions, it needs a very large resonant inductor, which results in very high voltage stress across the rectifier diodes, high conduction losses and no regulation of the output voltage. A. Waveforms Fig. 11 shows the key waveforms of the proposed converter at the nominal input voltage, i.e., 385 V and a full load of 5 A. As shown in Fig. 11, all measured waveforms are well following the theoretical waveforms described in Fig. 3. And, we can see that due to the output voltage wavefrom of the rectifier, the output filter can be much smaller than the conventional PSFB converters. Moreover, it is seen that there is no severe secondary-voltage overshoot and oscillation due to the low leakage inductances and improved turns ratio, which allows the use of lower voltage rating diodes. Figs. 12 and 13 show the ZVS waveforms of the leading-leg or lagging-leg SHBIs at different load conditions, respectively. From Figs. 12 and 13, it is clear that all the switches in the proposed converter are turned ON with ZVS under entire load conditions. In addition, we can see the wide negative

This paper has presented a new soft-switching dc/dc converter that can solve the drawbacks of existing PSFB converters, such as narrow zero-voltage-switching (ZVS) range, large circulating current, large duty-cycle loss, and a large output filter in highvoltage applications. In this paper, the theoretical analysis has also been provided to show that the proposed converter has the performance over existing PSFB converters. The experiment results of a prototype converter realized with the specifications of an 80-in PDP sustain power module showed that the theoretical analysis is valid and the proposed converter achieves a significant improvement in efficiency. Hence, the proposed converter is applicable to the high-voltage applications such as PDP sustain power module, high voltage battery charger (200–400 V), etc. REFERENCES [1] J. A. Sabatè, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, “Design considerations for high-voltage high-power full-bridge zero-voltageswitching PWM converter,” in Proc. Appl. Power Electron. Conf., 1990, pp. 275–284. [2] B. Chen and Y. Lai, “Switching control technique of phase-shiftcontrolled full-bridge converter to improve efficiency under lightload and standby conditions without additional auxiliary components,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 1001–1011, Apr. 2010. [3] I. Cho, K. Cho, and G. Moon, “A new phase-shifted full-bridge converter with maximum duty operation for server power system,” IEEE Trans. Power Electron., vol. 26, no. 12, pp. 3491–3500, Dec. 2011. [4] Y. Shin, C. Kim, and S. Han, “A pulse frequency modulated full bridge DC/DC converter with series boost capacitor,” IEEE Trans. Ind. Electron., vol. 58, no. 11, pp. 5154–5162, Nov. 2011. [5] G. Hua, F. C. Lee, and M. M. Jovanović, “An improved full-bridge zerovoltage-switched PWM converter using a saturable inductor,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530–534, Oct. 1993. [6] R. Redl, N. O. Sokal, and L. Balogh, “A novel soft-switching full-bridge DC/DC converter: Analysis, design considerations, and experimental results at 1.5 kW, 100 kHz,” IEEE Trans. Power Electron., vol. 6, no. 3, pp. 408–418, Jul. 1991. [7] W. Chen, X. Ruan, and R. Zhang, “A novel zero-voltage-switching PWM full bridge converter,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 793–801, Mar. 2008. [8] W. Chen, X. Ruan, Q. Chen, and J. Ge, “Zero-voltage-switching PWM fullbridge converter employing auxiliary transformer to reset the clamping diode current,” IEEE Trans. Power Electron., vol. 25, no. 5, pp. 1149– 1162, May 2010. [9] Y. Jang and M. M. Jovanović, “A new family of full-bridge ZVS converters,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 701–708, May 2004.

122

[10] X. Wu, J. Zhang, and Z. Qian, “Analysis and optimal design considerations for an improved full bridge ZVS DC-DC converter with high efficiency,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1225–1234, Sep. 2006. [11] M. Borage, S. Tiwari, S. Bhardwaj, and S. Kotaiah, “A full-bridge DCDC converter with zero-voltage-switching over the entire conversion range,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1743–1750, Jul. 2008. [12] M. Borage, S. Tiwari, and S. Kotaiah, “A passive auxiliary circuit achieves zero-voltage-switching in full-bridge converter over entire conversion range,” IEEE Trans. Power Electron., vol. 3, no. 3, pp. 141–143, Dec. 2005. [13] Y. Jang, M. M. Jovanović, and Y. Chang, “A new ZVS-PWM full-bridge converter,” IEEE Trans. Power Electron., vol. 18, no. 5, pp. 1122–1129, Sep. 2003. [14] T. Wu, C. Tsai, Y. Chang, and Y. Chen, “Analysis and implementation of an improved current-doubler rectifier with coupled inductors,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2681–2693, Nov. 2008. [15] N. H. Kutkut, D. M. Divan, and R. W. Gascoigne, “An improved fullbridge zero-voltage-switching PWM converter using a two-inductor rectifier,” IEEE Trans. Ind. Appl., vol. 31, no. 1, pp. 119–126, Jan. 1995. [16] G. Koo, G. Moon, and M. Youn, “Analysis and design of phase shift full bridge converter with series-connected two transformers,” IEEE Trans. Power Electron., vol. 19, no. 2, pp. 411–419, Mar. 2004. [17] H. Yoon, S. Han, E. Choi, G. Moon, and M. Youn, “Zero-voltage switching and soft-commutation two-transformer full-bridge PWM Converter using the voltage-ripple,” IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 1478– 1488, Mar. 2008. [18] X. Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian, “Soft switched full bridge DC-DC converter with reduced circulating loss and filter requirement,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1949–1955, Sep. 2007. [19] X. Wu, X. Xie, C. Zhao, Z. Qian, and R. Zhao, “Low voltage and current stress ZVZCS full bridge DC-DC converter using center tapped rectifier reset,” IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 1470–1477, Mar. 2008. [20] K. Seok and B. Kwon, “An improved zero-voltage and zero-currentswitching full-bridge PWM converter using a simple resonant circuit,” IEEE Trans. Ind. Electron., vol. 48, no. 6, pp. 1205–1209, Dec. 2001. [21] J. Dudrik and N. Trip, “Soft-switching PS-PWM DC-DC converter for full-load range applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2807–2814, Aug. 2010. [22] T. T. Song and N. Huang, “A novel zero-voltage and zero-currentswitching full-bridge PWM converter,” IEEE Trans. Power Electron., vol. 20, no. 2, pp. 286–291, Mar. 2005. [23] E. Kim and Y. Kim, “A ZVZCS PWM FB DC/DC converter using a modified energy-recovery snubber,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1120–1127, Oct. 2002. [24] S. Moisseev, K. Soshin, and M. Nakaoka, “Tapped-inductor filter assisted soft-switching PWM DC-DC power converter,” IEEE Trans. Aerosp. Electron. Syst., vol. 41, no. 1, pp. 174–180, Jan. 2005. [25] H. Cha, L. Chen, R. Ding, Q. Tang, and F. Z. Peng, “An alternative energy recovery clamp circuit for full-bridge PWM converters with wide ranges of input voltage,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2828– 2837, Nov. 2008.


[26] R. Ayyanar and N. Mohan, “Novel soft-switching DC-DC converter with full ZVS-range and reduced filter requirement—Part I: Regulated-output applications,” IEEE Trans. Power Electron., vol. 16, no. 2, pp. 184–192, Mar. 2001. [27] R. Ayyanar and N. Mohan, “Novel soft-switching DC-DC converter with full ZVS-range and reduced filter requirement—Part II: Constant-input, variable-output applications,” IEEE Trans. Power Electron., vol. 16, no. 2, pp. 184–192, Mar. 2001. [28] S. Lin and C. Chen, “Analysis and design for RCD clamped snubber used in output rectifier of phase-shiftfull-bridge ZVS converters,” IEEE Trans. Ind. Electron., vol. 455, no. 2, pp. 358–359, Apr. 1998.

Il-Oun Lee (S’10) was born in Korea in 1976. He received the B.S. degree in electrical and electronic engineering from Kyungpook National University, Taegu, Korea, in 2000, and the M.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2002. He is currently working toward the Ph.D. degree at the Korea Advanced Institute of Science and Technology, Daejeon, Korea. Beginning in 2003, he was a Research Engineer in the Plasma Display Panel (PDP) Development Group, Samsung SDI, Korea, for five years, where he was involved in circuit and product development for 42-in, 50-in, 63-in, and 80-in PDP TV. From 2008 to 2009, he was a Senior Engineer in the Power Advanced Development Group, Samsung Electro-Mechanics Company Ltd., where he was involved in the power circuit development for LED lighting, LCD TV, PDP TV, and server power system. His current research interests include dc–dc converters, power-factor-correction ac–dc converters, LED driver, battery charger for electric vehicle, digital display power systems, and digital control approach of dc–dc converters.

Gun-Woo Moon (S’92–M’00) received the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1996, respectively. He is currently a Professor in the Department of Electrical Engineering, KAIST. His research interests include modeling, design and control of power converters, soft-switching power converters, resonant inverters, distributed power systems, power-factor correction, electric drive systems, driver circuits of plasma display panels, and flexible ac transmission systems. Dr. Moon is a Member of the Korean Institute of Power Electronics, Korean Institute of Electrical Engineers, Korea Institute of Telematics and Electronics, Korea Institute of Illumination Electronics and Industrial Equipment, and Society for Information Display.