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A Multiphase DC/DC Converter with Hysteretic Voltage Control and Current Sharing. Wei Gu*, Weihong Qiu, Wenkai Wu†, and Issa Batarseh. *Reliability Inc.

A Multiphase DC/DC Converter with Hysteretic Voltage Control and Current Sharing Wei Gu*, Weihong Qiu, Wenkai Wu†, and Issa Batarseh *Reliability Inc. Houston, TX 77084 Email: [email protected]

School of Electrical Engineering and Computer Science University of Central Florida Orlando, FL 32816

APECOR Co. Research Pavilion #453 12424 Research Parkway Orlando, FL 32826

comparators are used for all modules and interleaving is achieved through sequence circuit only. Reset circuit is activated during the large load transient using the same current probes for the MOSFETs protection circuit. The high-side switch of the first module is on and off when the output voltage hits the hysteretic boundary and then the high-side switch of second module is on and off, thus the two main switches work alternately with 180o phase shift if the power stages are identical.

Abstract: Interleaving technique and hysteretic voltage control are suitable for low-voltage, highcurrent, fast-response power supplies. In this paper, a multiphase DC/DC converter employing interleave and hysteretic control techniques and current sharing is proposed. The design considerations are discussed. Simulation and experimental results are reported. I. INTRODUCTION

Figure 2 shows the waveforms of output inductor currents and switching drive signals. For an interleaved converter with more than two modules, the toggle circuit could be replaced by a circuit with a functionality that outputs an ON signal in certain order to the driver circuit. In other words, when one switch is on, the other three are off. During large transients, all the switches are in same states when the output voltage hits the Vall_off or Vall_on.

Future high-performance microprocessors may require from 40 to 100 watts of power for the CPU alone. Load current must be supplied with at least 50A/µs slew rate while keeping the output voltage within tight regulation and response time tolerances. Conventional synchronous regulator control techniques include PWM voltage control, PWM current control and variable frequency current control. CPU power supplies that are designed using these types of control methods require additional bulk storage capacitors to maintain output voltage within the regulation limits during the high di/dt load transients because of the limited bandwidth of the controller.

Load Vin

Hysteretic control, also called bang-bang control or ripple regulator control, maintains the output voltage within the hysteretic band centered about the internal reference voltage [1-4]. If the output voltage reaches or exceeds the reference plus one-half of the hysteretic band, the controller turns off the high-side MOSFETs and turns on the low-side MOSFETs. This is the power stage offstate, and it causes the output voltage to decrease. When the output voltage is at or below the level of the reference minus one-half of the hysteretic band, the power stage is in off-stage. This hysteretic method of control keeps the output voltage within the hysteretic band around the reference voltage. Thus the output voltage is corrected as quickly as the output filter allows.

Driver Circuit

Reset and Protection Circuit



Vvalley Softstart

The general layout for an interleaved structure and its hysteretic control are shown in Fig. 1 [5]. Only a 2-module converter is presented for simplicity. In Fig. 1, Vpeak and Vvalley are the hysteretic band boundary and Vall_on and Vall_off are the voltage levels below or above which all the switches will be on or off, respectively. The same

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Sequence Circuit


Fig. 1: Interleaved synchronous regulator


From [3], the equation for the switching frequency of one power stage converter is:

IL 1

f s0 =

VO × (VI − VO ) × ( ESR − tdel / CO ) VI × (VI × ESR × tdel + Hyst × L − ESL × VI )

IL 2

where, V I is the input voltage and VO is the output voltage. For a 2-module interleaved converter, the ripple cancellation should be taken into account during the prediction.

IL 1 + IL 2

The hysteretic band is equal to the difference between the peak-peak values of the Vo ripple (Vp-p), at the times ton − t del and toff − t del , and given by,

t S m o d u l1

Hyst = V p − p (ton − tdel ) − V p − p (toff − tdel )

Based the above equations, the following equation for the switching frequency of a 2-module converter can be derived:

S m o d u l2


Fig. 2: Waveforms of Interleaved synchronous regulator

fs =

VO × (VI − VO ) 2 × ( ESR − tdel / CO ) 2VIVO × (VI − VO ) × (VI × ESR × tdel − ESL × VI ) + 2V 2 I × (VI − 2VO ) × Hyst × L

II. SWITCH FREQUENCY ANALYSIS Figures 4(a) and (b) give theoretical estimate of the switching frequencies against the input voltage or hysteretic band voltage.

After the elements of the output filter are determined, the power supply switching frequency must be estimated [3]. If the estimated switching frequency is too high, the switching losses in the power MOSFETs will be high, resulting in less than optimum efficiency. If the estimated switching frequency is too low, the inductor value may be too high, resulting in unsatisfactory transient response.

Three Os-con 820-µF, 4-V capacitors were used in this example circuit. ESR and ESL for each capacitor were 8mΩ, and 4.8nH, respectively. The other values that were substituted are the following: L=0.5µ, Hyst=20mV, tdel=0.8µs. It is noted that the switching frequency of the multiphase converter is too small. That’s why another method is recommended in Section IV.

To accurately predict the switching frequency of a hysteretic regulator, the output voltage in Figure 3 is the desired steady-state value. The output voltage ripple shown in Fig. 3 will be investigated. The three elements of the capacitor that contribute to ripple are ESR, ESL, and capacitance.


1 .10


V p − p (t ) = VC (t ) + VESR (t ) + VESL (t ) tdel Vripple


fs(v) fs0(v)


1 .10



1 .10



4 5 6 7 8 9 10 11 12 13 v Input voltage


(a) freq. vs input voltage Fig. 3: Output ripple

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with current sharing (the value of the added resistors is 0.01Ω).



1 .10


fs ( v ) fs0( v )

1 .10


1 .10


1 .10






Hyst v (b) Frequency vs Hyst Fig. 4: Estimation of switching frequencies Fig. 5 Without current sharing, current difference is around 4A (total current: 26A)

III. CURRENT SHARING Due to the strict size and efficiency requirements and for cost and integration purpose, the current sharing becomes more critical in the VRM application. For a twomodule multiphase converter, the duty ratios are given by the following relations: D1 =

Vo − I o1 × Ron1 and V − I o 2 × Ron 2 . D2 = o Vin Vin

where I o1 and

I o 2 are the output currents for the two modules, and Ron1 and Ron 2 are the on resistances of the two high-side MOSFETs for the two modules. For the voltage control, we have, roughly, D1 = D2 . Therefore,

I o1 × Ron1 = I o 2 × Ron 2 . Usually, there is 20% difference for the on resistances of the MOSFETs. The larger the load current, the worse the current sharing results.

Fig. 6 With current sharing, current difference is around 0.2A

In Fig. 1, two small resistors are added between the output inductors and the output. The feedback signal, which is used to compare with the reference Vpeak, is not from the output node, but from the nodes between the two inductors and added resistors. As such, the current information is introduced into the control loop and current sharing is achieved. The channel with the larger current will have a larger voltage drop on the resistor, thus the voltage of node between the inductor and the resistor increases more rapidly than that of the other channel, which means a smaller turn-on time. Thus the current from this channel is decreased and current balance is reached for the two channels.

IV. INTERLEAVING WITH “TPS5211 METHOD” The operation of the single-phase hysteretic controller TPS5211 differs from a regular hysteretic controller. The additional ramp signal through the input of the hysteretic comparator is formed by R and C as shown in Fig. 7(a). The two signals are summed through the inputs of the comparator. The two signals are the ramp signal from R-C circuitry (the other module is the same) and the signal from the output converter. By proper selection of R and C, one can get the amplitude of an additional ramp signal which is greater than the output ripple of the converter. As a result, the switching frequency is larger while the output ripple becomes lower. Figure 8 shows the two current waveforms and output voltage ripple. Without current sharing, the current difference is around 4A out of the total current 26A with a 57% ON resistance difference.

Figure 5 shows the two current waveforms and output voltage ripple. Without current sharing (without adding the two small resistors), the current difference is around 4A out of the total current 26A with a 57% ON resistance difference. Figure 6 shows that there is 0.2A difference

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Figure 9 shows there is 0.3A difference with current sharing. The general layout is shown in Fig.7(b). Two current sensing resistors between the output inductors and the output and three Op-amps are added (comparied with Fig. 7(a)). Not only the feedback signal, which is used to compare with the reference Vpeak and which is from the RC node, but also the current signals that are proportional to the voltage across the current sensing resistors determine the time that the output voltage hit the Vpeak. As such, the current information is introduced into the control loop and current sharing is achieved.

Voutput Load



Fig. 8 Without current sharing, current difference is around 4A (total current: 26A).


Driver Circuit


Reset and Protection Circuit


VoutputMain Vvalley


Sequence Circuit Vpeak



Fig. 9 With current sharing, current difference is around 0.3A


Driver Circuit

From Fig. 9, it’s shown by adding simple circuitry the current sharing is effective. The current sensing resistors and Op-amps translating the current signal to the voltage signal and play the role in modifying the Vpeak value on a cycle-by-cycle basis. However, it should be noted this modification must be kept in a low amplitude in order to keep the output voltage with the accuracy window. Also in this approach, the resetting and proctection circuit can utilize the average output current signal from the output inductor instead of the MOSFET current.


Reset and Protection Circuit


Vvalley Softstart

Sequence Circuit

A 5-12V input, 1.65V output 2-module interleaved converter with a maximum output current 26A is designed. Simulation results are shown in Fig. 10. Load transient from 10% load to full load and from full load to 10% load occurs at 152µs and 250µs, respectively.


(b) Fig 7 General Layout

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hysteretic. Improvement could be made with the introduction of a custom designed IC. Additional experimental results for four-phase VRM employing current sharing is being done. V. SUMMARY A multiphase buck converter with hysteretic voltage control and current sharing for two power stages is presented. The method for interleaving can be easily applied to large number of VRM modules by modifying the sequence circuit. One notable improvement is the increase in the switching frequency for all the channels without sacrificing the other performance. Only utilizing the output ripple to trigger the comparators is obvious not enough due to the delay of the control circuit. This will also help the stability of the converter since larger error signal is less susceptible to the noise from the outside. TPS5211 provides a good approach.

Fig. 10 Simulation Result

It was found that the output voltage would break out from the hysteretic band during large transients, and fail to reenter the band in some cases. Though the output voltage remains at a certain value, it is possible that the inductor currents IL1 and IL2 would run away which will make one the inductors saturate. As for a hysteretic voltage control, the switches are only changing status according to the output voltage. During the load transient from 10% load to full load, one high-side switch remains on until the current flowing through the switch reaches the maximum value allowed. The reset circuit triggered and this switch is turned off while the other high-side switch is turned on. Drive1 and Drive2 waveforms in Fig. 10 is the reset signal leading to the changes of switches’ status

With the integration of the output inductors, and design of mixed-signal chips for the control and driver circuit, the efficiency and performance should be improved which make this interleaved synchronous buck regulator a potent competitor in the future. Simulation and experimental results are in a full agreement. REFERENCES [1] Xunwei Zhou, “Low-Voltage High-Efficiency Fast Transient Voltage Regulator Modules”, Ph.D. Dissertation, Virginia Polytechnic Inst. State Univ., Blackburg, 1999. [2] Rais Miftakhutdinov, “Analysis and Optimization of Synchronous Buck Converter at High Slew Rate Load Current Transients,” in IEEE PESC 2000, pp.714-720. [3] “Designing Fast Response Synchronous Buck Regulators Using the TPS 5210”, Application Report, Texas Instrument, March 1999. [4] “Synchronous Buck EVM Using the TPS5211”, User’s Guide, Texas Instrument, June 2000. [5] Wei Gu and Issa Batarseh, “Interleaved Synchronous Buck Regulator with Hysteretic Voltage Control”, PESC 2001, Vancouver, Canada.

Fig. 11 Experimental results

Figure 11 shows some experimental results[5]. The upper waveforms are the two output currents at full load. The lower waveform is the output voltage ripple. The ripple of the output voltage is quite large due to the delay in the control circuit even with a preset value of zero

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