www.ietdl.org Published in IET Power Electronics Received on 15th August 2012 Revised on 18th November 2012 Accepted on 4th December 2012 doi: 10.1049/iet-pel.2012.0426

ISSN 1755-4535

Zero-voltage switching full-bridge DC/DC converter with parallel-connected output and without output inductor Bor-Ren Lin, Tung-Yuan Shiau Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: [email protected]

Abstract: This study presents a soft-switching converter without output inductor. The features of the proposed converter are zero-voltage switching (ZVS) for all power switches, load current sharing and high circuit efﬁciency. Full-bridge converter with phase-shift pulse-width modulation (PWM) is adopted to regulate the output voltage. Based on the resonant behaviour by the output capacitance of MOSFETs and the resonant inductance, active switches can be turned on at ZVS during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The voltage stress of power switches is clamped to DC bus voltage. Four transformers are connected in series in the primary side. Each transformer can be operated as an inductor to smooth the output current or a transformer to achieve electric isolation and power transfer from input side to output side. Therefore no output inductor is needed in the secondary side. Two centre-tapped rectiﬁers connected in parallel are used in the secondary side to achieve load current sharing. Finally, experiments based on a 960 W (48 V/20 A) laboratory prototype are provided to demonstrate the performance of proposed converter.

1

Introduction

Switching converters with high-efﬁciency and high-power density have been demanded for modern power supply units such as server systems, data storage systems, telecommunication system, cloud power systems and medical power systems. To meet the climate saver computing initiative (CSCI) or environment protection agency (EPA) requirements, two-stage AC/DC converters with power factor correction (PFC) are usually adopted to reduce AC current harmonics and reactive power and to regulate output DC voltage against the AC input voltage and load variations. PFC converters [1–3] with boost-type technique and continuous conduction mode are widely used in the front stage to draw a sinusoidal line current from AC utility in order to meet the IEC61000–3-2 limits. In the second stage, three-level DC/DC converters [4–6], resonant converters [7–9], active clamp converters [10–12], asymmetric half-bridge converters [13–15] and full-bridge converters [16, 17] have been proposed to regulate the output voltage with the wide load ranges and input voltage variations. Three-level converters use the clamp diodes or clamp capacitors to reduce the voltage stress on active switches for high-voltage applications. However, the disadvantages of three-level converters are too many active and passive components, high circuit cost and the difﬁcult control scheme. Resonant converters can achieve zero-voltage switching (ZVS) on MOSFETs with the wide load ranges. However, the transformer in resonant converters cannot be designed at the optimal condition IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

because of using the variable switching frequency to regulate output voltage. Active clamp converters can reduce the switching losses with the auxiliary switch and clamp capacitor. The voltage stress of power switches in active clamp topologies cannot be reduced to a safety region if the maximum duty ratio is >0.5. Asymmetric half-bridge converters have the advantages of ZVS turn-on and low-voltage stress on power switches. However, the drawbacks are the average DC magnetising current on the transformer is not zero and the voltage stresses on the rectiﬁer diodes are unbalanced. This paper presents a soft-switching full-bridge converter without output inductor. Two centre-tapped rectiﬁers are used in the output side to reduce the current stress of the secondary windings. To balance the output currents of two centre-tapped rectiﬁers, the transformer primary windings are connected in series. For each centre-tapped rectiﬁer, there are two transformers connected in series. One transformer works as a forward-type transformer, and the other transformer works as an inductor. Thus, no output inductor is needed at the secondary side and the output current before the output capacitor is a continuous waveform. Based on the pulse-width modulation (PWM) with phase-shifted technique, active switches in the leading leg can be turned on at ZVS with the wide load ranges because of the energy stored in the resonant inductance and magnetising inductance. The active switches in the lagging leg can also achieve ZVS in the desired load range with the selected resonant inductance. Thus, the switching losses of active switches are reduced. The circuit conﬁguration, 505

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www.ietdl.org principle of operation, circuit characteristics and design procedure of the proposed converter are presented in detail. Finally, experiments, based on a 960 W prototype, are presented to verify the effectiveness of the proposed converter.

2

Circuit configuration

Fig. 1 gives the circuit conﬁguration of the proposed ZVS converter. The input DC bus voltage is obtained from a power factor corrector. The input DC bus voltage Vin is usually regulated at 390 V for universal single-phase utility voltage. Q1, Q2, Q3 and Q4 are power MOSFETs. Lr is the resonant inductance. Cr1–Cr4 are output capacitances of power MOSFETs Q1–Q4, respectively. D1–D4 are rectiﬁer diodes at output side. Lm1–Lm4 are the magnetising inductances of transformers T1–T4, respectively. Co is the output capacitance. Full-bridge converter is used to regulate output voltage. Two centre-tapped rectiﬁers are adopted to share load current. In order to balance two centre-tapped rectiﬁers, the primary windings of transformers T1–T4 are connected in series. T1–T4 can be operated as transformers to achieve electric isolation and power transfer or operated as inductors to smooth output current. Therefore no output inductor is necessary in the proposed converter. The phase-shift PWM scheme is used to control power MOSFETs. Based on the resonant behaviour by Lr and Cr1–Cr4 at the transition interval, Q1–Q4 can be turned on at ZVS. Thus, the switching losses of active switches Q1–Q4 can be reduced. The voltage stress of each power MOSFET is equal to input DC bus voltage. Therefore MOSFETs with 500 or 600 V voltage stress can be used in the proposed converter.

3

System analysis and operation principle

Before the discussion the operation principle, some assumptions are made to simplify the system analysis of the proposed converter. 1. Four transformers T1–T4 have the same magnetising inductances Lm1 = Lm2 = Lm3 = Lm4 = Lm and turns ratio n = np/ns; 2. Q1–Q4 are ideal and have the same output capacitances Cr1 = Cr2 = Cr3 = Cr4 = Cr; 3. Diodes D1–D4 are ideal; 4. Resonant inductance Lr < < Lm; 5. Co is large enough to be a constant voltage; 6. The energy stored in the resonant inductance Lr is greater than the energy stored in resonant capacitors Cr1–Cr4 such that the ZVS turn-on of all switches can be achieved.

switching period. The theoretical PWM waveforms of the proposed converter are shown in Fig. 2. The duty cycle of each switch is equal to 0.5. The PWM signals of Q3 and Q4 are phase-shifted with respective to the PWM signals of Q2 and Q1. Fig. 3 gives the equivalent circuits of ten operation modes. Before time t0, Q1 and Q4 are both in the on-state and diodes D1–D4 are conducting. Mode 1 [t0 ≤ t < t1]: At time t0, diode currents iD2 and iD4 are decreased to zero. Only diodes D1 and D3 are conducting in this mode. The magnetising voltage vLm1 = vLm3 = nVo. Thus, the magnetising currents iLm1 and iLm3 increase with the slope of nVo/Lm. Lm2 and Lm4 operate as the inductors in this mode. The voltage across inductors Lr, Lm2and Lm4 equals Vin–2nVo. The inductor current iLr increases linearly with the slope of (Vin–2nVo)/(Lr + 2Lm). The energy stored in Lr, Lm2 and Lm4 is increasing. The input power is transferred to output load through Q1, T1, T3, Q4, D1 and D3. This mode ends at time t1 when Q1 is turned off. At time t1, the inductor current iLr is given as V − 2nVo t1 − t0 iLr t1 ≃ iLr t0 + in Lr + 2Lm

(1)

Mode 2 [t1 ≤ t < t2]: At time t1, Q1 is turned off. Since the inductor current iLr(t1) > 0, Cr1 is charged and Cr2 is discharged in this mode. Since Cr1 and Cr2 are about hundreds of pico-farad, vCr1 and vCr2 can be expressed as iLr t1 iLr t1 vCr1 (t) ≃ t − t1 , vCr2 (t) ≃ Vin − t − t1 (2) 2Cr 2Cr The inductor current iLr is almost constant in this mode. The ZVS condition of Q2 is given in (3).

Lr + 2Lm i2Lr t1 . Cr Vin2 2

(3)

This mode ends at time t2 when vCr2 = 0. Mode 3 [t2 ≤ t < t3]: At time t2, vCr2 = 0. Since iLr(t2)≃ iLr(t1) > 0, the anti-parallel diode of Q2 is conducting. Therefore Q2 can be turned on at ZVS in this moment. The dead time between Q1 and Q2 should be greater than the

Based on the on/off states of Q1–Q4 and D1–D4, the proposed converter has ten operating modes during one

Fig. 1 Proposed soft-switching converter without output inductor 506 & The Institution of Engineering and Technology 2013

Fig. 2 Key waveforms of the proposed converter IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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Fig. 3 Operation modes of the proposed converter in one switching cycle a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9 j Mode 10

IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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www.ietdl.org time interval in mode 2. td ≥ Dt12 = t2 − t1 =

2Cr Vin iLr t1

(4)

In this mode, Q2 and Q3 are conducting and the primary winding voltage vcb = vLm1 + vLm2 + vLm3 + vLm4 = 0. No power is transferred to output load in this mode. Thus, the duty cycle loss in this mode is given as

In this mode, vLm2 + vLm4 + vLr = − 2nVo. Thus the inductor current is given as iLr (t) ≃ iLr t2 −

2nVo t − t2 Lr + 2Lm

(5)

Inductor current iLr decreases in this mode. This mode ends at time t3 when Q4 is turned off. The inductor current iLr(t3) is given as iLr t3 ≃ iLr t2 −

2nVo t3 − t2 Lr + 2Lm

(6)

Mode 4 [t3 ≤ t < t4]: At time t3, Q4 is turned off. Since iLr < Io/(2n), diodes D1–D4 are all conducting to commutate the load current. Magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. Diode currents iD1 and iD3 decrease and diode currents iD2 and iD4 increase. Since iLr(t3) > 0, Cr3 and Cr4 are discharged and charged, respectively. Capacitor voltages vCr3 and vCr4 are expressed as iLr t3 iLr t3 t − t3 , vCr4 (t) ≃ t − t3 (7) vCr3 (t) ≃ Vin − 2Cr 2Cr If the energy stored in Lr is greater than the energy stored in Cr3 and Cr4, then Cr3 can be discharged to zero voltage. Therefore the ZVS of Q3 is given in (8). Lr i2Lr t3 . Cr Vin2 2

(8)

This mode ends at time t4 when vCr3 = 0. The time interval in mode 4 approximates Dt34 = t4 − t3 ≃

2Cr Vin iLr t3

(9)

The dead time td between active switches Q3 and Q4 must be greater than the time interval Δt34 in order to turn on Q3 at ZVS. Mode 5 [t4 ≤ t < t5]: At time t4, vCr3 = 0. Since iLr(t4) > 0, the anti-parallel diode of Q3 is conducting. Before iLr is negative, Q3 must be turned on to achieve ZVS. Diodes D1–D4are still in the commutation interval. Thus, the magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. The inductor voltage vLr = − Vin. Thus, the inductor current iLr decreases rapidly. V iLr (t) ≃ iLr t4 − in t − t4 Lr

(10)

This mode ends at time t5 when diode currents iD1 and iD3 are decreased to zero. The inductor current variation ΔiLr in this mode is approximately equal to Io/n. Thus, the time interval in this mode approximates Dt45 = t5 − t4 ≃

L r Io nVin

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(11)

dloss,5 =

Dt45 Lr Io fs ≃ Ts nVin

(12)

where Ts is the switching period and fs is the switching frequency. Mode 6 [t5 ≤ t < t6]: At time t5, diode currents iD1 and iD3 are decreased to zero. Only diodes D2 and D4 are conducting in the secondary side. The magnetising voltages vLm2 = vLm4 = − nVo such that the magnetising currents iLm2 and iLm4 decrease with the slope of − nVo/Lm. Lm1 and Lm3 are operated as the inductors in this mode. The voltage across Lr, Lm1and Lm3 equals 2nVo–Vin < 0. The inductor current iLr decreases linearly. The input power is transferred to output load through Q3, T2, T4, Q2, D2 and D4. This mode ends at time t6 when Q2 is turned off. At time t6, the inductor current iLr is given as V − 2nVo t − t5 iLr t6 ≃ iLr t5 − in Lr + 2Lm 6

(13)

Mode 7 [t6 ≤ t < t7]: At time t6, Q2 is turned off. Since the inductor current iLr(t6) < 0, Cr1 is discharged and Cr2 is charged in this mode. Capacitor voltages vCr1 and vCr2 can be expressed as iLr t6 t − t6 , vCr2 (t) vCr1 (t) ≃ Vin + 2Cr i t ≃ − Lr 6 t − t6 2Cr

(14)

The inductor current iLr is almost constant in this mode. The ZVS condition of Q1 is given in (15).

Lr + 2Lm i2Lr t6 . Cr Vin2 2

(15)

This mode ends at time t7 when vCr1 = 0. The time interval in this mode is given as Dt67 = t7 − t6 =

2Cr Vin −iLr t6

(16)

The dead time td between active switches Q1 and Q2 must be greater than the time interval Δt67 in order to turn on Q1 at ZVS. Mode 8 [t7 ≤ t < t8]: At time t7, vCr1 = 0. Since iLr(t7) ≃iLr(t6) < 0, the anti-parallel diode of Q1 is conducting. Before iLr is positive, Q1 must be turned on to achieve ZVS. In this mode, vLr + vLm1 + vLm3 = 2nVo. Thus, the inductor current iLr increases in this mode. This mode ends at time t8 when Q3 is turned off. The inductor current iLr(t8) is given as iLr t8 ≃ iLr t7 +

2nVo t8 − t7 Lr + 2Lm

(17)

Mode 9 [t8 ≤ t < t9]: At time t8, Q3 is turned off. Diodes D1–D4 are all conducting to commutate the load current. IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

www.ietdl.org Magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. Diode currents iD1 and iD3 increase and diode currents iD2 and iD4 decrease. Since iLr(t8) < 0, Cr3 and Cr4 are charged and discharged, respectively. Capacitor voltages vCr3 and vCr4 are expressed as iLr t8 t − t8 , vCr4 (t) vCr3 (t) ≃ − 2Cr iLr t8 ≃ Vin + t − t8 2Cr

(18)

If the energy stored in Lr is greater than the energy stored in Cr3 and Cr4, then Cr4 can be discharged to zero voltage. Therefore the ZVS of Q4 is given in (19). Lr i2Lr t8 . Cr Vin2 2

(19) Fig. 4 Waveforms of the simpliﬁed main operation modes

This mode ends at time t9 when vCr4 = 0. The time interval in mode 9 approximates Dt89

2Cr Vin = t9 − t8 ≃ −iLr t8

(20)

The dead time td between active switches Q3 and Q4 must be greater than the time interval Δt89 in order to turn on Q4 at ZVS. Mode 10 [t9 ≤ t < Ts + t0]: At time t9, vCr4 = 0. Since iLr(t9) < 0, the anti-parallel diode of Q4 is conducting. Before iLr is positive, Q4 must be turned on to achieve ZVS. Diodes D1–D4are still in the commutation interval. The magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. The inductor voltage vLr = Vin and the inductor current iLr increases rapidly. V iLr (t) ≃ iLr t9 + in t − t9 Lr

Lr Io nVin

Vo + Vf d − dloss d − = ≃ Vin n

(22)

Dt90 Lr Io fs ≃ = dloss,5 Ts nVin

(25)

The output voltage is a function of duty cycle δ, input voltage Vin, switching frequency fs, inductance Lr and load current Io. If the ripple magnetising current ΔiLm1 in time [t0, t1] is less than the diode current reﬂected to primary side iD1/n, then the ripple inductor current ΔiLr in time [t0, t1] can be expressed as Vin − 2n Vo + Vf LI f d − r o s Ts DiLr ≃ nVin 2Lm

(26)

≃ DiD /(2n) = rIo /(2n)

Circuit characteristics

Since the transition intervals in modes 2, 4, 7 and 9 are much less than the turn-on time of active switches, we can neglect the transition intervals in these modes. However, we need to consider the effect of duty cycle losses at modes 5 and 10 shown in Fig. 3. Fig 4 gives the main six operating IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

(24)

(23)

Then the operating modes of the proposed converter in a switching period are completed.

4

Lr Io fs / nVin n

Vin L r Io f s Vo = − Vf d− n nVin

In this mode, Q1 and Q4 are conducting and the primary winding voltage vLm1 + vLm2 + vLm3 + vLm4 = 0. Thus, the duty cycle loss in mode 10 is given as

dloss,10 =

where Vf is the voltage drop on diodes D1–D4. Therefore the output voltage Vo is expressed as

(21)

This mode ends at time Ts + t0 when diode currents iD2 and iD4 are decreased to zero. The inductor current variation ΔiLr in this mode is approximately equal to Io/n. Thus, the time interval in this mode approximates Dt90 = Ts + t0 − t9 ≃

modes during one switching cycle. In time interval [t5, t1], the AC side voltage vab = Vin with duty cycle, δ. However, there is no power transfer from input to output in [t5, t0] and [t2, t3]. In the steady state, the resultant output diode current iD(t0) should be equal to iD(t3). Thus we can obtain the DC voltage conversion ratio of the proposed converter.

where r is the ripple current ratio of load current. From (24) and (26), the magnetising inductance Lm of T1–T4 is given as

Lm ≃

n2 Vo + Vf 1 − 2 d − Lr Io fs / nVin rIo fs

(27)

The average diode currents are expressed as ID1 = ID2 = ID3 = ID4 = Io /4

(28) 509

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www.ietdl.org The voltage stresses of rectiﬁer diodes D1–D4 are given as

Thus, the inductance Lr is expressed as

VD1,stress = VD2,stress = VD3,stress = VD4,stress = Vin /(2n) (29) In Fig. 4, power is delivered from input source voltage to output load in time intervals [t0, t1] and [t3, t4]. Thus the root-mean-square (rms) values of switching currents iQ1,rms– iQ4,rms can be expressed as iQ1,rms = iQ2,rms = iQ3,rms = iQ4,rms ≃

Io √

2n 2

(30)

The voltage stresses of Q1–Q4 are expressed as VQ1,stress = VQ2,stress = VQ3,stress = VQ4,stress = Vin

(31)

At time t1, the inductor current iLr(t) is approximated as (see (32)) At time t2, the inductor current iLr(t) is approximated as iLr t2 ≃ iLr t1 −

2n Vo + Vf

(0.5 − d)Ts 2Lm V + V o f (1 − 0.5r)Io LI + = × ro 2n Vin Lm

(33)

Lr + 2Lm . Lr .

2Cr Vin2 i2Lr t2

dloss,max =

Io Lr fs Po L r fs ≃ , 0.05 2 nVin,min dmax Vin,min

dmax − dloss,max Vin,min (0.45 − 0.05) × 350 = n≃ Vo + Vf 48 + 1.2 V = 2.846

(36)

(38)

The magnetic core TDK EER-42 with Ae = 194 mm2 and ΔB = 0.3 T is used to design transformers T1–T4. The minimum primary winding turns of T1–T4 are derived as n Vo + Vf 0.5 + dloss,max DBAe fs

(39)

2.846 × (48 + 1.2) × (0.5 + 0.05) ≃ 13.2 = 0.3 × 194 × 10−6 × 100 000 Therefore the actual primary and secondary turns of T1–T4 are np = 40 and ns = 14. From (24), the minimum duty cycle at the maximum input voltage and full load is given as

dmin ≃

(35)

The design procedure of the prototype circuit and experimental results are shown in this section to verify the effectiveness of the proposed converter. The rated power of the prototype circuit is 960 W (48 V/20 A). The input minimum, nominal and maximum voltages are 350, 390 and 400 V, respectively. The switching frequency of PWM signals is 100 kHz. The assumed circuit efﬁciency is 90%. The maximum duty cycle δmax of the proposed converter is 0.45 at minimum input voltage and full-load condition. We assumed that the maximum duty cycle loss δloss is < 5% at full load.

(37)

The actual resonant inductance Lr in the prototype is 26 μH. From (24), the turn ratio of T1–T4 is expressed as

(34)

5 Design procedure and experiment verification

2 0.05dmax Vin,min 0.05 × 0.45 × 3502 = Po fs 960 × 100 000

≃ 28.7 mH

np ≥

Thus the ZVS conditions of active switches in leading leg such as Q1 and Q2 and in lagging leg such as Q3 and Q4 can be given in (34) and (35) res 2Cr Vin2 i2Lr t1

Lr ,

n Vo + Vf Vin,max

+

L r Io f s nVin,max

=

(40/14) × (48 + 1.2) 400

+

26 × 10−6 × 20 × 100 000 ≃ 0.396 (40/14) × 400

The ripple current ratio r of iD is equal to 0.2. Based on (27), the magnetising inductance Lm of T1–T4 is expressed as

Lm ≃

n2 Vo + Vf 1 − 2 dmin − Lr Io fs / nVin,max rIo fs

≃ 300 mH (41) The IRFP460 MOSFETs with VDS = 500 V, ID,rms = 20 A, RDS,on = 0.27 Ω and Coss = 480 pF at 25 V are used for switches Q1–Q4. Power switches in lagging leg are designed to have ZVS turn-on from 50% load to full load at the maximum input voltage. Since Coss of the IRFP460 MOSFETs is 480 pF at 25 V, the equivalent output

ID1 Vin − 2n Vo + Vf LI f + iLr t1 ≃ d − r o s Ts 2n nVin 2Lm (1 − 0.5r)Io n Vo + Vf Lr Io fs L r Io f s + × d− Ts = 1−2 d− 2n nVin nVin 2Lm 510 & The Institution of Engineering and Technology 2013

(40)

(32)

IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

www.ietdl.org From (37) and (44), the selected resonant inductor Lr = 26 μH can meet ZVS condition of Q3 and Q4 from 50 to 100% load conditions. It is clear that ZVS condition of Q1 and Q2 in leading leg from 50 to 100% load conditions is also achieved based on equation in (34). The average currents and voltage stresses of rectiﬁer diodes are given as

capacitance Cr at maximum input voltage is given as

4 25 4 25 Cr ≃ Coss,25 = × 480 × 3 vQ1,ds 3 400/2 ≃ 226 pF

(42) ID1 = ID2 = ID3 = ID4 = Io /4 = 5 A, VD1,stress

From (33), the inductor current iLr(t2) at 50% load can be obtained as (see (43)) From (35), the required resonant inductance to achieve ZVS of Q3 and Q4 from 50% load to full load is obtained as Lr .

2 2Cr Vin,max i2Lr,50% t2

=

2 × 226 × 10−12 × 4002 1.682

= 25.6 mH

(44)

Fig. 5 Photograph of the prototype circuit

= VD2,stress = VD3,stress = VD4,stress = Vin,max /(2n) = 70 V (45) The BYV72EW-200 fast recovery rectiﬁer with VRRM = 200 V and IF = 30 A are used for D1–D4 at the secondary side. The capacitance of output capacitor Co is 3600 μF. Experiments with the circuit parameters derived in the previous section were provided to verify the effectiveness and performance of the proposed converter. Fig. 5 shows the photograph of the prototype circuit. Fig. 6 shows the measured gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with Vin = 350 V and 50% load and full-load conditions. It is clear that the gate voltage vQ4,gs lags vQ1,gs, and vQ3,gs lags vQ2,gs. The duty cycle loss in full load is more serious than the duty cycle loss in half-load condition. Therefore the AC side voltage vab has large duty cycle ratio in full-load condition. In the same manner, Figs. 7 and 8 show the measured gate voltages, AC side voltage and transformer primary side current at nominal input voltage and maximum input voltage, respectively. Fig. 9 gives the measured gate voltage, drain voltage and drain current of switch Q1 at nominal input voltage with 50 and 100% load conditions. Before switch Q1 is turned on, drain current is negative to discharge the drain-to-source capacitor. Thus, the drain

Fig. 6 Experimental waveforms of gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with minimum input voltage Vin = 350 V and a 50% load b full load

(1 − 0.5r)Io,50% + iLr,50% t2 = 2n

Vo + Vf Lm

×

Lr Io,50% Vin,max

(43)

(1 − 0.5 × 0.2) × 10 (48 + 1.2) 26 × 10−6 × 10 + ≃ 1.68 A = × 2 × 40/14 300 × 10−6 400 IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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Fig. 7 Experimental waveforms of gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with nominal input voltage Vin = 390 V and a 50% load b Full load

Fig. 8 Experimental waveforms of gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with nominal input voltage Vin = 400 V and a 50% load b Full load

Fig. 9 Measured waveforms of gate voltage, drain voltage and switch current of Q1 at nominal input voltage and a 50% load b 100% load 512 & The Institution of Engineering and Technology 2013

IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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Fig. 10 Measured waveforms of gate voltage, drain voltage and switch current of Q2 at nominal input voltage and a 50% load b 100% load

Fig. 11 Measured waveforms of gate voltage, drain voltage and switch current of Q3 at nominal input voltage and a 50% load b 100% load

Fig. 12 Measured waveforms of gate voltage, drain voltage and switch current of Q4 at nominal input voltage and a 50% load b 100% load IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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Fig. 13 Measured waveforms of gate voltages vQ1, gs and vQ4, gs, diode currents iD1–iD4 and the resultant output current iD at nominal input voltage and a 50% load b Full load

stress of each MOSFET is clamped at input voltage. The energy stored in the resonant inductance and magnetising inductance is used to achieve ZVS turn-on of MOSFETs at the leading leg. However, only resonant inductance is used to achieve ZVS turn-on of MOSFETs at the lagging leg. The drawback of the proposed converter is that the size of the proposed circuit with four ferrite cores is larger than the interleaved phase-shift full bridge converter with two ferrite cores and two power iron cores. A design example of a 960 W prototype circuit is presented and the system performance is veriﬁed by the experiments. Fig. 14 Measured circuit efﬁciencies of the proposed converter at different load conditions and nominal input voltage case

voltage can be decreased to zero voltage and Q1 is turned on at ZVS for both 50 and 100% loads. In the same manner, Figs. 10–12 show the measured gate voltage, drain voltage and switch current of Q2–Q4 at nominal input voltage with 50 and 100% load conditions. Active switches Q2–Q4 are also turned on at ZVS for both 50 and 100% loads. Fig. 13 gives the measured waveforms of gate voltages vQ1,gs and vQ4,gs, diode currents iD1–iD4 and the resultant output current iD at nominal input voltage with 50 and 100% loads. It is clear that the output diode currents iD1–iD4 are balanced. The measured circuit efﬁciencies at different load conditions are shown in Fig. 14. The measured circuit efﬁciency is 87.1, 91.5 and 90.2% at 20, 50 and 100% load with nominal input voltage.

6

Conclusion

A full-bridge converter without output inductor is presented to achieve ZVS turn-on for all power switches from 50 to 100% load. Four transformers are connected in series at the primary side and connected in parallel at the secondary side to share the load current. Each transformer can be operated as either an isolated transformer or an inductor such that no output inductor is needed at the output side. The voltage 514 & The Institution of Engineering and Technology 2013

7

References

1 Garcia, O., Cobos, J.A., Prieto, R., Alou, P., Uceda, J.: ‘Single phase power factor correction: a survey’, IEEE Trans. Power Electron., 2003, 18, (3), pp. 749–755 2 Baumann, M., Kolar, J.W.: ‘Parallel connection of two three-phase three-switch buck-type unity-power-factor rectiﬁer systems with DC-link current balancing’, IEEE Trans. Ind. Electron., 2007, 54, (6), pp. 3042–3053 3 Nussbaumer, T., Raggl, K., Kolar, J.W.: ‘Design guidelines for interleaved single-phase boost PFC circuits’, IEEE Trans. Ind. Electron., 2009, 56, (7), pp. 2559–2573 4 Ertl, H., Kolar, J.W., Zach, F.C.: ‘A novel multicell DC–AC converter for applications in renewable energy systems’, IEEE Trans. Ind. Electron., 2002, 49, (5), pp. 1048–1057 5 Pinheiro, J.R., Barbi, I.: ‘The three-level ZVS PWM converter – a new concept in high-voltage dc-to-dc conversion’. Proc. IEEE IECON’92, 1992, pp. 173–178 6 Jin, K., Ruan, X.: ‘Zero-voltage-switching multiresonant three-level converters’, IEEE Trans. Ind. Electron., 2007, 54, (3), pp. 1705–1715 7 Yang, S., Abe, S., Shoyama, M.: ‘Design consideration of ﬂat transformer in LLC resonant converter for low core loss’. Proc. IEEE IPEC, 2010, pp. 343–348 8 Xie, X., Zhang, J., Chen, Z., Zhao, Z., Qian, Z.: ‘Analysis and optimization of LLC resonant converter with a novel over-current protection circuit’, IEEE Trans. Power Electron., 2007, 22, (2), pp. 435–443 9 Lin, B.R., Wu, S.F.: ‘Implementation of a series resonant converter with series–parallel transformers’, IET Proc. – Power Electron., 2011, 4, (8), pp. 919–926 10 Lin, B.R., Dong, J.Y.P.: ‘Analysis and implementation of an active clamping zero-voltage turn-on switching/zero-current turn-off switching converter’, IET Proc. – Power Electron., 2010, 3, (3), pp. 429–437 IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

www.ietdl.org 11 Torrico-Bascop, R., Barbi, N.: ‘A double ZVS-PWM active-clamping forward converter: analysis, design, and experimentation’, IEEE Trans. Power Electron., 2001, 16, (6), pp. 745–751 12 Papanikolaou, N.P., Tatakis, E.C.: ‘Active voltage clamp in ﬂyback converters operating in CCM mode under wide load variation’, IEEE Trans. Ind. Electron., 2004, 51, (3), pp. 632–640 13 Choi, B., Lim, W., Bang, S., Choi, S.: ‘Small-signal analysis and control design of asymmetrical half-bridge DC–DC converters’, IEEE Trans. Ind. Electron., 2006, 53, (2), pp. 511–520 14 Mishima, T., Nakaoka, M.: ‘A novel high-frequency transformer-linked soft-switching half-bridge DC–DC converter with constant-frequency

IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

asymmetrical PWM scheme’, IEEE Trans. Ind. Electron., 2009, 56, (8), pp. 2961–2969 15 Lin, B.-R., Tseng, C.-H.: ‘Analysis of parallel-connected asymmetrical soft-switching converter’, IEEE Trans. Ind. Electron., 2009, 54, (3), pp. 1642–1653 16 Yungtack, J., Jovanovic, M.M., Chang, Y.M.: ‘A new ZVS–PWM full-bridge converter’, IEEE Trans. Power Electron., 2003, 18, (5), pp. 1122–1129 17 Jiang, Y., Chen, Z., Pan, J.: ‘Zero-voltage switching phase shift full-bridge step-up converter with integrated magnetic structure’, IET Proc. – Power Electron., 2010, 3, (3), pp. 732–739

515

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ISSN 1755-4535

Zero-voltage switching full-bridge DC/DC converter with parallel-connected output and without output inductor Bor-Ren Lin, Tung-Yuan Shiau Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: [email protected]

Abstract: This study presents a soft-switching converter without output inductor. The features of the proposed converter are zero-voltage switching (ZVS) for all power switches, load current sharing and high circuit efﬁciency. Full-bridge converter with phase-shift pulse-width modulation (PWM) is adopted to regulate the output voltage. Based on the resonant behaviour by the output capacitance of MOSFETs and the resonant inductance, active switches can be turned on at ZVS during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The voltage stress of power switches is clamped to DC bus voltage. Four transformers are connected in series in the primary side. Each transformer can be operated as an inductor to smooth the output current or a transformer to achieve electric isolation and power transfer from input side to output side. Therefore no output inductor is needed in the secondary side. Two centre-tapped rectiﬁers connected in parallel are used in the secondary side to achieve load current sharing. Finally, experiments based on a 960 W (48 V/20 A) laboratory prototype are provided to demonstrate the performance of proposed converter.

1

Introduction

Switching converters with high-efﬁciency and high-power density have been demanded for modern power supply units such as server systems, data storage systems, telecommunication system, cloud power systems and medical power systems. To meet the climate saver computing initiative (CSCI) or environment protection agency (EPA) requirements, two-stage AC/DC converters with power factor correction (PFC) are usually adopted to reduce AC current harmonics and reactive power and to regulate output DC voltage against the AC input voltage and load variations. PFC converters [1–3] with boost-type technique and continuous conduction mode are widely used in the front stage to draw a sinusoidal line current from AC utility in order to meet the IEC61000–3-2 limits. In the second stage, three-level DC/DC converters [4–6], resonant converters [7–9], active clamp converters [10–12], asymmetric half-bridge converters [13–15] and full-bridge converters [16, 17] have been proposed to regulate the output voltage with the wide load ranges and input voltage variations. Three-level converters use the clamp diodes or clamp capacitors to reduce the voltage stress on active switches for high-voltage applications. However, the disadvantages of three-level converters are too many active and passive components, high circuit cost and the difﬁcult control scheme. Resonant converters can achieve zero-voltage switching (ZVS) on MOSFETs with the wide load ranges. However, the transformer in resonant converters cannot be designed at the optimal condition IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

because of using the variable switching frequency to regulate output voltage. Active clamp converters can reduce the switching losses with the auxiliary switch and clamp capacitor. The voltage stress of power switches in active clamp topologies cannot be reduced to a safety region if the maximum duty ratio is >0.5. Asymmetric half-bridge converters have the advantages of ZVS turn-on and low-voltage stress on power switches. However, the drawbacks are the average DC magnetising current on the transformer is not zero and the voltage stresses on the rectiﬁer diodes are unbalanced. This paper presents a soft-switching full-bridge converter without output inductor. Two centre-tapped rectiﬁers are used in the output side to reduce the current stress of the secondary windings. To balance the output currents of two centre-tapped rectiﬁers, the transformer primary windings are connected in series. For each centre-tapped rectiﬁer, there are two transformers connected in series. One transformer works as a forward-type transformer, and the other transformer works as an inductor. Thus, no output inductor is needed at the secondary side and the output current before the output capacitor is a continuous waveform. Based on the pulse-width modulation (PWM) with phase-shifted technique, active switches in the leading leg can be turned on at ZVS with the wide load ranges because of the energy stored in the resonant inductance and magnetising inductance. The active switches in the lagging leg can also achieve ZVS in the desired load range with the selected resonant inductance. Thus, the switching losses of active switches are reduced. The circuit conﬁguration, 505

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www.ietdl.org principle of operation, circuit characteristics and design procedure of the proposed converter are presented in detail. Finally, experiments, based on a 960 W prototype, are presented to verify the effectiveness of the proposed converter.

2

Circuit configuration

Fig. 1 gives the circuit conﬁguration of the proposed ZVS converter. The input DC bus voltage is obtained from a power factor corrector. The input DC bus voltage Vin is usually regulated at 390 V for universal single-phase utility voltage. Q1, Q2, Q3 and Q4 are power MOSFETs. Lr is the resonant inductance. Cr1–Cr4 are output capacitances of power MOSFETs Q1–Q4, respectively. D1–D4 are rectiﬁer diodes at output side. Lm1–Lm4 are the magnetising inductances of transformers T1–T4, respectively. Co is the output capacitance. Full-bridge converter is used to regulate output voltage. Two centre-tapped rectiﬁers are adopted to share load current. In order to balance two centre-tapped rectiﬁers, the primary windings of transformers T1–T4 are connected in series. T1–T4 can be operated as transformers to achieve electric isolation and power transfer or operated as inductors to smooth output current. Therefore no output inductor is necessary in the proposed converter. The phase-shift PWM scheme is used to control power MOSFETs. Based on the resonant behaviour by Lr and Cr1–Cr4 at the transition interval, Q1–Q4 can be turned on at ZVS. Thus, the switching losses of active switches Q1–Q4 can be reduced. The voltage stress of each power MOSFET is equal to input DC bus voltage. Therefore MOSFETs with 500 or 600 V voltage stress can be used in the proposed converter.

3

System analysis and operation principle

Before the discussion the operation principle, some assumptions are made to simplify the system analysis of the proposed converter. 1. Four transformers T1–T4 have the same magnetising inductances Lm1 = Lm2 = Lm3 = Lm4 = Lm and turns ratio n = np/ns; 2. Q1–Q4 are ideal and have the same output capacitances Cr1 = Cr2 = Cr3 = Cr4 = Cr; 3. Diodes D1–D4 are ideal; 4. Resonant inductance Lr < < Lm; 5. Co is large enough to be a constant voltage; 6. The energy stored in the resonant inductance Lr is greater than the energy stored in resonant capacitors Cr1–Cr4 such that the ZVS turn-on of all switches can be achieved.

switching period. The theoretical PWM waveforms of the proposed converter are shown in Fig. 2. The duty cycle of each switch is equal to 0.5. The PWM signals of Q3 and Q4 are phase-shifted with respective to the PWM signals of Q2 and Q1. Fig. 3 gives the equivalent circuits of ten operation modes. Before time t0, Q1 and Q4 are both in the on-state and diodes D1–D4 are conducting. Mode 1 [t0 ≤ t < t1]: At time t0, diode currents iD2 and iD4 are decreased to zero. Only diodes D1 and D3 are conducting in this mode. The magnetising voltage vLm1 = vLm3 = nVo. Thus, the magnetising currents iLm1 and iLm3 increase with the slope of nVo/Lm. Lm2 and Lm4 operate as the inductors in this mode. The voltage across inductors Lr, Lm2and Lm4 equals Vin–2nVo. The inductor current iLr increases linearly with the slope of (Vin–2nVo)/(Lr + 2Lm). The energy stored in Lr, Lm2 and Lm4 is increasing. The input power is transferred to output load through Q1, T1, T3, Q4, D1 and D3. This mode ends at time t1 when Q1 is turned off. At time t1, the inductor current iLr is given as V − 2nVo t1 − t0 iLr t1 ≃ iLr t0 + in Lr + 2Lm

(1)

Mode 2 [t1 ≤ t < t2]: At time t1, Q1 is turned off. Since the inductor current iLr(t1) > 0, Cr1 is charged and Cr2 is discharged in this mode. Since Cr1 and Cr2 are about hundreds of pico-farad, vCr1 and vCr2 can be expressed as iLr t1 iLr t1 vCr1 (t) ≃ t − t1 , vCr2 (t) ≃ Vin − t − t1 (2) 2Cr 2Cr The inductor current iLr is almost constant in this mode. The ZVS condition of Q2 is given in (3).

Lr + 2Lm i2Lr t1 . Cr Vin2 2

(3)

This mode ends at time t2 when vCr2 = 0. Mode 3 [t2 ≤ t < t3]: At time t2, vCr2 = 0. Since iLr(t2)≃ iLr(t1) > 0, the anti-parallel diode of Q2 is conducting. Therefore Q2 can be turned on at ZVS in this moment. The dead time between Q1 and Q2 should be greater than the

Based on the on/off states of Q1–Q4 and D1–D4, the proposed converter has ten operating modes during one

Fig. 1 Proposed soft-switching converter without output inductor 506 & The Institution of Engineering and Technology 2013

Fig. 2 Key waveforms of the proposed converter IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

www.ietdl.org

Fig. 3 Operation modes of the proposed converter in one switching cycle a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9 j Mode 10

IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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www.ietdl.org time interval in mode 2. td ≥ Dt12 = t2 − t1 =

2Cr Vin iLr t1

(4)

In this mode, Q2 and Q3 are conducting and the primary winding voltage vcb = vLm1 + vLm2 + vLm3 + vLm4 = 0. No power is transferred to output load in this mode. Thus, the duty cycle loss in this mode is given as

In this mode, vLm2 + vLm4 + vLr = − 2nVo. Thus the inductor current is given as iLr (t) ≃ iLr t2 −

2nVo t − t2 Lr + 2Lm

(5)

Inductor current iLr decreases in this mode. This mode ends at time t3 when Q4 is turned off. The inductor current iLr(t3) is given as iLr t3 ≃ iLr t2 −

2nVo t3 − t2 Lr + 2Lm

(6)

Mode 4 [t3 ≤ t < t4]: At time t3, Q4 is turned off. Since iLr < Io/(2n), diodes D1–D4 are all conducting to commutate the load current. Magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. Diode currents iD1 and iD3 decrease and diode currents iD2 and iD4 increase. Since iLr(t3) > 0, Cr3 and Cr4 are discharged and charged, respectively. Capacitor voltages vCr3 and vCr4 are expressed as iLr t3 iLr t3 t − t3 , vCr4 (t) ≃ t − t3 (7) vCr3 (t) ≃ Vin − 2Cr 2Cr If the energy stored in Lr is greater than the energy stored in Cr3 and Cr4, then Cr3 can be discharged to zero voltage. Therefore the ZVS of Q3 is given in (8). Lr i2Lr t3 . Cr Vin2 2

(8)

This mode ends at time t4 when vCr3 = 0. The time interval in mode 4 approximates Dt34 = t4 − t3 ≃

2Cr Vin iLr t3

(9)

The dead time td between active switches Q3 and Q4 must be greater than the time interval Δt34 in order to turn on Q3 at ZVS. Mode 5 [t4 ≤ t < t5]: At time t4, vCr3 = 0. Since iLr(t4) > 0, the anti-parallel diode of Q3 is conducting. Before iLr is negative, Q3 must be turned on to achieve ZVS. Diodes D1–D4are still in the commutation interval. Thus, the magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. The inductor voltage vLr = − Vin. Thus, the inductor current iLr decreases rapidly. V iLr (t) ≃ iLr t4 − in t − t4 Lr

(10)

This mode ends at time t5 when diode currents iD1 and iD3 are decreased to zero. The inductor current variation ΔiLr in this mode is approximately equal to Io/n. Thus, the time interval in this mode approximates Dt45 = t5 − t4 ≃

L r Io nVin

508 & The Institution of Engineering and Technology 2013

(11)

dloss,5 =

Dt45 Lr Io fs ≃ Ts nVin

(12)

where Ts is the switching period and fs is the switching frequency. Mode 6 [t5 ≤ t < t6]: At time t5, diode currents iD1 and iD3 are decreased to zero. Only diodes D2 and D4 are conducting in the secondary side. The magnetising voltages vLm2 = vLm4 = − nVo such that the magnetising currents iLm2 and iLm4 decrease with the slope of − nVo/Lm. Lm1 and Lm3 are operated as the inductors in this mode. The voltage across Lr, Lm1and Lm3 equals 2nVo–Vin < 0. The inductor current iLr decreases linearly. The input power is transferred to output load through Q3, T2, T4, Q2, D2 and D4. This mode ends at time t6 when Q2 is turned off. At time t6, the inductor current iLr is given as V − 2nVo t − t5 iLr t6 ≃ iLr t5 − in Lr + 2Lm 6

(13)

Mode 7 [t6 ≤ t < t7]: At time t6, Q2 is turned off. Since the inductor current iLr(t6) < 0, Cr1 is discharged and Cr2 is charged in this mode. Capacitor voltages vCr1 and vCr2 can be expressed as iLr t6 t − t6 , vCr2 (t) vCr1 (t) ≃ Vin + 2Cr i t ≃ − Lr 6 t − t6 2Cr

(14)

The inductor current iLr is almost constant in this mode. The ZVS condition of Q1 is given in (15).

Lr + 2Lm i2Lr t6 . Cr Vin2 2

(15)

This mode ends at time t7 when vCr1 = 0. The time interval in this mode is given as Dt67 = t7 − t6 =

2Cr Vin −iLr t6

(16)

The dead time td between active switches Q1 and Q2 must be greater than the time interval Δt67 in order to turn on Q1 at ZVS. Mode 8 [t7 ≤ t < t8]: At time t7, vCr1 = 0. Since iLr(t7) ≃iLr(t6) < 0, the anti-parallel diode of Q1 is conducting. Before iLr is positive, Q1 must be turned on to achieve ZVS. In this mode, vLr + vLm1 + vLm3 = 2nVo. Thus, the inductor current iLr increases in this mode. This mode ends at time t8 when Q3 is turned off. The inductor current iLr(t8) is given as iLr t8 ≃ iLr t7 +

2nVo t8 − t7 Lr + 2Lm

(17)

Mode 9 [t8 ≤ t < t9]: At time t8, Q3 is turned off. Diodes D1–D4 are all conducting to commutate the load current. IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

www.ietdl.org Magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. Diode currents iD1 and iD3 increase and diode currents iD2 and iD4 decrease. Since iLr(t8) < 0, Cr3 and Cr4 are charged and discharged, respectively. Capacitor voltages vCr3 and vCr4 are expressed as iLr t8 t − t8 , vCr4 (t) vCr3 (t) ≃ − 2Cr iLr t8 ≃ Vin + t − t8 2Cr

(18)

If the energy stored in Lr is greater than the energy stored in Cr3 and Cr4, then Cr4 can be discharged to zero voltage. Therefore the ZVS of Q4 is given in (19). Lr i2Lr t8 . Cr Vin2 2

(19) Fig. 4 Waveforms of the simpliﬁed main operation modes

This mode ends at time t9 when vCr4 = 0. The time interval in mode 9 approximates Dt89

2Cr Vin = t9 − t8 ≃ −iLr t8

(20)

The dead time td between active switches Q3 and Q4 must be greater than the time interval Δt89 in order to turn on Q4 at ZVS. Mode 10 [t9 ≤ t < Ts + t0]: At time t9, vCr4 = 0. Since iLr(t9) < 0, the anti-parallel diode of Q4 is conducting. Before iLr is positive, Q4 must be turned on to achieve ZVS. Diodes D1–D4are still in the commutation interval. The magnetising voltages vLm1 = vLm3 = nVo and vLm2 = vLm4 = − nVo. The inductor voltage vLr = Vin and the inductor current iLr increases rapidly. V iLr (t) ≃ iLr t9 + in t − t9 Lr

Lr Io nVin

Vo + Vf d − dloss d − = ≃ Vin n

(22)

Dt90 Lr Io fs ≃ = dloss,5 Ts nVin

(25)

The output voltage is a function of duty cycle δ, input voltage Vin, switching frequency fs, inductance Lr and load current Io. If the ripple magnetising current ΔiLm1 in time [t0, t1] is less than the diode current reﬂected to primary side iD1/n, then the ripple inductor current ΔiLr in time [t0, t1] can be expressed as Vin − 2n Vo + Vf LI f d − r o s Ts DiLr ≃ nVin 2Lm

(26)

≃ DiD /(2n) = rIo /(2n)

Circuit characteristics

Since the transition intervals in modes 2, 4, 7 and 9 are much less than the turn-on time of active switches, we can neglect the transition intervals in these modes. However, we need to consider the effect of duty cycle losses at modes 5 and 10 shown in Fig. 3. Fig 4 gives the main six operating IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

(24)

(23)

Then the operating modes of the proposed converter in a switching period are completed.

4

Lr Io fs / nVin n

Vin L r Io f s Vo = − Vf d− n nVin

In this mode, Q1 and Q4 are conducting and the primary winding voltage vLm1 + vLm2 + vLm3 + vLm4 = 0. Thus, the duty cycle loss in mode 10 is given as

dloss,10 =

where Vf is the voltage drop on diodes D1–D4. Therefore the output voltage Vo is expressed as

(21)

This mode ends at time Ts + t0 when diode currents iD2 and iD4 are decreased to zero. The inductor current variation ΔiLr in this mode is approximately equal to Io/n. Thus, the time interval in this mode approximates Dt90 = Ts + t0 − t9 ≃

modes during one switching cycle. In time interval [t5, t1], the AC side voltage vab = Vin with duty cycle, δ. However, there is no power transfer from input to output in [t5, t0] and [t2, t3]. In the steady state, the resultant output diode current iD(t0) should be equal to iD(t3). Thus we can obtain the DC voltage conversion ratio of the proposed converter.

where r is the ripple current ratio of load current. From (24) and (26), the magnetising inductance Lm of T1–T4 is given as

Lm ≃

n2 Vo + Vf 1 − 2 d − Lr Io fs / nVin rIo fs

(27)

The average diode currents are expressed as ID1 = ID2 = ID3 = ID4 = Io /4

(28) 509

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www.ietdl.org The voltage stresses of rectiﬁer diodes D1–D4 are given as

Thus, the inductance Lr is expressed as

VD1,stress = VD2,stress = VD3,stress = VD4,stress = Vin /(2n) (29) In Fig. 4, power is delivered from input source voltage to output load in time intervals [t0, t1] and [t3, t4]. Thus the root-mean-square (rms) values of switching currents iQ1,rms– iQ4,rms can be expressed as iQ1,rms = iQ2,rms = iQ3,rms = iQ4,rms ≃

Io √

2n 2

(30)

The voltage stresses of Q1–Q4 are expressed as VQ1,stress = VQ2,stress = VQ3,stress = VQ4,stress = Vin

(31)

At time t1, the inductor current iLr(t) is approximated as (see (32)) At time t2, the inductor current iLr(t) is approximated as iLr t2 ≃ iLr t1 −

2n Vo + Vf

(0.5 − d)Ts 2Lm V + V o f (1 − 0.5r)Io LI + = × ro 2n Vin Lm

(33)

Lr + 2Lm . Lr .

2Cr Vin2 i2Lr t2

dloss,max =

Io Lr fs Po L r fs ≃ , 0.05 2 nVin,min dmax Vin,min

dmax − dloss,max Vin,min (0.45 − 0.05) × 350 = n≃ Vo + Vf 48 + 1.2 V = 2.846

(36)

(38)

The magnetic core TDK EER-42 with Ae = 194 mm2 and ΔB = 0.3 T is used to design transformers T1–T4. The minimum primary winding turns of T1–T4 are derived as n Vo + Vf 0.5 + dloss,max DBAe fs

(39)

2.846 × (48 + 1.2) × (0.5 + 0.05) ≃ 13.2 = 0.3 × 194 × 10−6 × 100 000 Therefore the actual primary and secondary turns of T1–T4 are np = 40 and ns = 14. From (24), the minimum duty cycle at the maximum input voltage and full load is given as

dmin ≃

(35)

The design procedure of the prototype circuit and experimental results are shown in this section to verify the effectiveness of the proposed converter. The rated power of the prototype circuit is 960 W (48 V/20 A). The input minimum, nominal and maximum voltages are 350, 390 and 400 V, respectively. The switching frequency of PWM signals is 100 kHz. The assumed circuit efﬁciency is 90%. The maximum duty cycle δmax of the proposed converter is 0.45 at minimum input voltage and full-load condition. We assumed that the maximum duty cycle loss δloss is < 5% at full load.

(37)

The actual resonant inductance Lr in the prototype is 26 μH. From (24), the turn ratio of T1–T4 is expressed as

(34)

5 Design procedure and experiment verification

2 0.05dmax Vin,min 0.05 × 0.45 × 3502 = Po fs 960 × 100 000

≃ 28.7 mH

np ≥

Thus the ZVS conditions of active switches in leading leg such as Q1 and Q2 and in lagging leg such as Q3 and Q4 can be given in (34) and (35) res 2Cr Vin2 i2Lr t1

Lr ,

n Vo + Vf Vin,max

+

L r Io f s nVin,max

=

(40/14) × (48 + 1.2) 400

+

26 × 10−6 × 20 × 100 000 ≃ 0.396 (40/14) × 400

The ripple current ratio r of iD is equal to 0.2. Based on (27), the magnetising inductance Lm of T1–T4 is expressed as

Lm ≃

n2 Vo + Vf 1 − 2 dmin − Lr Io fs / nVin,max rIo fs

≃ 300 mH (41) The IRFP460 MOSFETs with VDS = 500 V, ID,rms = 20 A, RDS,on = 0.27 Ω and Coss = 480 pF at 25 V are used for switches Q1–Q4. Power switches in lagging leg are designed to have ZVS turn-on from 50% load to full load at the maximum input voltage. Since Coss of the IRFP460 MOSFETs is 480 pF at 25 V, the equivalent output

ID1 Vin − 2n Vo + Vf LI f + iLr t1 ≃ d − r o s Ts 2n nVin 2Lm (1 − 0.5r)Io n Vo + Vf Lr Io fs L r Io f s + × d− Ts = 1−2 d− 2n nVin nVin 2Lm 510 & The Institution of Engineering and Technology 2013

(40)

(32)

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www.ietdl.org From (37) and (44), the selected resonant inductor Lr = 26 μH can meet ZVS condition of Q3 and Q4 from 50 to 100% load conditions. It is clear that ZVS condition of Q1 and Q2 in leading leg from 50 to 100% load conditions is also achieved based on equation in (34). The average currents and voltage stresses of rectiﬁer diodes are given as

capacitance Cr at maximum input voltage is given as

4 25 4 25 Cr ≃ Coss,25 = × 480 × 3 vQ1,ds 3 400/2 ≃ 226 pF

(42) ID1 = ID2 = ID3 = ID4 = Io /4 = 5 A, VD1,stress

From (33), the inductor current iLr(t2) at 50% load can be obtained as (see (43)) From (35), the required resonant inductance to achieve ZVS of Q3 and Q4 from 50% load to full load is obtained as Lr .

2 2Cr Vin,max i2Lr,50% t2

=

2 × 226 × 10−12 × 4002 1.682

= 25.6 mH

(44)

Fig. 5 Photograph of the prototype circuit

= VD2,stress = VD3,stress = VD4,stress = Vin,max /(2n) = 70 V (45) The BYV72EW-200 fast recovery rectiﬁer with VRRM = 200 V and IF = 30 A are used for D1–D4 at the secondary side. The capacitance of output capacitor Co is 3600 μF. Experiments with the circuit parameters derived in the previous section were provided to verify the effectiveness and performance of the proposed converter. Fig. 5 shows the photograph of the prototype circuit. Fig. 6 shows the measured gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with Vin = 350 V and 50% load and full-load conditions. It is clear that the gate voltage vQ4,gs lags vQ1,gs, and vQ3,gs lags vQ2,gs. The duty cycle loss in full load is more serious than the duty cycle loss in half-load condition. Therefore the AC side voltage vab has large duty cycle ratio in full-load condition. In the same manner, Figs. 7 and 8 show the measured gate voltages, AC side voltage and transformer primary side current at nominal input voltage and maximum input voltage, respectively. Fig. 9 gives the measured gate voltage, drain voltage and drain current of switch Q1 at nominal input voltage with 50 and 100% load conditions. Before switch Q1 is turned on, drain current is negative to discharge the drain-to-source capacitor. Thus, the drain

Fig. 6 Experimental waveforms of gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with minimum input voltage Vin = 350 V and a 50% load b full load

(1 − 0.5r)Io,50% + iLr,50% t2 = 2n

Vo + Vf Lm

×

Lr Io,50% Vin,max

(43)

(1 − 0.5 × 0.2) × 10 (48 + 1.2) 26 × 10−6 × 10 + ≃ 1.68 A = × 2 × 40/14 300 × 10−6 400 IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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Fig. 7 Experimental waveforms of gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with nominal input voltage Vin = 390 V and a 50% load b Full load

Fig. 8 Experimental waveforms of gate voltages of Q1–Q4, AC side voltage vab and transformer primary current iLr with nominal input voltage Vin = 400 V and a 50% load b Full load

Fig. 9 Measured waveforms of gate voltage, drain voltage and switch current of Q1 at nominal input voltage and a 50% load b 100% load 512 & The Institution of Engineering and Technology 2013

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Fig. 10 Measured waveforms of gate voltage, drain voltage and switch current of Q2 at nominal input voltage and a 50% load b 100% load

Fig. 11 Measured waveforms of gate voltage, drain voltage and switch current of Q3 at nominal input voltage and a 50% load b 100% load

Fig. 12 Measured waveforms of gate voltage, drain voltage and switch current of Q4 at nominal input voltage and a 50% load b 100% load IET Power Electron., 2013, Vol. 6, Iss. 3, pp. 505–515 doi: 10.1049/iet-pel.2012.0426

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Fig. 13 Measured waveforms of gate voltages vQ1, gs and vQ4, gs, diode currents iD1–iD4 and the resultant output current iD at nominal input voltage and a 50% load b Full load

stress of each MOSFET is clamped at input voltage. The energy stored in the resonant inductance and magnetising inductance is used to achieve ZVS turn-on of MOSFETs at the leading leg. However, only resonant inductance is used to achieve ZVS turn-on of MOSFETs at the lagging leg. The drawback of the proposed converter is that the size of the proposed circuit with four ferrite cores is larger than the interleaved phase-shift full bridge converter with two ferrite cores and two power iron cores. A design example of a 960 W prototype circuit is presented and the system performance is veriﬁed by the experiments. Fig. 14 Measured circuit efﬁciencies of the proposed converter at different load conditions and nominal input voltage case

voltage can be decreased to zero voltage and Q1 is turned on at ZVS for both 50 and 100% loads. In the same manner, Figs. 10–12 show the measured gate voltage, drain voltage and switch current of Q2–Q4 at nominal input voltage with 50 and 100% load conditions. Active switches Q2–Q4 are also turned on at ZVS for both 50 and 100% loads. Fig. 13 gives the measured waveforms of gate voltages vQ1,gs and vQ4,gs, diode currents iD1–iD4 and the resultant output current iD at nominal input voltage with 50 and 100% loads. It is clear that the output diode currents iD1–iD4 are balanced. The measured circuit efﬁciencies at different load conditions are shown in Fig. 14. The measured circuit efﬁciency is 87.1, 91.5 and 90.2% at 20, 50 and 100% load with nominal input voltage.

6

Conclusion

A full-bridge converter without output inductor is presented to achieve ZVS turn-on for all power switches from 50 to 100% load. Four transformers are connected in series at the primary side and connected in parallel at the secondary side to share the load current. Each transformer can be operated as either an isolated transformer or an inductor such that no output inductor is needed at the output side. The voltage 514 & The Institution of Engineering and Technology 2013

7

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