DC converter with parallel input and parallel output ... - IEEE Xplore

IET Power Electronics Research Article

DC/DC converter with parallel input and parallel output with shared power switches and rectifier diodes

ISSN 1755-4535 Received on 19th June 2014 Accepted on 23rd November 2014 doi: 10.1049/iet-pel.2014.0489 www.ietdl.org

Bor-Ren Lin ✉, Chung-Wei Chu Department of Electrical Engineering, National Yunlin University of Science and Technology, Touliu, Yunlin 640, Taiwan ✉ E-mail: [email protected]

Abstract: A DC/DC converter with parallel input and parallel output circuit topology is presented to achieve the main features of reduced switch count and medium power level compared with conventional parallel half-bridge resonant converter. The proposed converter has three resonant circuits to share load currents and reduce the current stress of circuit components. These three resonant circuits use the same power switches to deliver power from input side to output load so that the switch counts are reduced compared with the conventional parallel resonant converter. The rectifier diodes at the secondary side of three resonant circuits are partially used in common so that the diode counts are also reduced. Since three resonant circuits are connected in parallel, the sizes of the transformers and active and passive components are reduced. The switching frequency of the proposed converter is operated to be less than the series resonant frequency. Thus, active switches are turned on under zero voltage switching and rectifier diodes are turned off under zero current switching. A 1.6 kW laboratory prototype is designed and constructed to demonstrate the feasibility and performance of the proposed circuit.

1

Introduction

Owing to the serious greenhouse effect and environmental pollution by using fossil fuels, renewable energy conversion systems such as photovoltaic (PV) inverter systems, wind power generation system and fuel cell conversion systems are the attractive power supply sources for distributed generation power systems [1–3]. Combining multiple renewable sources with a common DC bus of the power converter has been widespread for past 10 years. Solar power based on PV cells is a quiet and clean way to convert the sunlight into electrical energy. The output voltage of single PV cells is relatively low. Thus, the series connection of PV arrays is the conventional solution to provide medium power and output voltage. It is also an important issue to save the energy demand and increase energy conversion efficiency. High-efficiency converters with soft switching techniques have been studied for the past 20 years to meet the circuit efficiency demand of modern power converters. Active clamp converters [4–7] can achieve zero voltage switching (ZVS) turn-on to reduce the switching losses on power switches. However, the unbalanced voltage stress on rectifier diodes and DC magnetising current is the main drawback of active clamp techniques. Phase-shift pulse-width modulation (PWM) converters [8–10] can accomplish ZVS turn-on in limited input voltage ranges or load conditions. However, the large circulating current in the primary side will reduce the circuit efficiency, especially at light load condition or the low duty cycle case. In order to overcome this problem, the active or passive components [11, 12] can be used in the primary side or secondary side of conventional full-bridge converter to increase the circuit efficiency. However, many components added in full-bridge converter will reduce the circuit reliability and also increase the circuit cost. Resonant converters [13–18] have been presented to achieve the features of high circuit efficiency and high power density. All power switches can be turned on under ZVS. The rectifier diodes can be turned off under zero current switching (ZCS). Thus, the converter efficiency in the series resonant converters can be higher than that in the active clamp converters and phase-shift full-bridge converters.

A new resonant converter based on a half-bridge topology with three series resonant circuits is presented to achieve soft switching for all power devices and to decrease the current rating on power components. These three resonant circuits use the same active switches to reduce the switch counts compared with the switch counts in conventional parallel resonant converters. The rectifier diodes at secondary side are partially used in common so that the diode counts are also reduced. Since three resonant circuits are used in the half-bridge converter, the proposed converter can provide more power to output load compared with the conventional half-bridge resonant converter. The input impedance of the resonant circuit is controlled as inductive impedance. Thus, active switches are turned on under ZVS from no load to full load. Although resonant converter has high root mean square current (rms) compared with the rms current in the full-bridge converter, the total circuit efficiency of resonant converter is still higher than the other topologies owing to the low switching losses. Circuit analysis, circuit characteristics, design procedure and experimental results are provided in detail to demonstrate the feasibility and performance of the proposed circuit.

2

Circuit configuration

Fig. 1a shows a conventional half-bridge resonant converter for renewable energy DC/DC converter. For medium power rating, the outputs of several renewable energy sources are connected in series. Thus, the input voltage of resonant converter is in the range of 250 –300 V and the output voltage of DC/DC converter is about 400 V. A full-bridge resonant converter shown in Fig. 1b can supply double power rating in the half-bridge resonant converter. In order to deliver more power to output load and also to reduce current rating of power devices and passive components, the parallel connection of several resonant converters with the common active switches is adopted in the proposed converter for medium power applications. The circuit configuration of the proposed converter is given in Fig. 2. The proposed converter is controlled by using the variable switching frequency to regulate output voltage. The proposed converter has three resonant circuits with the same active switches S1 and S2. The components (Cr1, Lr1 IET Power Electron., 2015, Vol. 8, Iss. 5, pp. 814–821

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Fig. 1 Circuit configuration a Half-bridge resonant converter for high output voltage b Full-bridge resonant converter for high output voltage

Fig. 3 Key waveforms of the proposed converter

Fig. 2 Circuit configuration of proposed resonant converter

and Lm1), (Cr2, Lr2 and Lm2) and (Cr3, Cr4, Lr3 and Lm3) are the resonant tanks for circuits 1–3, respectively. Each resonant circuit supplies one-third of rated power to load side so that the current stresses of circuit components are reduced. T1–T3 are the isolation transformers. D1–D8 are the rectifier diodes. Coss1 and Coss2 are output capacitances of S1 and S2, respectively. Co and Ro are output capacitance and load resistance. Active switches S1 and S2 can be turned on under ZVS owing to the resonant behaviour at the transition interval. If the operating switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under ZCS. Full-bridge diode rectifiers instead of centre-tapped rectifiers are adopted at the secondary side to reduce voltage stress of rectifier diodes for high output voltage applications.

3

Operation principle

In this section, several assumptions made to the analysis of the proposed converter are as follows: (1) T1–T3 are identical with the same magnetising inductances Lm1 = Lm2 = Lm3 = Lm and turns ratio n = np/ns. (2) S1 and S2 have the same output capacitances Coss1 = Coss2 = Coss. (3) Resonant capacitances Cr1 = Cr2 = 2Cr3 = 2Cr4 = Cr. (4) Resonant inductances Lr1 = Lr2 = Lr3 = Lr. The proposed converter has four operation modes in a switching cycle when the switching frequency is greater than series resonant

frequency. However, six operation modes can be found in the proposed converter when the switching frequency is less than the series resonant frequency. The proposed converter at full load is designed to have the switching frequency less than the series resonant frequency. Fig. 3 shows the key PWM waveforms of the proposed converter in a switching cycle. Figs. 4 and 5 show the topological states in different operation modes. Before t0, both S1 and S2 are in the off-state, and D2, D3, D6 and D7 are conducting. Mode 1 [t0–t1]: This mode stars at t0 when the drain voltage of S1 reaches zero voltage and the drain voltage of S2 equals input voltage Vin. Since switch current iS1 < 0, the internal anti-parallel diode of S1 conducts. Thus, S1 can be turned on at this moment under ZVS. Diodes D2, D3, D6 and D7 are conducting. The secondary winding voltages are vT1,s = − Vo and vT2,s = vT3,s = Vo. The magnetising voltages are vLm1 = − nVo and vLm2 = vLm3 = nVo. Thus, the magnetising current iLm1 decreases linearly, and iLm2 and iLm3 increase linearly in this mode. Lr1 and Cr1 in circuit 1 are resonant. In the same manner, Lr2 and Cr2 in circuit 2 are resonant and Cr3, Cr4 and Lr3 are resonant in circuit 3. The resonant frequency in each resonant circuit is equal to fr = 1/2p Lr Cr . Power is transferred from input voltage source Vin to output load Ro. Since the switching frequency fsw < fr, the secondary winding currents iT1,s, iT2,s and iT3,s can be decreased to zero before S1 is turned off. Mode 2 [t1–t2]: This mode starts at t1 when the transformer secondary winding currents are all decreased to zero. Thus, the primary side currents iLr1 = iLm1, iLr2 = iLm2 and iLr3 = iLm3 and the secondary side diode currents iD1–iD8 are all equal to zero. (Cr1, Lr1 and Lm1), (Cr2, Lr2 and Lm2) and (Cr3, Cr4, Lr3 and Lm3) are resonant in circuits 1–3, respectively. The resonant frequency in this mode is equal to fp = 1/2p (Lr + Lm )Cr . Mode 3 [t2–t3]: This mode starts at time t2 when active switch S1 is turned off and D1, D4, D5 and D8 start conducting. The primary winding voltages are vLm1 = nVo and vLm2 = vLm3 = − nVo. The

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Fig. 5 Equivalent circuits of the proposed converter in modes 5 and 6 a Mode 5 b Mode 6

Mode 4 [t3–t4]: Mode 4 starts at time t3 when drain voltage vS2,ds reaches zero voltage. Since switch current iS2 < 0, the internal anti-parallel diode of S2 conducts. S2 can be turned on at this moment to perform ZVS. In this mode, D1, D4, D5 and D8 are conducting so that the secondary winding voltages vT1,s = Vo and vT2,s = vT3,s = − Vo. The magnetising voltages vLm1 = nVo and vLm2 = vLm3 = − nVo so that the magnetising current iLm1 increases and iLm2 and iLm3 both decrease. (Lr1 and Cr1), (Lr2 and Cr2) and (Cr3, Cr4 and Lr3) are resonant in circuits 1–3, respectively. Power is transferred from input voltage Vin to output load Ro. Since the operating switching frequency fsw < fr, the secondary winding currents iT1,s, iT2,s and iT3,s will be decreased to zero before S2 is turned off. Mode 5 [t4–t5]: Mode 5 starts at time t4 when iLm1 = iLr1, iLm2 = iLr2 and iLm3 = iLr3. At this moment, the transformer secondary winding currents are all equal to zero. Diodes D1–D8 are all in the off-state. Since Q2 is still conducting, (Cr1, Lr1 and Lm1), (Cr2, Lr2 and Lm2) and (Cr3, Cr4, Lr3 and Lm3) are resonant in circuits 1–3, respectively. Mode 6 [t5–T + t0]: Mode 6 starts at time t5 when S2 is turned off. In this mode, diodes D2, D3, D6 and D7 are conducting so that the magnetising voltages vLm1 = − nVo and vLm2 = vLm3 = nVo. The inductor current iLm1 decreases. In the same manner, iLm2 and iLm3 increase in this mode. Since iLr1(t5) > 0, iLr2(t5) < 0 and iLr3(t5) < 0, Coss2 is discharged and Coss2 is charged. If the energy stored in Lr1, Lr2 and Lr3 is greater than the energy stored in Coss1 and Coss2, then Coss1 can be discharged to zero voltage. The drain voltages of S1 and S2 can be obtained in (3) and (4)

Fig. 4 Equivalent circuits of the proposed converter in modes 1–4 a Mode 1 b Mode 2 c Mode 3 d Mode 4

magnetising current iLm1 increases and iLm2 and iLm3 both decrease. Since the inductor current iLr1(t2) < 0 and iLr2(t2) > 0 and iLr3(t2) > 0, Coss1 is charged and Coss2 is discharged. Coss2 can be discharged to zero voltage if the energy stored in Lr1, Lr2 and Lr3 is greater than the energy stored in Coss1 and Coss2. The drain voltages of S1 and S2 can be obtained in (1) and (2) vS1,ds (t) ≃

iLr2 (t2 ) + iLr3 (t2 ) − iLr1 (t2 ) (t − t2 ) 2Coss

vS2,ds (t) ≃ Vin −


(1)

(2)

vS1,ds (t) ≃ Vin +

vS2,ds (t) ≃


iLr1 (t5 ) − iLr2 (t5 ) − iLr3 (t5 ) (t − t5 ) 2Coss

(3)

(4)

At time T + t0, Coss1 is discharged to zero voltage. The internal anti-parallel diode of S1 is forward biased. IET Power Electron., 2015, Vol. 8, Iss. 5, pp. 814–821

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4 Analysis of the proposed converter and design example There are three resonant tanks in the proposed converter. The input voltage of the resonant tank is a square wave voltage. The resonant tank is a band-pass filter with the narrow bandwidth which is much less than the switching frequency. Thus, the harmonics of the input square wave voltage can be neglected at the output of each resonant tank. Variable frequency modulation is adopted to maintain output voltage at the desired voltage level. Each resonant tank provides one-third of rated power to output load. The duty ratio of S1 and S2 is equal to 0.5. Thus, the input voltage to each resonant tank is a square waveform. Based on the Fourier series analysis, the input voltages of resonant tanks are expressed as vin,1 = vin,2 = vin,3 =

2V Vin in sin (2pmfs t) + 2 mp m=1,3,5,...

m=1,3,5,...

m

2Vin sin (2pmfs t) np

24n2 R p2 o

2n(Vo + 2Vf ) 1 . (1 + k) Vin, max

Vin, max 2(1 + k)(Vo + 2Vf )

(12) Gdc, max =

2(Vo + 2Vf )n 2 × (400 + 2 × 1.7) × 0.4 = 1.29 = 250 Vin, min

Step 3: Q value at full load. The AC voltage gain curves against frequency ratio fs/fr with k = 1/6 are given in Fig. 6. Since the obtained maximum DC gain is 1.29 in (13), the maximum Q at full load in Fig. 5 should be less than 0.4 in order to obtain a switching frequency to regulate output voltage. Thus, the selected Q value at full load is 0.4 in this prototype circuit. Step 4: AC equivalent resistance. The AC equivalent resistance Rac at full load can be obtained from (7):

(7)

(8)

(9)

where Vf is voltage drop on D1–D8. Thus, the turns ratio of transformers T1–T3 is obtained as nmin =

2(Vo + 2Vf )n 2 × (400 + 2 × 1.7) × 0.4 = 1.076 = 300 Vin, max

(6)

where k = Lr1/Lm1, Q = Lr1 /Cr1 /Rac,1 , fr = 1/(2p Lr1 Cr1 ) and fs is the switching frequency. If the minimum DC voltage gain at maximum input voltage is greater than the AC voltage gain at no-load condition, then the output voltage of the proposed converter can be regulated Gdc, min =

Gdc, min =

(13)

The AC voltage gain of the resonant tank 1 is derived as 1 |Gac (f )| = 2 2 1 + k(1 − (fr2 /fs2 )) +Q2 (fs /fr ) − (fr /fs )

Step 2: DC voltage gain. The actual minimum and maximum DC gains of the proposed converter are shown in (12) and (13)

(5)

It is clear to find that there is a DC voltage level Vin/2 on input voltages vin,1 and vin,2. The DC voltage levels are blocked by resonant capacitors Cr1 and Cr2. However, the input AC voltage components of the three resonant tanks are identical. Three resonant tanks have the matching circuit components and parameters. Thus, only resonant tank 1 is discussed in the following to derive the system AC voltage gain. Based on the fundamental frequency analysis, the load resistance Ro reflected to the transformer primary side can be given as Rac,1 = Rac,2 = Rac,3 = Rac =

The actual primary and secondary turns in the prototype circuit are np = 16 T and ns = 40 T and the actual turns ratio n is equal to 0.4. Transformers T1–T3 were implemented using TDK EER-42 magnetic core with Ae = 194 mm2.

Rac =

24n2 24 × 0.42 400 = 38.9 V Ro = × 2 4 p 3.141592

(14)

Step 5: Resonant capacitances and inductances. The series resonant frequency is 120 kHz and the selected Q = 0.4. Thus, the resonant capacitances and inductances can be obtained in (15)–(17) Lr1 = Lr2 = Lr3 = Lr =

QRac 0.4 × 38.9 = ≃ 20.6 mH 2p × 120000 2pfr

(15)

1 ≃ 86 nF 4p2 Lr fr2

(16)

Cr1 = Cr2 = Cr =

Cr3 = Cr4 = 0.5Cr = 43 nF

(17)

Based on the selected inductance ratio k = Lr/Lm = 1/6, the magnetising inductances of T1–T3 are obtained in (18) Lm1 = Lm2 = Lm3 = Lr /k =

20.6 mH ≃ 124 mH 1/6

(18)

(10)

A design example of the proposed converter is provided in the following. A laboratory prototype with 1.6 kW rated power was made to verify the performance of the proposed converter. The input voltage range is 250–300 V and output voltage is 400 V with 4 A load current. The series resonant frequency fr = 120 kHz. The selected inductance ratio k = Lr/Lm = 1/6. Step 1: Turns ratio of T1–T3. The minimum DC gain Gdc,min at Vin = 300 V is proposed to be unity (at series resonant frequency). Based on (9), the theoretical turns ratio of T1–T3 is given as n=

np Vin, max 300 ≃ 0.37 = = ns 2(Vo + 2Vf ) 2(400 + 2 × 1.7)

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(11) Fig. 6 AC voltage gain and DC voltage gain at different frequency ratio fs/fr

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Step 6: No load condition. Based on (10), the minimum turns ratio of T1–T3 at no-load condition is obtained in (19) Vin, max 2(1 + k)(Vo + 2Vf ) 300 = ≃ 0.319 2 × (1 + 1/6) × (400 + 2 × 1.7)

controller (TL431), an optocoupler (PC817) and a variable frequency control IC are used to control the output voltage.

5

nmin =

(19)

The selected turns ratio of T1–T3 is n = 0.4 > nmin. Therefore the output voltage can be regulated at no-load case. Step 7: Power semiconductors. The input maximum voltage is 300 V and the input DC current is 1600 W/300 V = 5.3 A. MOSFETs IRFP460 with Coss = 480 pF at 25 V, 500 V voltage rating and 20 A current rating are adopted for S1 and S2. The output voltage is 400 V and load current 4 A. FSF10A60 with 600 V voltage rating and 10 A current rating are adopted for D1–D8 in the prototype circuit. The constant output voltage is demanded in the DC/DC converter. Thus, a resistor-based voltage divider, a voltage

Experimental results

Based on the circuit parameters derived in the previous section, the prototype circuit was tested and results are provided in this section to verify the performance and effectiveness of the proposed converter. The test results of gate voltage, drain voltage and drain current of S1 at different input voltage and load current are shown in Fig. 7. Similarly, Fig. 8 illustrates the test results of gate voltage, drain voltage and drain current of S2 at different input voltage and load current. From the test results in Figs. 7 and 8, both switches S1 and S2 are turned on under ZVS. Fig. 9 gives the test results of three resonant inductor currents and four resonant capacitor voltages at minimum input voltage and different load current conditions. In the same manner, the measured resonant inductor currents and resonant capacitor voltages at maximum input voltage and different load current conditions are illustrated in Fig. 10. From the test results in Figs. 9 and 10, three resonant inductor currents are balanced under

Fig. 7 Measured gate voltage, drain voltage and switch current of S1

Fig. 8 Measured gate voltage, drain voltage and switch current of S2

a At 25% load Vin = 250 V b At 100% load Vin = 250 V c At 25% load Vin = 300 V d At 100% load Vin = 300 V

a At 25% load Vin = 250 V b At 100% load Vin = 250 V c At 25% load Vin = 300 V d At 100% load Vin = 300 V


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Fig. 9 Measured inductor currents and capacitor voltages at primary side under Vin = 250 V a iLr1–iLr3 at 25% load b vCr1–vCr4 at 25% load c iLr1–iLr3 at 100% load d vCr1–vCr4 at 100% load

Fig. 10 Measured inductor currents and capacitor voltages at primary side under Vin = 300 V a iLr1–iLr3 at 25% load b vCr1–vCr4 at 25% load c iLr1–iLr3 at 100% load d vCr1–vCr4 at 100% load


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Fig. 12 Measured switching frequency and efficiency of the proposed converter a Switching frequency against load b Efficiency against load

Fig. 11 Measured diode currents at secondary side at full load a Vin = 250 V b Vin = 300 V

different load currents and input voltages. The test results of gate voltage vS1,gs and rectifier diode currents iD1–iD8 at different input voltage and full-load conditions are shown in Fig. 11. It is clear that the measured diode currents iD3–iD6 are larger than the diode currents iD1, iD2, iD7 and iD8 and D1–D8 are all turned off under ZCS. When S1 is in the on-state, the transformer secondary current iT1,s will flow through diodes D2 and D3. Similarly, the transformer secondary currents iT2,s and iT3,s will flow through (D3 and D6) and (D6 and D7). Therefore iT1,s and iT2,s flow through D3 at the same time. In the same manner, iT2,s and iT3,s flow through D6 at the same time. The measured switching frequencies and circuit efficiencies at different loads are shown in Fig. 12.

6

Conclusions

The main contribution of this paper is to present a half-bridge converter with three resonant circuits to provide more output

power and reduced current stress of passive components compared with the conventional half-bridge resonant converter. For a 1.6 kW resonant converter, parallel half-bridge resonant converters with more active switches are needed because one LLC resonant converter can approximately provide 0.5 kW to output load. Thus, more components are needed in parallel resonant converters. In the proposed converter, three resonant circuits share only one half-bridge leg so that the switch counts are reduced compared with the conventional parallel resonant converters. Each resonant circuit delivers one-third of load power to output side. Since the output side is high-voltage applications, some rectifier diodes are shared by two resonant converters. Thus, the rectifier diodes are also reduced in the proposed converter. Full-wave diode rectifier is adopted at high-voltage side to limit the voltage stress of rectifier diode at output voltage. Based on the frequency modulation scheme, the input impedance of each resonant circuit is an inductive load. Thus, power metal–oxide–semiconductor fieldeffect transistors (MOSFETs) can be turned on under ZVS and rectifier diodes can be turned off under ZCS. The switching losses in power switches and reverse recovery losses in rectifier diodes can be improved. The system analysis, characteristics analysis and design example of the proposed converter are discussed in detail. Finally, experiments are provided to verify the performance and effectiveness of the converter.

7

Acknowledgment

This project is supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224-022-MY3.

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