DC converter with two half

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Aug 9, 2011 - of the proposed converter are provided and discussed. Experiments ... have been proposed to reduce total current harmonics and increase ... First, three-phase utility voltage (vLL ¼ 380 V) is rectified .... Based on the Fourier series analysis, the input ... tank is excited by an effectively sinusoidal input voltage.

www.ietdl.org Published in IET Power Electronics Received on 7th April 2011 Revised on 9th August 2011 doi: 10.1049/iet-pel.2011.0130

ISSN 1755-4535

Zero-voltage switching DC/DC converter with two half-bridge legs and series-parallel transformers C.-H. Chien1 Y.-H. Wang1 B.-R. Lin2 1

Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: [email protected]

2

Abstract: A new zero-voltage switching (ZVS) converter with the series half-bridge legs for high DC bus application is presented. Two circuit modules with the interleaved pulse-width modulation are adopted to share the load current. In each circuit module, a series resonant converter with two transformers that are series-connected in primary side and parallelconnected in secondary side is used to achieve load current sharing and reduce the current stresses of rectified diodes and transformer secondary windings. Based on the series resonant behaviour, power metal-oxide semiconductor field-effect transistors (MOSFETs) are turned on at ZVS and rectifier diodes can be turned off at zero current switching. Therefore the switching losses of power semiconductors are reduced. Two half-bridge legs and two split capacitors are connected in series such that the voltage stress of each active switch is clamped to one-half of DC bus voltage. Thus, the low voltage stress of MOSFETs can be used in high DC bus application. The principle of operation, steady-state analysis and design consideration of the proposed converter are provided and discussed. Experiments with a laboratory prototype with 24 V/40 A output are provided to verify the effectiveness of the proposed converter.

1

Introduction

Power converters with high power density, high power factor and high efficiency are demanded to meet the energy-saving requirements and harmonic limits. IEC61000-3-2 Class A standard limits the current harmonics and input power factor of AC/DC converters if the power level is greater than 75 W. Power factor correction (PFC) techniques [1 – 6] have been proposed to reduce total current harmonics and increase input power factor for single-phase or three-phase AC/DC converters. For three-phase 380 V (or 480 V) AC/ DC converters, the DC bus voltage may be higher than 500 V (or 650 V). Therefore it is difficult to select suitable metal-oxide semiconductor field effect transistors (MOSFETs) for the second-stage DC/DC converter. Threelevel neutral-point clamp converters [7 – 10] can overcome these drawbacks with more power switches, split capacitors and clamp diodes such that the voltage stress of MOSFETs is clamped to one-half of DC bus voltage. The main disadvantages of three-level DC –DC converters are more circuit components, high cost and the complicated control schemes. Series resonant converters [11 – 15] have been proposed with the advantages of high conversion efficiency and high power density. Owing to the resonant behaviour, power MOSFETs can be turned on at zero-voltage switching (ZVS). If the operating switching frequency is lower than the series resonant frequency, the rectifier diodes can be turned off at zero-current switching (ZCS). Thus, the reverse recovery losses of diode rectifier and switching losses of active switches are reduced. IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419–427 doi: 10.1049/iet-pel.2011.0130

A novel DC/DC converter with two circuit modules for high voltage application is presented. Two capacitors and two half-bridge legs are connected in series in high voltage side to clamp the voltage stress of MOSFETs at one-half of DC bus voltage. Two circuit modules are operated with the phase-shift of one-fourth of switching period to reduce the input and output ripple currents, share the load current, reduce the size of the magnetic core and lessen the current stress on the primary windings. In each circuit module, a series resonant tank with two series transformers and two centre-tapped rectifiers is used to achieve soft switching for all semiconductors with wide input voltage ranges and load conditions. Thus switching losses of power switches and reverse recovery problem of the rectifier diodes are reduced. The primary windings of two transformers are connected in series to balance the secondary winding currents, and the secondary windings of two transformers are connected in parallel to reduce the current stresses on the secondary windings. Thus the load current is equally distributed into each isolated transformers. The centre-tapped rectifiers are used at the secondary side to reduce the conduction losses on rectifier diodes compared to the conduction losses on full-bridge diode rectifiers. Finally, experiments based on a 960 W prototype were provided to verify the performance of the proposed converter.

2

Circuit configuration

Fig. 1a gives the circuit configuration of the proposed AC/DC converter based on two interleaved series resonant converters. 419

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Fig. 1 Circuit configuration a Proposed interleaved series resonant converter with two circuit modules b Converter 1

First, three-phase utility voltage (vLL ¼ 380 V) is rectified into an uncontrolled DC voltage through a three-phase diode rectifier. The nominal DC bus voltage (Vin) is about 530 V. Two series resonant converters operated with an interleaved pulse-width modulation (PWM) scheme is operated to regulate output voltage at the desired voltage level and to reduce the ripple currents at the input and output sides. If the switching frequency is less than the series resonant frequency in each converter, all active switches can be turned on at ZVS and the rectifier diodes can be operated turned off at ZCS. Therefore the switching losses of active switches are reduced and the reverse recovery losses of the fast recovery diodes are also lessened. For the converter 1 (Fig. 1b), Vin/2 is input DC bus voltage, switches S1 and S2 are the half-bridge network, Cr1 , Lr1 , Lm1 and Lm2 are the resonant tank, T1 and T2 are two isolated transformers, D1 – D4 are rectifier diodes and Co is the output capacitance. Therefore the voltage stress of each active switch is clamped at Vin/2 and the low-voltage stress MOSFETs can be used in the adopted circuit for high DC bus applications. For high load current applications, the current stress of the transformer secondary winding is increased. To overcome these problems, two small size transformers with lower winding current stress are connected in series at the primary side and connected in parallel at load side. Thus the current stresses of the secondary windings of two transformers are theoretically equal to one-half of the current stress of the secondary windings with only one transformer circuit. Two circuit modules are operated with interleaved PWM scheme in order to share load current and reduce output ripple current.

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circuit operation and the behaviours of converter 1 during one switching period. Based on the on/off states of active switches S1 and S2 and rectifier diodes D1 – D4 , there are six operation modes in converter 1. Fig. 2 shows the key PWM waveforms of converter 1 in a switching cycle. The topological equivalent circuits of converter 1 for each operating mode are given in Fig. 3. Before time t0 , S2 is in the on state and all the rectifier diodes are in the off state. Thus, the resonant current iLr1 equals the magnetising currents iLm1 and iLm2 . Mode 1 [t0 ≤ t , t1]: At time t0 , S2 is turned off. Diodes D1 and D3 are conducting in this mode such that the magnetising voltages vLm1 and vLm2 are clamped to nVo . The components of CS1 , CS2 and Lr1 are resonant in this mode. The resonant current iLr1 charges capacitor CS2 from zero voltage and discharges capacitor CS1 from Vin/2. If the energy stored in Lr1 is greater than the energy stored in CS1

Operation principle

In the proposed circuit, two converters are operated with interleaved PWM scheme to share load current and reduce the ripple current at output capacitor. To simplify the circuit analysis, the following statements are only discussed: the 420 & The Institution of Engineering and Technology 2012

Fig. 2 Key PWM waveforms of the converter 1 in a switching cycle IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419 –427 doi: 10.1049/iet-pel.2011.0130

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Fig. 3 Operation modes of the converter 1 a b c d e f

Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6

and CS2 , then capacitor CS1 can be discharged from Vin/2 to zero voltage and capacitor CS2 can be charged from zero voltage to Vin/2. The magnetising currents iLm1 and iLm2 increase in this mode. iLm1 (t) = iLm1 (t0 ) +

nVo (t − t0 ) Lm

nV (t − t0 ) iLm2 (t) = iLm2 (t0 ) + o Lm

(1)

where np/ns1 ¼ n and Lm1 ¼ Lm2 ¼ Lm . The diode currents iD1 and iD3 are given as iD1 (t) = n(iLr1 (t) − iLm1 (t)), iD3 (t) = n(iLr1 (t) − iLm2 (t)) (2) Since CS1 and CS2 are much less than Cr1 , capacitor CS1 is discharged very quickly and inductor current iLr1 is almost constant in this time interval. At time t1 , the capacitor IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419–427 doi: 10.1049/iet-pel.2011.0130

voltages vCS2 ¼ Vin/2 and vCS1 ¼ 0. Then the anti-parallel diode of S1 is conducting. Mode 2 [t1 ≤ t , t2]: At time t1 , the anti-parallel diode of S1 is conducting such that active switch S1 can be turned on at this moment to achieve ZVS, since the diodes D1 and D3 are conducting in this mode. Thus the magnetising voltages vLm1 ¼ vLm2 ¼ nVo and the magnetising currents iLm1 and iLm2 increase linearly with the slope of nVo/Lm . Lr1 and Cr1 are resonant with the applied voltage Vin/2 2 2nVo . The inductor current iLr1 and capacitor voltage vCr1 in this mode are expressed as

iLr1 (t) =

Vin /2 − 2nVo − vCr1 (t1 ) sin vr (t − t1 ) Zr + iLr1 (t1 ) cos vr (t − t1 )

(3)

vCr1 (t) = Vin /2 − 2nVo − [Vin /2 − nVo − vCr1 (t1 )] × cos vr (t − t1 ) + iLr1 (t1 )Zr sin vr (t − t1 ) 421

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www.ietdl.org   where vr = 1/ Lr1 Cr1 and Zr = Lr1 /Cr1 . From (3), the inductor current iLr1 increases in this mode. This mode ends at time t2 when iLm1 ¼ iLm2 ¼ iLr1 . Then iD1 ¼ iD3 ¼ 0 and diodes D1 and D3 are off. Mode 3 [t2 ≤ t , t3]: This mode starts at t2 when iLm1 ¼ iLm2 ¼ iLr1 . All rectifier diodes D1 – D4 are in the off state. Active switch S1 is still in the on state. Cr1 , Lr1, Lm1 and Lm2 are resonant in this mode. The inductor current iLr1 and capacitor voltage vCr1 are expressed as Vin /2 − vCr1 (t2 ) sin vp (t − t2 ) + iLr1 (t2 ) cos vp (t − t2 ) Zp

iLr1 (t) =

vCr1 (t) = Vin /2 − [Vin /2 − vCr1 (t2 )] cos vp (t − t2 ) + iLr1 (t2 )Zp sin vp (t − t2 ) (4)  where vp = 1/ (Lr1 + Lm1 + Lm2 )Cr1 and   Zp = (Lr1 + Lm1 + Lm2 )/Cr1 . This mode ends at time t3 when S1 is turned off. Mode 4 [t3 ≤ t , t4]: At time t3 , S1 is turned off and diodes D2 and D4 are conducting. Thus the magnetising voltages vLm1 ¼ vLm2 ¼ 2nVo and the magnetising currents iLm1 and iLm2 decrease with the slope of 2nVo/Lm in this mode. Since the inductor current iLr1(t3) is positive, CS1 is charged and CS2 is discharged in this mode. If the energy stored in Lr1 is greater than the energy stored in CS1 and CS2 , then capacitor CS1 can be charged to Vin/2 and CS2 can be discharged to zero voltage. These two capacitor voltages are expressed as vCS1 (t) ≃

Fig. 4 Key waveforms of the proposed interleaved series resonant converter

this mode. The inductor current iLr1 and capacitor voltage vCr1 are expressed as

iLr1 (t3 ) i (t ) (t − t3 ), vCS2 (t) ≃ Vin /2 − Lr1 3 (t − t3 ) 2CS 2CS (5)

iLr1 (t) = −

vCr1 (t) = vCr1 (t5 ) cos vp (t − t5 ) + iLr1 (t5 )Zp sin vp (t − t5 )

where CS ¼ CS1 ¼ CS2 . The diode currents iD2 and iD4 are given as iD2 (t) = n(iLm1 (t) − iLr1 (t)), iD4 (t) = n(iLm2 (t) − iLr1 (t)) (6) At time t4 , the capacitor voltage vCS2 equals zero voltage. Then the anti-parallel diode of S2 is conducting. Mode 5 [t4 ≤ t , t5]: At time t4 , the anti-parallel diode of S2 is conducting (since iLr1(t4) . 0). Thus active switch S2 can be turned on at this moment to achieve ZVS. Since diodes D2 and D4 are conducting in this mode such that the magnetising voltages vLm1 ¼ vLm2 ¼ 2nVo . Lr1 and Cr1 are resonant with the applied voltage 2nVo and the inductor current iLr1 and capacitor voltage vCr1 are expressed as iLr1 (t) =

2nVo − vCr1 (t4 ) sin vr (t − t4 ) + iLr1 (t4 ) cos vr (t − t4 ) Zr

vCr1 (t) = 2nVo − [2nVo − vCr1 (t4 )] cos vr (t − t4 ) + iLr1 (t4 )Zr sin vr (t − t4 )

vCr1 (t5 ) sin vp (t − t5 ) + iLr1 (t5 ) cos vp (t − t5 ) Zp

(8) This mode ends at time t0 when S2 is turned off. Then the operation of converter 1 for one switching cycle is completed. The next switching cycle begins and returns to mode 1. Fig. 4 shows the key current and voltage waveforms of the proposed converter with interleaved PWM operation. Active switches S1 and S2 in converter 1 and S3 and S4 in converter 2 are phase-shifted 908, respectively. Thus iLr1 , vCr1 , iD1 – iD4 in converter 1 and iLr2 , vCr2 , iD5 – iD8 in converter 2 are also phase-shifted 908 each other. Therefore the ripple current of output capacitor Co is reduced compared to the ripple current of a conventional series resonant converter. Also, the voltage stresses of all active switches are clamped to Vin/2 instead of Vin in a conventional half-bridge series resonant converter. Therefore the adopted converter is suitable for high DC bus voltage applications.

(7) From (7), the inductor current iLr1 decreases in this mode. This mode ends at time t5 when iLm1 ¼ iLm2 ¼ iLr1 . Then diode currents iD2 ¼ iD4 ¼ 0 and diodes D2 and D4 are off. Mode 6 [t5 ≤ t , t0]: This mode starts at t5 when iLm1 ¼ iLm2 ¼ iLr1 . All diodes D1 – D4 are in the off state. S2 is still in the on state. Cr1 , Lr1, Lm1 and Lm2 are resonant in 422 & The Institution of Engineering and Technology 2012

4

System analysis

Two converters are operated with interleaved PWM scheme and variable switching frequency with 50% duty cycle to regulate load voltage. Each converter supplies one-half of load power. The fundamental harmonic analysis is used to analyse the DC voltage conversion ratio. Basically the input IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419 –427 doi: 10.1049/iet-pel.2011.0130

www.ietdl.org no-load condition is expressed as |Gac (f )|NL =

1 [1 + k(1 − (fr2 /f 2 ))]

(15)

If the switching frequency is infinity, the minimum AC voltage gain at no-load condition is obtained as |Gac (1)|NL =

Fig. 5 AC equivalent circuit of the converter 1

power is transferred to output load through a resonant tank based on the switching frequency. The harmonics of the switching frequency can be neglected in the system analysis. Fig. 5 shows the AC equivalent circuit of the converter 1. Based on the Fourier series analysis, the input voltage of the resonant tank can be expressed as vCS2 =



Vin Vin + sin(2pmfs t) 4 m p m=1,3,5...

(9)

The root-mean-square√(rms) value of the fundamental input  voltage VCS2,f is Vin / 2p. With respect to the fundamental input voltage, the resonant tank current can be expressed as iLr1,f =

√ 2ILr1,f sin(2pfs t − w)

(10)

where ILr1,f and w are the rms current and phase shift of fundamental inductor current iLr1,f . Based on the fundamental frequency analysis, the load resistance reflected to primary side of transformer can be expressed as 32n2 Rac = 2 Ro p

VCS2,f (s) 1 sLm Rac = + sLr1 + 2 ILr1,f (s) sLm + Rac sCr1

(12)

where Lm ¼ Lm1 ¼ Lm2 . The equivalent AC voltage gain of converter 1 is expressed as  2VRac,f (s) 2sLm Rac = Gac (s) = VCS2,f (s) sLm + Rac   1 2sLm Rac 8nVo + sLr1 + = sLm + Rac Vin sCr1

Thus the output voltage of the proposed converter can be regulated at the no-load condition if the minimum DC voltage gain is greater than the minimum AC voltage gain in (16).

5

Design example

A laboratory prototype with 960 W rated power was presented to verify the effectiveness of the proposed converter. The output voltage and full load current are 24 V and 40 A. The input DC bus voltage is from 480 to 600 V and the nominal input voltage is 530 V. The selected series resonant frequency fr ¼ 100 kHz. The selected primary and secondary turns of transformers T1 –T4 are np ¼ 20 T and ns1 ¼ 6 T. Thus the minimum and maximum DC gains of the proposed converter are Gdc, min =

8(Vo + Vf )np 8 × (24 + 0.8) × 20 ≃ 1.1 = Vin, max ns1 600 × 6

(17)

Gdc, max =

8(Vo + Vf )np 8 × (24 + 0.8) × 20 ≃ 1.38 = Vin, min ns1 480 × 6

(18)

In the prototype circuit, the selected Q ¼ 0.3 and k ¼ 1/8. The ac equivalent resistance Rac is derived as Rac =

32n2 32(20/6)2 24 ≃ 21.6 V R = p2 o p2 40

(19)

The characteristic impedance Zo can be given as  Lr = Q × 2Rac = 0.3 × 2 × 21.6 ≃ 12.96 V (20) Zo = Cr Based on the derived characteristic impedance Zo , resonant frequency fr and inductance ratio k, the resonant inductance Lr1 , magnetic inductance Lm and resonant capacitance Cr1 can be obtained as

(13) Lr1 =

1 |Gac (f )| =  [1 + k(1 − (fr2 /f 2 ))]2 + Q2 ((f /fr ) − (fr /f ))2  Lr1 /Cr1 /2Rac and where k ¼ r1/(2Lm), Q = Zo /2Rac = L  fr = 1/2p Lr1 Cr1 . At the no-load condition, we can obtain that Rac ¼ 1 and Q ¼ 0. The AC voltage gain in (14) at the

Zo 12.96 ≃ 20.6 mH = 2pfr 2p × 100000

Lm = Lr1 /2k =

(14)

IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419–427 doi: 10.1049/iet-pel.2011.0130

(16)

(11)

where n ¼ np/ns and Ro ¼ Vo/Io . Therefore the AC resonant tank is excited by an effectively sinusoidal input voltage VCS2,f and drives an effective resistive road 2Rac . The input impedance of the resonant tank is given as Zin (s) =

1 (1 + k)

Cr1 =

20.6 mH ≃ 82.4 mH 2/8

(21)

(22)

1 1 = ≃ 123 nF 4p2 Lr1 fr2 4p2 × 20.6 × 10−6 × (100000)2 (23) 423

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www.ietdl.org From (16), the no-load gain of the adopted circuit is given as |Gac (1)|NL =

1 1 = ≃ 0.89 , Gdc, min = 1.1 (1 + k) 1 + 1/8 (24)

Therefore the output voltage of the proposed converter can be regulated at no-load condition. The rms current of capacitors Cr1 and Cr2 is obtained from the magnetising current iLm1 and the secondary winding current reflected to the primary side. Thus the rms currents of resonant capacitors Cr1 and Cr2 are derived as (see (25)) The voltage stress, rms current and average current of rectifier diodes D1 – D8 are given as vD1, max = 2Vo + Vf = 2 × 24 + 0.8 = 48.8 V

(26)

iD1,rms = pIo, max /16 = 3.14159 × 40/16 ≃ 7.85 A

(27)

iD1,av = Io /8 = 40/8 = 5 A

(28)

The Schottky diodes MBR3060PT with 60 V voltage stress, 30 A current stress and 0.8 V voltage drop are used for D1 – D8 in the proposed circuit. The voltage stress and rms current of power switches S1 – S4 are given as

iS1,rms

vS1, max = Vin, max /2 = 300 V √ √ = iCr1,rms / 2 ≃ 5.47/ 2 ≃ 3.87 A

(29) (30)

The MOSFETs IRFP460 with 500 V voltage stress and 20 A current stress are used for S1 – S4 in the proposed circuit. Table 1 shows the selected component parameters in the proposed circuit shown in Fig. 1a.

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Experimental results

Experiments based on a laboratory prototype with the rated 960 W were presented in this section to verify the effectiveness of the proposed converter. The main

Table 1

Key circuit parameters of the prototype circuit

input voltage Vin input nominal voltage Vin_nom output voltage Vo and output current Io series resonant frequency fr switches S1 –S4 diodes D1 –D8 turns ratio of T1 – T4 resonant inductances Lr1 –Lr2 magnetising inductances Lm1 –Lm4 resonant capacitances Cr1 – Cr2 input capacitances Cin1 , Cin2 output capacitance Co

iCr1,rms = iCr2,rms

480– 600 V 530 A 24 V/40 A 100 kHz IRFP460 MBR3060PT np:ns1:ns2 ¼ 20:6:6 21 mH 82 mH 114 nF 330 mF/400 V 2200 mF/50 V

specifications and circuit parameters of the prototype are given in Table 1. The front stage of the proposed converter is a three-phase diode rectifier and a bulk capacitor to convert a three-phase 380Vrms utility voltage into a DC bus voltage Vin ≃ 530 V. The type-2 voltage controller based on a TL431 and optocoupler PC817 is used to regulate the switching frequency. The pulse frequency modulation IC L6599, D-type flip-flop IC and isolated gate drivers are adopted to generate four gate signals for MOSFETs. Fig. 6 shows the measured waveforms of gate voltages of four active switches with different input voltages and full-load condition. From Fig. 6, we can observe that the phase shift between the gate voltages vS1,gs and vS3,gs is one-fourth of switching period. Fig. 7 shows the measured gate voltages, drain voltages and drain currents of active switch Q1 at 25 and 100% load conditions with input voltage Vin ¼ 480, 530 and 600 V cases. Before switch S1 is turned on, the drain current is negative to discharge capacitance CS1 . Thus drain voltage can be decreased to zero voltage, then switch S1 can be turned on at ZVS. Similarly, we can obtain that switches S2 – S4 are turned on at ZVS from wide input voltages and load conditions. Fig. 8 illustrates the measured waveforms of gate voltages vS1,gs and vS3,gs , inductor currents iLr1 and iLr2 and resonant capacitor voltages vCr1 and vCr2 at full load and input voltage Vin ¼ 480, 530 and 600 V cases. It is clear that the resonant inductor currents iLr1 and iLr2 are balanced with the different input voltages and full-load condition. Fig. 9 shows the measured waveforms of gate voltages vS1,gs and vS3,gs and output currents of each centre-tapped rectifier at full-load and nominal input voltage Vin ¼ 530 V. Fig. 10 shows the measured switching frequencies at different input voltages and different load conditions. Since the input current of each series resonant converter is a symmetrical waveform and the duty ratio of active switches in these two halfbridge converters is fixed to 0.5 with phase-shift one-fourth of switch period, two split capacitor voltages are naturally balanced to supply the balanced currents to output load. There are several ways to avoid two split capacitor voltage unbalance. First, the balance resistors can be connected in parallel with two spilt capacitors to avoid the unbalanced capacitor voltages. Second, two series resonant converters with the circuit parameters can also help to balance the output currents of two converters. Thus, two split capacitor voltages can be balanced. These two ways are adopted in the prototype circuit and worked well. At full-load condition, the voltage difference between two split capacitors is 6.5, 5.4 and 4.7 V with Vin ¼ 480, 530 and 600 V, respectively. Fig. 11 shows the measured efficiencies of the proposed converter at different load conditions. The circuit efficiency of the proposed converter is also compared with the two series asymmetrical PWM half-bridge converters with the same circuit specifications and shown in Fig. 12. Since the rectifier diodes of asymmetrical pulse-width modulated (APWM) half-bridge converter have reverse recovery losses, the proposed converter has better circuit efficiency compared to the APWM half-bridge converters.

 2 

 2  2  2

pI n(Vo + Vf ) p × 40 (20/6) × (24 + 0.8) o, max  √ + √ √ + √ = ≃ 5.47 A = 4 3 Lm fs, min 4 3 × 82.4 × 10−6 × 100000 8 × (20/6) × 2 8n 2 (25)

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IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419 –427 doi: 10.1049/iet-pel.2011.0130

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Fig. 6 Experimental waveforms of gate voltages of S1  D4 at full load a Vin ¼ 480 V b Vin ¼ 530 V c Vin ¼ 600 V

Fig. 7 Experimental gate voltage, drain voltage and drain current of switch S1 a b c d e f

Vin ¼ 480 V and 25% load Vin ¼ 480 V and 100% load Vin ¼ 530 V and 25% load Vin ¼ 530 V and 100% load Vin ¼ 600 V and 25% load Vin ¼ 600 V and 100% load

IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419–427 doi: 10.1049/iet-pel.2011.0130

425

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Fig. 8 Measured waveforms of gate voltages vS1,gs and vS3,gs , inductor currents iLr1 and iLr2 and resonant capacitor voltages vCr1 and vCr2 at full load a Vin ¼ 480 V b Vin ¼ 530 V c Vin ¼ 600 V

Fig. 9 Measured waveforms of gate voltages vS1,gs and vS3,gs and output currents of each centre-tapped rectifier at full load and nominal input voltage Vin ¼ 530 V 426 & The Institution of Engineering and Technology 2012

Fig. 10 Measured switching frequencies at different input voltages and different load conditions IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419 –427 doi: 10.1049/iet-pel.2011.0130

www.ietdl.org adopted converter are discussed in detail in this paper. Finally experiments based on a laboratory prototype are provided to verify the effectiveness of the converter.

8

Acknowledgment

The authors would like to acknowledge the financial support of the National Science Council in Taiwan, Republic of China, through its grant NSC101-2221-E-224-MY2.

9 Fig. 11 Measured efficiencies of the proposed converter at different load conditions

Fig. 12 Measured efficiencies of the proposed converter and the two APWM half-bridge converters at nominal input voltage and different load conditions

7

Conclusion

This paper presents a resonant converter with the series halfbridge legs for high DC bus voltage applications. There are two circuit modules to share the load power. In each circuit module, a series resonant converter with the seriesconnected in primary side and parallel-connected in secondary side to achieve the characteristics of ZVS turn-on for power switches, ZCS turn-off for rectifier diodes, balance secondary winding currents and low switching losses on power semiconductors. Since two half-bridge legs are connected in series in input terminal, the voltage stress of each active switch is clamped at half of input voltage. Thus, the active switches with low voltage stress can be used for high DC bus voltage applications. The system analysis, circuit characteristics and a design example of the

IET Power Electron., 2012, Vol. 5, Iss. 4, pp. 419–427 doi: 10.1049/iet-pel.2011.0130

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