converters, to provide zero-voltage turn-on, or is .... During this stage, power is transferred from the input ... This stage finishes when Vcl(t)= V,,l2 and VC2(t)=0.
DC/DC CONVERTER FOR HIGH INPUT VOLTAGE: FOUR SWITCHES WITH PEAK VOLTAGE OF ViJ29 CAPACITIVE TURN-OFF SNUBBING, AND ZERO-VOLTAGE TURN-ON
Ivo Barbi and Roger Gules Power Electronics Institute - UFSC P. 0. Box: 5119 Florianopolis - SC - Brazil 88040-970
Richard Red1 ELF1 S.A. Derrey-la-Cabuche CH-1756 Onnens (FR) Switzerland
Abstract- A new four-switch full-bridge dcldc converter topol’ogy is especially well-suited for power converters operating from high input voltage: it imposes only half of the input voltage across each of thie four switches. The two legs of a full-bridge converter are connected in series with each other, across the dc input source, instead of the usual topology in which each leg is connected across the dc source. The topology reduces turn-off switching losses by providing capacitive snubbing of the turn-off voltage transient, and eliminates capacitor-discharge turn-on losses by providing zero-voltage tuirn-on. (Switching losses are especially important in converters operating a t high input voltage because turn-on losses are proportional to the square of the input voltage, and turn-off losses are proportional to the input voltage). The topology is suitable for resonant and nonresonant converters. It adds one bypass capacitor and one commutating inductor to the minimum-topology full-bridge converter (that inductor is already present in many present-day converters, to provide zero-voltage turn-on, or is associated with one o r two capacitors to provide resonant operatiton), and contains a capacitor in series with the output transformer (that capacitor is already present in resonant power converters). The paper gives a theoretical analysis, and experimental data on a 1.5-kW example that was built and tested: 600 Vdc input, 60 V output a t up to 25 A, and 50kHz switching frequency. The measured performance agireed well with the theoretical predictions. The measured efficiency was 93.6% a t full load, and was a maximum of 95.15% a t 44.8% load.
breakdown voltage, with the disadvantages of higher cost and higher “on” resistance than would be the case if the transistors could be rated for operation at (for example) half of that voltage. In a previous approach [l], each switch was realized as two transistors in series, with voltage-balancing components that would cause the two transistors to share the voltage equally. Then each transistor would sustain only half of input voltage. This approach worked well, but the equipment cost had to include the cost of eight power transistors for the full-bridge. In the new approach proposed here, shown in Fig. 1, the two legs of the full bridge (each leg containing the usual two switches in series) are connected in series across the supply voltage. The node at which the two legs is joined are held at half of the input voltage, by bypasdfilter capacitors that are connected to each of the two input rails. (This adds one more bypass capacitor to the usual input bypassing). As in many present-day full-bridge converters, e.g., [ 2 ] , this topology can be operated with (a) capacitive turn-off snubbing to reduce turn-off switching power losses and (b) resonant transitions that provide zerovoltage turn-on to eliminate turn-on switching power losses. However, a different timing of the switch operations is used, shown in the next section.
11. THE CIRCUIT AND PRINCIPLE OF OPERATION
A . Circuit Description Fig. 1 shows the power-stage circuit. The upper leg comprises SI and Sz; the lower leg comprises S3 and Sq. The example design that was built and tested (Section V) used MOSFET switches. In each MOSFET switch, the internal substrate diode conducts inverse-polarity current and clamps the switch reverse voltage at about I V. (If bipolar junction transistors are used, external anti-parallel diodes should be added.) The MOSFET internal CO,,capacitances are used as C1-C4,providing capacitive turn-off snubbing. In some applications (but not in the example in Section V), the internal capacitances can be supplemented with external capacitors that should be connected across the switches with as low wiring inductance as possible.
I . INTRODUCTION In conventional full-bridge converters, the four switches must sustain the input voltage when they are “off’. In applications using high values of input voltage, such as railway traction, that voltage can be larger than the safe operating voltage of power transistors that the; designer would like to use, i f it
would be possible. A straightforward way to meet the requirements is to iise transistors with sufficiently high
0-7803-4489-8/98/$1 CI.00 0 1998 IEEE
Nathan 0. Sokal Design Automation, Inc. 4, Tyler Road Lexington, MA 02 1732404 USA
I
power transfer and the output/input voltage ratio are controlled by the duty ratio (D) of the switches SI and S3; the switches S2 and S4 operate as the complements of SI and S3, respectively. The six sequential circuit states are described below. I ) Stage I (Fig. 2.a): Power transfer. During this stage, power is transferred from the input source (V,,) to the load through switches SI, Drl, Dr4 and S4. The voltage stored on the series capacitor (Vcs) is VInl2and the voltage applied across L, is (VI,, - Vcs). 2) Stage 2 (Fig. 2.b): Commutation of switch SI. At the instant tl, switch SI is turned off at zero voltage, capacitor C1begins to charge, and C2 begins to discharge linearly with time, with a constant current. This stage finishes when Vcl(t)= V,,l2 and VC2(t)=0. 3) Stage 3 (Fig. 2.4: Free-wheeling stage. The voltage across C2 becomes zero and diode D2 begins to conduct. During this stage, the resonant inductor current (iL,) is approximately constant. The circuit operates in a free-wheeling mode, with current flowing from +Vln,through Clnl,DZ,and L,, through the parallel combination of L, and the rectifiers (reflected to the primary side), and through CS and S4. Because free-wheeling current flows through both polarities of the rectifier, the output voltage is zero. In this stage, switch S2must be gated on. 4) Stage 4 (Fig. 2.4: Commutation of switch S,.. At the instant t3, the switch S4 is turned off at zero voltage and the capacitor C4 begins to charge while the capacitor C3 begins to discharge in a resonant way. This stage finishes when Vc4(t)= V,,/2 and Vc3(t)=0.
The input capacitors Clnl and Cln2bypass the input voltage and generate a bypassed dc mid-point voltage of V,,/2. As the switches go through their cycle of switching, to be discussed below, each switch has V,,,l2 applied across it while it is “off’. Cs is a dc-blocking capacitor that blocks the dc voltage of V,,,/2 from being applied to the series combination of L, and Trf. In this application, Cs is large enough to act as only a dc voltage source, to prevent dc current from flowing through L, and Trf. If a resonant load network is used, CS can be the series-connected resonance capacitor. The stored energy in L, charges and discharges the snubbing capacitors C1- C4 during a conduction gap that is provided between tuming-off one of a pair of switches and turning-on the other switch of the pair. That action brings the switch voltage to zero before the switch is turned-on. L, comprises the sum of an external inductor and the internal primary-side leakage inductance of the transformer. The transformer provides galvanic isolation and voltage transformation, between the source and the load &. DR1 and DR2rectify the rectangular-wave output of the transformer, and Lo and COfilter-out the ripple in the rectified output.
Vi n
Fig. 1. Power circuit of the proposed converter. Vir
B. Principle of Operation To simplify the explanation and the analysis of circuit operation, the following assumptions are made: . All components are ideal. . The ripple in the DC voltage across the series capacitor Cs and the input capacitors Clnl and Cm2is negligibly small. . The output filter and load are replaced by a current sink I,. * The analysis is based on the circuit reflected to the primary side of the transformer, where L, represents the mutual inductance in the transformer’s T equivalent circuit and the leakage inductance is absorbed into L,. . The output rectifier is replaced by four rectifiers diodes. Fig. 2 shows the resulting equivalent circuit, referred to the primary side of the transformer. The six subsections of the figure show the six successive circuit configurations during a half-period of the cycle of switching. The second half-period is the mirror-image of the first half-period, to be described shortly. Fig. 3 shows the switch-timing sequence for the four switches, and the resulting circuit voltages and currents. The
I
(
I
! (c)
I
I
1
/
1
1
(4
(e) 8 Fig 2 Operation stages of power converter
2
5)Stage 5 (Fig. 2.e):Discharge of resonant inductor energy. When the voltage Vc3 becomes zero, the diode D3 begins to conduct and the current through L, begins to decrease linearly with a voltage -Vcs applied to its terminals. During this stage, the switch S3 must be gated on. 6) Stage 6 (Fig. 2.j: Charge of resonant inductor energy. In Stage 6, the: resonant inductor current becomes negative and switches S2-S3 begin to conduct at zero voltage and zero current. When the current through L, reaches the value -I,/n, the free-wheeling in the output rectifier is finished and power is transferred from the series capacitor to the load. In the discharge and charge of resonant inductor energy (Stages 5 and 6), a reduction in the duty ratio occurs, because during these stages a gate signal is applied to the S3 switch, but the free-wheeling in the output rectifiers maintains zero voltage across the power transformer.
where: Vi, - Input voltage Vcs - Series capacitor voltage n - Transformer turns ratio (Np/Ns) D/2 - (t7-t4)/T The voltage on the dc-blocking capacitor (Vcs) is
Vcs =-Vin
2 Then, the output voltage is
(3) But the output voltage is controlled by an effective duty ratio that is smaller than the nominal duty ratio: Deff = D - A
(4)
where A is the reduction of duty ratio caused by the conduction gap. That reduction can be calculated by determining the duration of Stages 5 and 6 (discussed in Section 11). The current in L, will be considered to be constant during the fi-ee-wheeling stage, and the current in L, is neglected. Then, the current in L, during Stages 5 and 6 is
At time tg, iL, = -1Jn.
This occurs two times in the period T. Then the total reduction of duty ratio during the period is
I
A
S. L,. f.”
= L Vin
Therefore the reduction in the duty ratio is proportional to L, and the load current. Substituting the effective duty ratio of (8) in place of the firstapproximation duty ratio in (3), we obtain, for the output voltage,
Fig. 3. Main theoretical waveforms.
In the waveforms of Fig. 3, note that the maximum voltages across the “off’ switches are only V1,/2 because the join-point of Clnl and Cln2 is at voltage V,,/2: the voltage across SI or S2 is the voltage on Cl,,, and the voltage across S3 or S4 is the voltage on C,,2, but both of those capacitor voltages are V1,/2.
(9)
111. ANALYSIS B. Turn-onand turn-offswitching Turn-ofl The turn-off losses are reduced by the action of the snubber capacitors that are in parallel with the switches.
A. Output Characteristic At first, temporarily neglecting the reduction of duty ratio caused by the conduction gap that allows the zerovoltage tum-on, the average voltage at the load (V,) is
3
2) Resonant inductor L,: The resonant inductor L,is defined by the maximum duty ratio reduction specified and is calculated from (8).
Turn-on: The converter uses zero-voltage tum-on to eliminate the turn-on switching losses. The active switches are turned on while the anti-parallel diodes are conducting, so the switches turn-on at essentially zero voltage and almost zero current. But turn-on losses occur if the turn-off snubber capacitors are not filly discharged. Switches S1 and S3 turn-off in the powertransfer stage (Stage 1 in Section II), and the output current referred to the primary accomplishes the charge and discharge of the snubber capacitors (linearly with time). The large stored energy of the ripple-filter inductor Lo is available for this purpose, so, as a practical matter, S2 and S4 will always be turned-on at zero voltage. But switches S2 and S4 turn-off in the free-wheeling stage (Stage 3 of Section II), during which the transformer is short-circuited by the output rectifier. Thus, only the energy stored in the circuit inductance L, (that includes the transformer primary-side leakage inductance) is available to charge and discharge the snubber capacitors, in a resonant way. The minimum current that maintains zero-voltage turn-on for S1 or S3
L,
-A.y!L-
0.12. 6oo 8 . f . L 8.50.103 .$-
= 24.spH
(1 3)
n
3) Series capacitor Cs: The series capacitor Cs must be large enough that it can be treated as a voltage source. The voltage ripple on CS produces a small reduction of the voltage across the transformer primary winding, from the idealized value of Vin/2. Thus, the required value of Cs is calculated as a function of the maximum allowable ripple voltage. The relationship between the ripple voltage and the current in Cs is
ics = Cs .-AVCS At
Then the series capacitor is calculated as
is
Limiting the voltage ripple to 3.5% of its average value, yields
where C is the snubber capacitor (C=C1=C2=C3=C4)
A larger value of L, decreases the primary-side current needed to obtain zero-voltage turn-on of S1 and S3, but the inductance of the resonant inductor L, is limited by the maximum allowed reduction of duty ratio (see (8) ). Section IV gives a design example that includes the effect ofthat reduction of duty ratio.
c, 2
The input data for the design of an example converter are: Input voltage: V,, = 600 V Output Voltage V0=6OV Output power: Po = 1500 W Output current: I, = 25 A Switching frequency: f = 50 kHz
where: At =
and diodes and considering: D = 0.8 Nominal duty-ratio: Maximum duty ratio reduction: 15% of the nominal value of D.
= 7pF
~
( ~ - D ) . T (1-D) 2 2.f
I and iCin = -92.n
Then the input capacitors are calculated as Cinl = Cin2 2
A = 0.15 * D = 0.15.0.8 = 0.12 (1 1) The transformer turns ratio is calculated from (9).
vo
2.3.4.50. lo3 .10.5
iCin = Ci, .-Avcin At
A. Determination ofpassive components 1) Transformer turns ratio: Assuming ideal switches
n = Vin.(?)
25
(16)
4) Input capacitors: The input capacitors Clnl and Cln2can be calculated by the same method used above for Cs. The voltage stored on the input capacitors and the voltage ripple are applied across the switches. It is reasonable to allow 5% voltage ripple in the voltages across Clnl and Cln2. The relationship between the capacitors’ ripple voltages and the currents in the capacitors is
IV. SIMPLIFIED DESIGNEXAMPLE
0.8 - 0.1 2 - 600.(2) = 3.4
= 0.035.300 = 10.5V
AV,,
I, . (1 - D) 4 . n , f . AV,;,
Allowing 5% voltage ripple, we have AVcin = 0.05.300 = 15V
(19)
Then the input capacitances are:
(12)
60
c.in1 - c .in2 >-
4
25. (1 - 0.8)
4.3.4.50. lo3 .15
= 0.5pF
5) Outputfilter: The output filter can be calculated as for a conventional full-bridge converter. The inductance and capacitance of the filter are calculated with (20) and (21), to provide a maximum current ripple AI, of 10% and a maximum voltage ripple AV, of 1%.
-
2) Output rectiper: For the output rectifier shown in Fig. 1, the diode reverse voltage is
.n
600 Lo I,,," = -
16.50.lo3 .3.4.2.5
(28)
= 88.23pH
AI0 =
2.5
-
- IS4",% = ___ 3.42;2 - 5.2A
Vi"
LotnLn 16. f. Ai
CO,"
1s2,
= 10.4pF
--
%50.103 .0.6
Maximum allowable series resistance of output capacitor CO:
The interaction of the transformer leakage indutance with the rectifier capacitance and the reverse-recovery process of the rectifier causes overshoot of the diode reverse voltage, which can be controlled by using softrecovery rectifiers and a reverse-voltage clamping circuit such as the one shown in Fig. 4. The rectifier-diodes7 average and rms currents are needed for the same reasons as are the switch currents. They are given by
Idrnns =
B. Switches voltage and current stresses I ) Active Switches: The maximum voltage across the "off' switches is
The switch rms current is needed if one wishes to calculate the coriduction power dissipation in the switch, to estimate the needed cooling capability and to estimate the expected converter efficiency by knowing the sum of all of the losses. The average and rms currents through S,, and S3 are Io D
= k3,,,,, = -.-
n 2
-I$=
2
= 17.667A
V. EXPERIMENTAL RESULTS To veri@ the practical aspects of the proposed converter, the example design of Section IV was built and tested. Fig. 4 is the circuit diagram, including details about the components. The transformer and L, cores were Thomton IP-12 ferrite. The effective value of L, was 24.5 pH: an actual wound inductor of 20.5 pH, in series with the 4 pH primary-side leakage inductance of the transformer. The MOSFET body diodes were used for DI-D4of Fig. 1, and the MOSFET CO,, capacitances were used for C1-C4 of Fig. 1. r--t--
MUR 140
= -.25 O" = 2.94A
lsla,,g=
3.4 2
Lu=XU uH EEW20 IP12
-+I
.
.
MUR 140
The average and rms currents through S2 and S4 are
-
' ~ 2 a , , : - 's4:tvg
_- 2.n 10
(26)
25 IS2,,&!= IS#4',,, = 2.3.4 - 367A -- I O
I%
= IS4.,,
-
(27)
Fig.4. Circuit diagram of the laboratory prototype.
Figs. 5 through 11 are oscilloscope waveforms of the principal voltages and currents, recorded while the converter was supplying I .5 kW of output power (25 A at 60 Vdc), with 600 Vdc input. All of the observed waveforms agree well with the theoretical waveforms in Fig. 3. Figs. 5 and 6 demonstrate the principal characteristic of this converter topology: the switch peak voltages are 300 V, half of the 600-Vdc input voltage.
Fig. 9. Commutation of the switch S3 (100 V/div - 5 Mdiv - 5 ps/div).
Fig , 5. Drain-source voltages across SI and Sz (100 Vidiv - 5ps/div).
The voltage across the dc-blocking capacitor Cs; the dc value and the ripple are close to the expected values of 300 V and 3.5% of300 V.
F i g , 6. Drain-source voltages across S j and Sq (100 V/div - Sps/div).
Fig. 7 shows the currents in switches S2 and S3, showing the different conduction times of the two groups of switches.
Fig. 10. Voltage across the dc-blocking capacitor CS (1 00 V/div - 5 psldiv).
Fig. 11 shows the current through L,; the maximum positive and negative values are close to the expected I,/n = (25 AIl3.4 = 7.35 A.
Fig. 7. Currents through SZand (5 N d i v - 5ps/div ).
S3
Figs. 8 and 9 shows the current and voltage of switches S2 and S3, showing clearly the mechanism of the zero-voltage turn-on switching.
AX7
SOOAO
Fig. 11, Current through the resonant inductor (5 Ndiv - 5 p/div).
Fig. 12 shows the experimental and theoretical (from (9)) dependence of output voltage on output current, with V,, = 600 Vdc and D = 0.78. The output voltage
Fig. 8. Commutation of the switch S2 (1 00 V/div - 5 Aidiv - 5 ps/div).
decreases with increasing output current because the reduction of effective duty ratio increases with increasing current in L,, as the conduction gap increases, as predicted by (8). The measured output voltage is lower than the value predicted theoretically, due to the voltage drop across the transformer winding, output inductor Lo and the semiconductors.
55
---
1--
6
2
10 14 18 Output current ( A )
22
26
Fig 12. Output voltage as function of output current
Fig. 13 shows the measured efficiency of the power circuit as a function of the output current. The efficiency at full load (25 A) was 93.6%; the maximum efficiency (at 1 1.2 A = 44.8% load) was 95.15%.
0
4
8
12
16
20
24
Output current (A)
Fig. 13. Measured efficiency of the proposed converter.
\‘I. CONCLUSIONS This new four-switch power-circuit topology is wellsuited to economical realization of full-bridge dc/dc converters to be operated from dc input voltages of up to twice the maximum voltage that is allowed to be imposed on each switch in the power circuit. The measured performance of an example 1.5-kW dc/dc converter (600 Vclc input to 60 Vdc output at up to 25 Adc) agreed well with theoretical predictions.
REFERENCES
J. R. Pinheiro and I. Barbi, “The Three-Level ZVS-PWM DC-to-DC Converter”, IEEE Trans. on Power Electronics, vol. 8, no 4, pp.486-492, October 1993. R.Redl, L.13alogh & N. 0. Sokal, “A Novel Soft-Switching Full-Bridge DC/DC Converter: Analysis, Design Considerations, and Experimental Results at 1.5 kW, 100 kHz”, IEEE Trans. on Power Electronics, vol. 6, no. 3, pp. 408-418, July 1991.
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