IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 6, JUNE 2015
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Degradation of Gate Voltage Controlled Multilevel Storage in One Transistor One Resistor Electrochemical Metallization Cell Xiaoxin Xu, Student Member, IEEE, Hangbing Lv, Yuxiang Li, Hongtao Liu, Ming Wang, Qi Liu, Shibing Long, and Ming Liu, Senior Member, IEEE
Abstract— Multilevel per cell (MLC), achieved by controlling the compliance current during SET operation, is a common approach to realize high-density storage in resistive random access memory (RRAM). In this letter, we investigated the failure mechanism of the MLC storage in one transistor and one resistor structure. By commonly modulating the amplitudes of gate bias to achieve the MLC, we found some unexpected failed SET operations, which caused the shrinkage of the MLC margin. In situ monitoring of the dynamic voltage drops on both transistor and memory cell revealed that there was an abnormal rise of source potential of the transistor, resulting in the increase of threshold voltage of the access transistor. If the applied gate bias was below the increased threshold voltage, the transistor would not program the RRAM cell successfully. Finally, possible improvement approaches to solve this problem are suggested. Index Terms— One transistor and one resistor (1T1R), resistive random access memory (RRAM), ECM, multi-level cell (MLC).
I. I NTRODUCTION ESISTIVE random access memory (RRAM) is gaining continuous interests from research communities, stemming from its competitive capability for embedded and highdensity applications [1]–[5]. Due to the popular utilization of copper in connection of back-end-of-line (BEOL), integrating the electrochemical metallization cell (ECM) (a typical class of RRAM) on the top of copper plug or copper line is the most cost-effective way [2]. Multi-level per cell (MLC) is important to achieve high-density storage for RRAM. In 1R structure, different resistance states can be easily achieved by controlling the compliance current with an external current limiter in SET process [5]–[8]. In practical application, MLC is carried out by tuning the gate voltage of transistor. Here, the
R
Manuscript received February 11, 2015; revised March 16, 2015 and April 21, 2015; accepted April 23, 2015. Date of publication April 28, 2015; date of current version May 20, 2015. This work was supported in part by the Ministry of Science and Technology, China, under Grant 2011CBA00602, Grant 2010CB934200, Grant 2011CB921804, Grant 2011CB707600, Grant 2011AA010401, and Grant 2011AA010402, and in part by the National Natural Science Foundation of China under Grant 61322408, Grant 61334007, Grant 61376112, Grant 61221004, Grant 61274091, Grant 61106119, Grant 61106082, and Grant 61006011. The review of this letter was arranged by Editor T. San. The authors are with the Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China (e-mail:
[email protected];
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2015.2427393
additional transistor integrated with the memory cell acts as a compliance current limiter, and this structure is called as one transistor one resistor (1T1R) structure [9]–[11]. Compared with 1R structure, the operation principle in 1T1R structure is much more complicated. The voltage drops on the transistor and memory cell will be dynamic. In addition, body effect caused by potential rising on source terminal could affect the controllability of the transistor. Thus, these issues will greatly influence the MLC capability in 1T1R structure. Therefore, there is an urgent demand to clarify the underlying mechanism of MLC storage in 1T1R structure. In this letter, we investigated the failure mechanism of MLC storage in HfOx -based ECM device with 1T1R structure. We found the MLC ability in this structure would degenerate by traditionally modulating the amplitudes of gate voltage. This failure was resulted from the potential rise of source terminal during programming. In order to guarantee a high programming yield, the gate voltage should be kept above a certain value. So the MLC capability was limited by the controllability of the effective gate voltage, leading to the degradation of MLC margin. Possible improvement approaches to guarantee a satisfied MLC margin in 1T1R structure were discussed finally. II. E XPERIMENT The ECM device with Cu/HfOx /Pt structure was integrated on the NMOS transistor fabricated by the standard 0.13 µm CMOS process to form the 1T1R structure. Cu plug after chemical mechanical polish (CMP) served as the bottom electrode. The HfOx switching layer and Pt top electrode were grown by ion beam sputtering and electron-beam evaporation successively, with thickness of 4 nm and 70 nm, respectively. The channel width/length of the transistor is 10 µm/1 µm. The size of RRAM device is 300 nm × 400 nm, defined by the bottom Cu plug. The electrical characteristics of the devices were preliminary measured by Keithely 4200 SCS semiconductor parameter analyzer. III. R ESULTS AND D ISCUSSION In the forming/SET process, positive voltage bias was applied on the gate to turn on the access transistor and provide compliance current (ICC ). The drain terminal of 1T1R was forced by voltage sweeping, while the top electrode of the
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IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 6, JUNE 2015
Fig. 1. The I-V characteristics with different gate bias for Cu/HfOx (4 nm)/ Pt 1T1R device. The resistive switching phenomenon didn’t happen when VG = 1.5 V and 1.8 V. Insert: Schematic of the 1T1R device.
Fig. 2. (a) The ID -VD characteristic curves of the selecting transistor in our experiment. The saturation currents corresponding to the VG = 1.5 V and 1.8 V are 0.25 mA and 0.58 mA. (b) The program process of the RRAM, it shows that current of 5 nA is needed for a memory device switched successfully.
RRAM was kept on ground (insert of Fig.1). Fig. 1 shows the I-V characteristics under different gate biases (1.5 V, 1.8 V and 2.1 V) with the same VD sweeping range (0-2 V), which illustrates the failed operation under the gate bias of 1.5 V and 1.8 V. In order to guarantee a high programming yield, the applied gate voltage should be higher than 2.1 V, leading to the LRS to be around 400 !. In other words, the available resistance state range for MLC would be limited below 400 !. By testing the transistor and memory cell separately, we found their performances exhibited normally, as shown in Fig. 2. The saturation currents under 1.5 V and 1.8 V gate biases were 250 µA and 580 µA, respectively, whereas the switching current of the standalone RRAM was as low as 5 nA (Fig. 2(b)). It means that the saturation currents under 1.5 V and 1.8 V gate biases should be sufficient to drive the switching of RRAM cell in 1T1R. In order to find out the reason of the MLC failure, voltage drop on RRAM (VRRAM ) during programming is in-situ monitored by measuring the voltage of source electrode of the transistor (VS in the inset of Fig. 1). The relations of voltage/current of RRAM versus drain voltage (VD ) are shown in Fig. 3(a). Two obvious stages of the VRRAM evolution are observed. Firstly, VRRAM increases linearly with the VD . At this stage, most of the voltage drops on RRAM because its resistance (about 107 !) is much higher than the transistor’s
Fig. 3. (a) Dependence of the voltage drop on RRAM (black curve) and the current flowing through 1T1R (red curve) on the sweep voltage between source and drain with VG = 1.5 V. (b) Curve groups for different VG and RHRS , the VRRAM at the insertion indicates the max program voltage for certain VG and RHRS in 1T1R architecture.
under 1.5 V gate bias. The current flowing through the transistor and memory cell can be expressed by: IR =
V R R AM VS ≈ RH RS RH RS
(1)
As the VRRAM increases, VS (equal to VRRAM ) is raised spontaneously. Meantime, the threshold voltage of transistor is increased from Vth to Vth +VRRAM . It should be mentioned that body effect may also influence the drift of Vth . However, the increment portion from body effect can be neglected compared with that from the source potential rising. In order to keep the transistor open, the VG should be larger than Vth +VRRAM . When the VRRAM increases to a certain level (Vth +VRRAM ≈ VG ), the transistor would turn off, and the turning points (A) and (B) sketched in Fig. 3(a) appears. In this case, the VRRAM is statured and independent of the applied drain voltage. As can be seen in Fig. 3(a), the current at the turning point is about 10−7 A, which is lower than the typical value (10−6 A) in the definition of threshold voltage of transistor. In other words, the transistor at the turning point actually works at sub-threshold region. The current flows through the transistor can be expressed by: I D S ∝ I0 exp(VG − V R R AM − Vt h )
(2)
Based on this finding, the VRRAM at the turning point could be well determined by the load resistance plotting of the transistor. Fig. 3(b) shows the curve groups by plotting the load resistance with different VG and RHRS . The voltage at the cross-point of the IR curve and IDS curve should be the exact
XU et al.: DEGRADATION OF GATE VOLTAGE CONTROLLED MULTILEVEL STORAGE
Fig. 4. (a) The I-V curves for 1T1R devices with different thickness HfOx layer in SET program. (b) The multi-level RLRS can be realized through applying different ICC by modulating the VG for Cu/HfOx (3 nm)/ Pt 1T1R device.
VRRAM at the turning point. In the case of VG = 1.5V and RHRS = 107 !, the saturation of VRRAM is about 1V which is in good accordance with the value of VRRAM in Fig. 3(a). In order to guarantee a high programming yield, the gate voltage for SET operation should be approximated higher than VSET +Vth . The RRAM device with low SET voltage and high HRS is helpful to reduce the strict requirement of VG and thus increase the MLC margin. There are a variety of methods to reduce the program voltage, including doping, thickness scaling, interface engineering, or chemical treatment [12]–[14]. As shown in Fig. 4(a), the program voltage is reduced greatly by decreasing the thickness of HfOx . The SET voltage was lower than 0.5 V for the memory cell with 3 nm HfOx . As shown in Fig. 4(b), the multi-level RLRS can be achieved successfully under different ICC by modulating the gate voltage in Cu/HfOx (3 nm)/Pt 1T1R device. It should be mentioned that the RESET variation exists in the 3 nm device, which may bring trouble to the MLC storage and more efforts are needed to improve the device-to-device and cycle-to-cycle uniformity [15]. In addition, adopting PMOS transistor as the access device could also prohibit the rising of source potential. However, the driving current provided by PMOS is much lower than that by NMOS with the same width/length ratio. Converting the copper as the top electrode is another approach to solve the issue. All approaches would increase the area of the cell in some degree. The adoption of 4-terminal NMOS, by contrast, is a better choice to avoid the source potential rise by the voltage drop on RRAM. IV. C ONCLUSION In this letter, we systematically investigated the MLC failure mechanism in HfOx based ECM cell with 1T1R structure.
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During the SET operation, the threshold voltage of transistor was found to increase with the rising of source potential, which directly leads to the failure of programming operation. In order to guarantee a high programming yield, the gate voltage should be kept above a certain value (Vth +VRRAM ). The RRAM cell with lower SET voltage and higher HRS resistance would be benefit to achieve high MLC capability. The results in this work provide a possible guideline for device structure designing. R EFERENCES [1] R. Waser and M. Aono, “Nanoionics-based resistive switching memories,” Nature Mater., vol. 6, no. 11, pp. 833–840, Nov. 2007. [2] I. Valov et al., “Electrochemical metallization memories— Fundamentals, applications, prospects,” Nanotechnology, vol. 22, no. 25, pp. 1–24, May 2011. [3] H. Lv, H. Wan, and T. Tang, “Improvement of resistive switching uniformity by introducing a thin GST interface layer,” IEEE Electron Device Lett., vol. 31, no. 9, pp. 978–980, Sep. 2010. [4] M.-M. Tsai et al., “Bipolar resistive RAM characteristics induced by nickel incorporated into silicon oxide dielectrics for IC applications,” IEEE Electron. Device Lett., vol. 33, no. 12, pp. 1696–1698, Dec. 2012. [5] S. Z. Rahaman et al., “Low power operation of resistive switching memory device using novel W/Ge0.4 Se0.6 /Cu/Al structure,” in Proc. IEEE Int. Memory Workshop, May 2009, pp. 1–4. [6] C. Schindler et al., “Bipolar and unipolar resistive switching in Cu-doped SiO2 ,” IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2762–2768, Oct. 2007. [7] N. E. Gilbert and M. N. Kozicki, “An embeddable multilevel-cell solid electrolyte memory array,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1383–1391, Jun. 2007. [8] B. Chen et al., “Multi-level resistive switching characteristics correlated with microscopic filament geometry in TMO-RRAM,” in Proc. Int. Symp. VLSI Technol., Syst., Appl. (VLSI-TSA), Apr. 2013, pp. 1–2. [9] Z. Fang et al., “Fully CMOS compatible 1T1R integration of vertical nanopillar GAA transistor and oxide based RRAM cell for high density nonvolatile memory application,” in Proc. IEEE 5th Int. Nanoelectron. Conf. (INEC), Jan. 2013, pp. 228–230. [10] F. Nardi et al., “Control of filament size and reduction of reset current below 10 µA in NiO resistance switching memories,” Solid-State Electron., vol. 58, no. 1, pp. 42–47, Apr. 2011. [11] M. Zangeneh and A. Joshi, “Design and optimization of nonvolatile multibit 1T1R resistive RAM,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1026–1028, Aug. 2011. [12] Q. Liu et al., “Formulation of multiple conductive filaments in the Cu/ZrO2 :Cu/Pt device,” Appl. Phys. Lett., vol. 95, no. 2, p. 023501, Jul. 2009. [13] W. H. Guan et al., “On the resistive switching mechanisms of Cu/ZrO2 :Cu/Pt,” Appl. Phys. Lett., vol. 93, no. 22, p. 223506, Dec. 2008. [14] M. Wang et al., “Investigation of one-dimensional thickness scaling on Cu/HfO x /Pt resistive switching device performance,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1556–1558, Nov. 2012. [15] H. Liu et al., “Uniformity improvement in 1T1R RRAM with gate voltage ramp programming,” IEEE Electron Device Lett., vol. 35, no. 2, pp. 1224–1226, Dec. 2014.
