Design and Evaluation of High-Speed Operational

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Design and Evaluation of High-Speed Operational Amplifier Designs Using the Negative Miller Capacitance Design Technique

Author: Muhaned Ali Hussein Zaidi

Supervisors: Dr Ian Grout Professor Abu Khari Bin A’ain

Award the Doctor of Philosophy Department of Electronic and Computer Engineering

Submitted to the University of Limerick, October 2018 I

Abstract The operational amplifier (op-amp) is one of the most commonly used analogue circuits for analogue and mixed-signal Integrated Circuit (IC) designs. The op-amp is widely designed using a sub-micron Complementary Metal-Oxide-Semiconductor (CMOS) technology, for example, by making use of 0.35, 0.18, and 0.13 µm technology nodes. However, there are different techniques available to design the op-amp for different circuit requirements. For example, rail-to-rail operation is a common requirement for low-voltage operation where rail-to-rail operation can denote the input, the output, or both input and output, and, have a dynamic range that can reach the limits, or close to the limits, of the power supply voltage. However, all op-amps are required to have a suitable open-loop margin of stability in order for them to be used in a negative feedback closed-loop configuration with an appropriate frequency response. Therefore, openloop configuration should have a 45° or higher phase margin, which is achieved by using compensation techniques. Different compensation techniques could, therefore, be employed to achieve a required stability and frequency response. These compensation schemes could be employed individually or in combinations. In this work, techniques for op-amp compensation are identified and evaluated. The compensation schemes considered in this work are conventional (direct), indirect, and negative Miller compensation. A requisite condition for the op-amp designs is that they need to work at low-voltage and low-power. For low-voltage operation, the op-amp is designed using the gm/ID approach for the purpose of determining transistor dimensions. Each op-amp design is based on a single-rail power supply operating at, or below, +3.3 V. Moreover, the op-amp is designed such that the transistors can operate in weak and moderate inversion regions in addition to strong inversion. A serious drawback of transistor circuit designs operating in weak and moderate inversion is that it can reduce the frequency response performance of the op-amp. Direct and indirect Miller capacitances are used to reach the required margin of stability. However, by applying the negative Miller capacitance (negative Miller compensation) to specific nodes within the circuit, the amplifier bandwidth can be increased. The compensation techniques are considered within a two-stage CMOS op-amp with both single-ended and fully differential outputs. Negative Miller capacitance is used around the first stage whilst direct and indirect Miller capacitances are used around the second stage. The outline of this thesis is as follows. Chapter 1 will introduce the work undertaken in this research project, considering low-voltage and frequency response issues. The novel aspects of the work completed will also be identified. Chapter 2 will provide an overview of the MOSFET transistor large and small-signal operation as well as describing the gm/ID design approach. The gm/ID design approach is considered as it is suitable for use in low-voltage, low power analogue circuit design. Chapter 3 will introduce the two-stage CMOS op-amp architecture and amplifier compensation techniques used in work. Specifically, conventional (direct), indirect and negative Miller compensation have been utilised. Chapter 4 will present the rail-to-rail single ended output op-amp with Cadence Spectre simulation study results and a physical prototype device that was fabricated using the Austria Mikro Systeme (AMS) 0.35 µm n-well CMOS fabrication process. Chapter 5 will present the rail-to-rail CMOS op-amp with a fully-differential output. Chapter 6 will focus on the design and operation of a programmable op-amp and will present two different programming approaches. Chapter 7 will provide conclusions to the work and identify future research directions. i

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Declaration

A research project submitted in partial fulfilment of the requirements for the degree of Doctor of Philosophy in the University of Limerick. I declare that this research is my effort. It has not been presented before for any other degree, part of a degree at this or any other university. However, I have made a reasonable effort to ensure that the work is original, as far as I know, the law of copyright the publication was taken from other sources only in cases where the act was cited and recognised in the text.

Name _____________________________________________________

Signature ______________________________________________

Date _______________________________________________________

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Dedication

I am dedicating this thesis to all people who have meant and continued to mean so much to me.

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Acknowledgements

Initially, I would like to thank my supervisor, Dr Ian Grout, for his supervision and assistance through the various stages of this work. Thanks to professor Abu Khari Bin A’ain for assistance. I would like to thank and indebtedness go to the Ministry of Higher Education and Scientific Research (Iraq) / Wasit University (Iraq) for granting me the scholarship to pursue my higher studies. I would like to thank all faculty members and staff of the department of electronic and computer engineering. I would like to thank my love of my live “my wife Weam” for supporting me all difficult time, without her help and support, this thesis would not have seen the light. I would like to thank my angales My daughter “Meyar” and My little boy “Adam”. A greatest thank to “my parents” for guidance and support because of them I reached my goals. You give me a hug when I can’t find my voice. You wipe away the tears that the world makes me weep. I would like to thank my brother, sisters and my friends for their continued patience, love and confidence in me and I would to thank my uncle “Setar and his wife” for every telephone call back home renewed my hopes here.

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Table of Contents

Abstract ........................................................................................................................... i Declaration .................................................................................................................... iii Dedication ...................................................................................................................... v Acknowledgements ...................................................................................................... vii Table of Contents .......................................................................................................... ix List of Figures .............................................................................................................. xv List of Tables............................................................................................................. xxiii Abbreviations ........................................................................................................... xxvii Chapter 1

Introduction ................................................................................................ 1

1.1

Overview ........................................................................................................ 1

1.2

Operational transconductance amplifier and operational amplifier ............... 3

1.3

Applications ................................................................................................... 5

1.4

Design issues .................................................................................................. 7

1.4.1

Low-voltage issues ..................................................................................... 7

1.4.2

Frequency response issues ......................................................................... 9

1.5

Summary of the research .............................................................................. 12

1.6

Thesis outline ............................................................................................... 13

Chapter 2

Design methodologies .............................................................................. 15

2.1

Introduction .................................................................................................. 15

2.2

Metal-oxide-semiconductor field-effect transistor ....................................... 15

2.2.1

Large-signal model................................................................................... 17 ix

2.2.2 Small-signal model................................................................................... 18 2.2.3 MOSFET capacitances ............................................................................. 19 2.3

Transconductance efficiency design for all inversion regions ..................... 20

2.3.1 Inversion regions ...................................................................................... 21 2.3.2

gm/ID design and inversion region ............................................................ 26

2.3.3 Conventional and gm/ID design techniques .............................................. 28 2.3.4 gm/ID design flow...................................................................................... 31 2.3.5

The gm/ID sizing approach ........................................................................ 32

2.3

Temperature effects and the gm/ID design technique.................................... 35

2.4

CMOS technology ........................................................................................ 38

2.4.1 Introduction .............................................................................................. 38 2.4.2 AMS 0.35 µm process .............................................................................. 39 2.4.3 Capacitance .............................................................................................. 39 2.5 Chapter 3

Conclusions .................................................................................................. 40 CMOS operational amplifier structures ................................................... 41

3.1

Introduction .................................................................................................. 41

3.2

Operational amplifier ................................................................................... 42

3.2.1 Two-stage CMOS operational amplifier design ...................................... 44 3.2.2 Folded cascode amplifier ......................................................................... 44 3.2.3 Class-AB output Amplifier ...................................................................... 47 3.2.4 Rail-to-rail input/output op-amp .............................................................. 51 3.2.5 Design of a fully-differential op-amp ...................................................... 52 3.3

Feedback systems ......................................................................................... 53

3.3.1 Introduction .............................................................................................. 53 3.3.2 Properties of the negative feedback systems ............................................ 55 3.4

Compensation techniques............................................................................. 57

3.4.1 Introduction .............................................................................................. 57 3.4.2 Indirect Miller technique .......................................................................... 63 3.4.3 Negative Miller technique ........................................................................ 65 3.5 Chapter 4 4.1

Conclusions .................................................................................................. 70 Rail-to-rail output CMOS operational amplifier design .......................... 71 Introduction .................................................................................................. 71 x

4.2

Op-amp design structure .............................................................................. 72

4.2.1

Design implementation ............................................................................ 72

4.2.2

Layout design ........................................................................................... 77

4.3

Compensation techniques ............................................................................ 79

4.4

Simulations using Cadence Spectre ............................................................. 82

4.4.1

Frequency response .................................................................................. 83

4.4.2

Slew rate and settling time ....................................................................... 91

4.4.3

Output swing range .................................................................................. 95

4.4.4

Comparison of op-amp works .................................................................. 98

4.5

Physical prototype test ................................................................................. 99

4.6

Analysis and discussions ............................................................................ 105

4.7

Applications ............................................................................................... 107

4.8

Conclusions ................................................................................................ 109

Chapter 5

Operational amplifier topology alternatives........................................... 111

5.1

Introduction ................................................................................................ 111

5.2

Rail-to-rail input-output op-amp ................................................................ 112

5.2.1

Architecture and schematic of a rail-to-rail op-amp .............................. 112

5.2.2

Cadence Spectre simulation results ........................................................ 117

5.3

Fully-differential op-amp design................................................................ 126

5.3.1

Architecture and schematic of a fully-differential op-amp .................... 128

5.3.2

Cadence Spectre simulation results ........................................................ 131

5.4

Analysis and discussions ............................................................................ 135

5.5

Conclusions ................................................................................................ 136

Chapter 6

Digitally programmable operational amplifier design and simulation .. 137

6.1

Introduction ................................................................................................ 137

6.2

Digitally programmable analogue .............................................................. 138

6.2.1

Circuit performance alteration ............................................................... 139

6.2.2

Op-amp performance alteration ............................................................. 139

6.2.3

Field programmable analogue array....................................................... 139

6.2.4

Design for testability and built-in self-test ............................................. 140

6.2.5

Mixed-signal programmable system on a chip ...................................... 140

6.3

Programmable bandwidth op-amp with negative Miller compensation .... 141 xi

6.3.1 Analog sub-system ................................................................................. 142 6.3.2 Digital sub-system .................................................................................. 147 6.3.3 Simulation results ................................................................................... 150 6.4

Programmable gain/bandwidth op-amp design basis at tail current .......... 154

6.4.1 Op-amp design ....................................................................................... 155 6.4.2 Programmable control system ................................................................ 160 6.4.3 Simulation results ................................................................................... 162 6.5 Chapter 7 7.1

Conclusions ................................................................................................ 168 Conclusions and future work ................................................................. 169 Summary of the work ................................................................................. 169

7.1.1 Rail-to-rail single ended output op-amp ................................................ 169 7.1.2 Rail-to-rail input and output op-amp...................................................... 170 7.1.3 Fully-differential rail-to-rail output op-amp .......................................... 171 7.1.4 Programmable bandwidth op-amp ......................................................... 171 7.1.5 Programmable gain and bandwidth op-amp .......................................... 171 7.2

Aims of the research ................................................................................... 171

7.3

Proposed future work ................................................................................. 174

7.3.1 First aspect ............................................................................................. 174 7.3.2 Second aspect ......................................................................................... 175 References .................................................................................................................. 177 Appendix A - Publications ……………………………….……….........,,.............…A-1 Appendix B - MOSFET operations…………………………………….………....…B-1 B.1 Large signal model .......................................................................................... B-1 B.1.1 When vGS < VT ......................................................................................... B-1 B.1.2 When vGS ≥ VT and vDS < vDS(sat) .............................................................. B-1 B.1.3 When vGS ≥ VT and vDS ≥ vDS(sat) .............................................................. B-2 B.2 Small signal model .......................................................................................... B-4 B.2.1 Transconductance ..................................................................................... B-4 B.2.2 Output conductance .................................................................................. B-5 B.2.3 The voltage gain of the small-signal gain stage ....................................... B-6 B.3 gm/ID design technique charts .......................................................................... B-7 xii

B.3.1 gm/ID as a function of ID............................................................................ B-7 B.3.2 gm/ID as a function of ID/ (W/L) ............................................................... B-7 B.3.3 gm/ID as a function of the transition frequency ......................................... B-8 Appendix C - CMOS amplifiers…………………..……………………………...…C-1 C.1 Two-stage CMOS operational amplifier design .............................................. C-1 C.1.1 MOSFET differential input stage ............................................................. C-1 C.1.2 Current mirror ........................................................................................... C-1 C.1.3 Active load stage ...................................................................................... C-2 C.1.4 Common-source output stage ................................................................... C-3 C.2 Rail-to-rail input stage ..................................................................................... C-3 C.2.1 Rail-to-rail input stage with complementary differential pairs ................ C-3 C.2.2 Constant-gm rail-to-rail input stage using a one-times current mirror ...... C-8 C.2.3 Class-AB output stage .............................................................................. C-9 C.3 Fully-differential operational amplifier design ............................................. C-10 C.3.1 Fully-differential operational amplifier design ...................................... C-10 C.3.2 Common-mode feedback amplifier ........................................................ C-12 C.4 Miller capacitor ............................................................................................. C-13 C.4.1 Case-study of a conventional op-amp design ......................................... C-19 C.4.2 Case-study simulation ............................................................................ C-21 Appendix D - Op-amp layout design ………………………………….………....…D-1 Appendix E -Design tools and test equipment …………………………………...…E-1 Appendix F - Test board ……………………………………………. …...……...…F-1 Appendix G - List of equations……………………………………….………….…G-1

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List of Figures

Figure 1.1 Block diagram of a common operational amplifier (op-amp) ...................... 1 Figure 1.2 Block diagram of an amplifier ...................................................................... 3 Figure 1.3 Simple op-amp configuration ....................................................................... 4 Figure 1.4 RGB LED driver circuit design for an optical fibre sensor system [12] ...... 6 Figure 2.1 Symbols for the MOSFET with voltages and direction of currents ........... 16 Figure 2.2 Cross section of the MOSFET .................................................................... 17 Figure 2.3 Voltage and current description for the MOSFET ..................................... 17 Figure 2.4 Test circuit for a nMOS transistor with DC and AC operation .................. 18 Figure 2.5 Complete small-signal model for MOSFET (saturation region) ................ 19 Figure 2.6 MOSFET parasitic capacitances ................................................................. 20 Figure 2.7 Properties of MOSFET operation (W=10 µm and L=0.35 µm) ................. 22 Figure 2.8 Drain current versus gate-source voltage ................................................... 22 Figure 2.9 gm/ID versus ID for an nMOS transistor (ratio of W/L=10 µm /0.35 µm) .. 27 Figure 2.10 Flowchart of the gm/ID design process ...................................................... 31 Figure 2.11 Common source amplifier ........................................................................ 32 Figure 2.12 Saturation region in weak inversion ......................................................... 34 Figure 2.13 IV characteristics of an nMOS transistor (M11) operating in the weak inversion region ............................................................................................................ 35 Figure 2.14 IV characteristics of an nMOS transistor (M12) operating in the weak inversion region ............................................................................................................ 35 Figure 2.15 CMOS cross-section view of nMOS and pMOS transistors .................... 38 Figure 2.16 AMS 0.35 µm CMOS process cross-section [54] .................................... 39 Figure 3.1 Operational amplifier (op-amp) circuit symbol .......................................... 42 Figure 3.2 Schematic of a simple operational amplifier .............................................. 44 Figure 3.3 Concept of a folded cascode ....................................................................... 45 xv

Figure 3.4 Folded cascode circuit amplifier ................................................................. 46 Figure 3.5 Amplifier Classes and signals [63] ............................................................. 48 Figure 3.6 Concept of a class-AB output stage. ........................................................... 49 Figure 3.7 Diagram of the output currents of a class-AB ............................................ 49 Figure 3.8 Feed-forward class-AB control structure.................................................... 50 Figure 3.9 Rail-to-rail input/output op-amp concept ................................................... 52 Figure 3.10 Fully-differential op-amp configuration ................................................... 53 Figure 3.11 Basic feedback design with open-loop gain (A) and feedback network (ß) ...................................................................................................................................... 54 Figure 3.12 Negative feedback system ........................................................................ 56 Figure 3.13 Structure overlap capacitance of MOSFET .............................................. 58 Figure 3.14 Miller effect (a) Amplifier with impedance (b) Equivalent circuit .......... 59 Figure 3.15 Folded cascode with the class-AB output stage ....................................... 63 Figure 3.16 Small-signal model of rail-to-rail two-stage op-amp................................ 63 Figure 3.17 Two-stage op-amp folded cascode followed by a class-AB stage with indirect Miller compensation ....................................................................................... 64 Figure 3.18 Small-signal model of the indirect Miller compensation op-amp ............ 65 Figure 3.19 Capacitance modelling of the MOSFET................................................... 66 Figure 3.20 (a) Ideal negative capacitance circuit and (b) Negative Miller equivalent circuit............................................................................................................................ 67 Figure 3.21 Operational transconductance amplifier (OTA) and buffer [109] ............ 68 Figure 3.22 (a) Amplifier stage (b) Amplifier stage with negative Miller [90] ........... 68 Figure 3.23 Gain stage with negative Miller capacitance [92] .................................... 69 Figure 3.24 Negative Miller capacitance modelled around the amplifier .................... 69 Figure 4.1 Two-stage op-amp structure ....................................................................... 72 Figure 4.2 Rail-to-rail output CMOS op-amp with compensation techniques ............ 75 Figure 4.3 Wide-swing cascode circuit ........................................................................ 76 Figure 4.4 Concept of layout design ............................................................................ 79 Figure 4.5 Structure of two-stage class-AB output op-amp using Miller compensation (first op-amp) ............................................................................................................... 80 Figure 4.6 Structure of two-stage class-AB output op-amp using negative Miller and direct Miller compensation (second op-amp) .............................................................. 81

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Figure 4.7 Structure of two-stage class-AB output op-amp using negative Miller and indirect Miller compensation (third op-amp) ............................................................... 82 Figure 4.8 Op-amp block connected to the I/O pads ................................................... 82 Figure 4.9 Frequency response varying with Monto Carlo (first op-amp) (no output load).............................................................................................................................. 86 Figure 4.10 Monto Carlo analysis result: no. of samples versus UGF (first op-amp) (no output load) ............................................................................................................ 86 Figure 4.11 Monto Carlo analysis result: no. of samples versus PM (first op-amp) (no output load) .................................................................................................................. 87 Figure 4.12 Frequency response varying with Monto Carlo (second op-amp) (no output load) .................................................................................................................. 87 Figure 4.13 Monto Carlo analysis result: no. of samples versus UGF (second op-amp) (no output load) ............................................................................................................ 88 Figure 4.14 Monto Carlo analysis result: no. of samples versus PM (second op-amp) (no output load) ............................................................................................................ 88 Figure 4.15 Frequency response varying with Monto Carlo (third op-amp) (no output load).............................................................................................................................. 89 Figure 4.16 Monto Carlo analysis result: no. of samples versus UGF (third op-amp) (no output load) ............................................................................................................ 89 Figure 4.17 Monto Carlo analysis result: no. of samples versus PM (third op-amp) (no output load) .................................................................................................................. 90 Figure 4.18 Frequency response (top) and phase (bottom) at +2.5 V (no output load)90 Figure 4.19 Frequency response gain (top) and phase (bottom) at +1.8 V (no output load).............................................................................................................................. 91 Figure 4.20 Concept of SR and settling time ............................................................... 92 Figure 4.21 Step response (large-signal) at +2.5 V, step (period 1 µs, CL= 5 pF and TM) .............................................................................................................................. 93 Figure 4.22 Step response (small-signal) at +2.5 V, step (period 1 µs, CL= 5 pF) ...... 94 Figure 4.23 Step response (large-signal) at +1.8 V, step (period 100 µs, CL= 5 pF) ... 94 Figure 4.24 Step response (small-signal) at +1.8 V, step (period 100 µs, CL= 5 pF and TM) .............................................................................................................................. 95 Figure 4.25 Transient response at +2.5 V, at 10 kHz (TM and no output load) .......... 96 Figure 4.26 Transient response at +2.5 V, at 1 MHz (TM and no output load)........... 97 xvii

Figure 4.27 Transient response at +1.8 V, at 1 kHz (TM and no output load) ............ 97 Figure 4.28 Transient response at +1.8 V, at 10 kHz (TM and no output load) .......... 98 Figure 4.29 Physical prototype testing open-and closed-loop using the SF880 ........ 100 Figure 4.30 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF) .................................................................... 101 Figure 4.31 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest = 1 MΩ with CTest = 10 pF) .................................................................. 101 Figure 4.32 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF) .................................................................... 102 Figure 4.33 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF) .................................................................... 102 Figure 4.34 Physical prototype testing open-and closed-loop using the SF880 instrument with CL and RL ......................................................................................... 103 Figure 4.35 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF and RL =1 MΩ with CL =10 pF) ................. 104 Figure 4.36 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF and RL =1 MΩ with CL =10 pF) ................. 104 Figure 4.37 PM and UGF versus load capacitance (CL) (+2.5 V) ............................. 106 Figure 4.38 PM and UGF versus load capacitance (CL) (+1.8 V) ............................. 106 Figure 4.39 Non-inverting op-amp circuit ................................................................. 108 Figure 4.40 Inverting op-amp circuit ......................................................................... 108 Figure 4.41 Non-inverting second op-amp 2.5 V (no output load) ............................ 108 Figure 4.42 Inverting second op-amp 2.5 V (no output load) .................................... 108 Figure 4.43 Non-inverting second op-amp 1.8 V (no output load) ............................ 109 Figure 4.44 Inverting second op-amp 1.8 V (no output load) .................................... 109 Figure 4.45 Non-inverting third op-amp 2.5 V (no output load) ............................... 109 Figure 4.46 Inverting third op-amp 2.5 V (no output load) ....................................... 109 Figure 4.47 Non-inverting third op-amp 1.8 V (no output load) ............................... 109 Figure 4.48 Inverting third op-amp ............................................................................ 109 Figure 5.1 Block diagram of the rail-to-rail op-amp .................................................. 113 Figure 5.2 Rail-to-rail input/output op-amp schematic .............................................. 115 Figure 5.3 Rail-to-rail op-amp block connected to the I/O pads ................................ 117

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Figure 5.4 Frequency response varying with process variations and without I/O and power supply pads (VDD = +3.3 V, no output load) ................................................... 118 Figure 5.5 Frequency response varying with process variations and without I/O and power supply pads (VDD = +3.3 V, no output load) ................................................... 119 Figure 5.6 Frequency response varying with process variations with I/O and power supply pads (VDD = +3.3 V, no output load) .............................................................. 120 Figure 5.7 Frequency response varying with process variations with I/O and power supply pads (VDD = +3.3 V, no output load) .............................................................. 120 Figure 5.8 Monto Carlo analysis result: no. of samples versus UGF (VDD = +3.3 V, no output load, TM) ........................................................................................................ 121 Figure 5.9 Monto Carlo analysis result: no. of samples versus PM (VDD = +3.3 V, no output load and TM)................................................................................................... 121 Figure 5.10 Monto Carlo of the frequency response gain (top) and phase (bottom) (VDD = +3.3 V, no output load and TM) .................................................................... 122 Figure 5.11 Frequency response gain (top) and phase (bottom) (VDD = +3.3 V, with output load and TM)................................................................................................... 123 Figure 5.12 Rail-to-rail input and output voltage (VDD = +3.3 V, no output load) .... 124 Figure 5.13 gmTOT versus common mode (simulation results using the TM) (VDD = +3.3 V, no output load) .............................................................................................. 125 Figure 5.14 Step response (VDD = +3.3 V, no output load) ....................................... 125 Figure 5.15 Block diagram of a fully-differential amplifier ...................................... 127 Figure 5.16 Schematic of the fully-differential op-amp............................................. 129 Figure 5.17 Half circuit of the op-amp showing the class-AB output stage .............. 130 Figure 5.18 Common-mode feedback circuit ............................................................ 131 Figure 5.19 Fully-differential op-amp block connected to the I/O pads .................... 132 Figure 5.20 Open-loop frequency response for different load conditions (top) gain magnitude and (bottom) phase ................................................................................... 133 Figure 5.21 Open-loop gain versus temperature (VDD = +3.3 V, no output load) ..... 134 Figure 5.22 UGF versus temperature (VDD = +3.3 V, no output load) ...................... 135 Figure 5.23 PM versus temperature (VDD = +3.3 V, no output load) ........................ 135 Figure 6.1 Programmable feedback capacitances around the first amplification stage (negative Miller compensation) and the second amplification stage (Miller compensation) ............................................................................................................ 141 xix

Figure 6.2 Programmable bandwidth op-amp with negative Miller schematic ......... 143 Figure 6.3 Negative Miller capacitance array (Cadence Virtuoso schematic) ........... 144 Figure 6.4 Direct Miller capacitance array schematic ............................................... 145 Figure 6.5 Analog switch (transmission gate) and resistance versus voltage profile 146 Figure 6.6 Host processor to op-amp digital interface ............................................... 147 Figure 6.7 SPI and ResetN signal timing ................................................................... 148 Figure 6.8 SPI interface communication schematic design schematic ...................... 149 Figure 6.9 Programmable op-amp design schematic schematic ................................ 151 Figure 6.10 Simulated frequency response (VDD = +3.3 V, no output load and TM) 151 Figure 6.11 PM versus compensation capacitive (VDD = +3.3 V, no output load and TM) ............................................................................................................................ 153 Figure 6.12 UGF versus compensation capacitive (VDD = +3.3 V, no output load and TM) ............................................................................................................................ 153 Figure 6.13 GM versus compensation capacitive (VDD = +3.3 V, no output load and TM) ............................................................................................................................ 153 Figure 6.14 Operation of the programmable bandwidth op-amp (VDD = +3.3 V, no output load and TM)................................................................................................... 154 Figure 6.15 Structure of the programmable op-amp .................................................. 155 Figure 6.16 Programmable gain/ bandwidth op-amp design schematic .................... 157 Figure 6.17 Selectable transistors to adjust the tail current ....................................... 158 Figure 6.18 Input stage with tail current source ......................................................... 159 Figure 6.19 Host processor to op-amp digital interface ............................................. 160 Figure 6.20 Basic CMOS analogue switch schematic (left) and operating characteristics (right) .................................................................................................. 161 Figure 6.21 Block diagram of SPI communication .................................................... 162 Figure 6.22 SPI interface communication schematic design ..................................... 162 Figure 6.23 Programmable op-amp design schematic ............................................... 163 Figure 6.24 Frequency response plot (gain magnitude (dB) versus frequency (Hz)) (VDD = +3.3 V, no output load and TM) .................................................................... 165 Figure 6.25 PM versus tail current (VDD = +3.3 V, no output load and TM) ............ 165 Figure 6.26 UGF versus tail current ((VDD = +3.3 V, no output load and TM) ......... 165 Figure 6.27 PM versus output load (CL) (RL = 1 MΩ, with switches and TM) ......... 167

xx

Figure 6.28 Operation of the programmable gain and bandwidth op-amp (VDD = +3.3 V, no output load and TM) ......................................................................................... 168 Figure 7.1 Steps in the rail-to-rail output op-amp design and evaluation process using different compensation techniques ............................................................................. 170 Figure B.1 Structure and operation of the MOSFET ................................................. B-3 Figure B.2 iD versus vDS curve for the nMOS transistor .......................................... B-4 Figure B.3 MOSFET test circuit ................................................................................ B-5 Figure B.4 Transconductance efficiency (gm/ID) chart .............................................. B-7 Figure B.5 gm/ID versus. normalised current (ID/(W/L)) for a nMOS transistor (ratio of W/L=10 µm /0.35 µm) ............................................................................................... B-8 Figure B.6 gm/ID versus. transition frequency (fT) for an nMOS transistor (ratio of W/L=10 µm /0.35 µm) ............................................................................................... B-9 Figure C.1 Structure of the mirror current ................................................................. C-2 Figure C.2 Input common-mode range of a pMOS and nMOS transistor differential pairs with resistive loads ............................................................................................ C-4 Figure C. 3 Common-mode input range of a rail-to-rail input stage [35] .................. C-5 Figure C. 4 gmTOT versus the Vcom for a rail-to-rail complementary input [59] ..... C-6 Figure C.5 gm control by a current switch and current mirror (1:1) [35] ................... C-8 Figure C. 6 gm versus Vcom for the rail-to-rail complementary input stage with gm control and without gm control ................................................................................... C-9 Figure C.7 Circuit diagram of the low-voltage class-AB output stage .................... C-10 Figure C.8 Differential input folded cascode stage of the op-amp .......................... C-11 Figure C.9 Common-mode feedback circuit ............................................................ C-13 Figure C.10 Miller OTA small-signal model without compensation ...................... C-14 Figure C.11 Miller OTA small-signal model with compensation............................ C-18 Figure C.12 Pole/zero locations ............................................................................... C-18 Figure C.13 Bode plot diagram of an amplifier ....................................................... C-19 Figure C.14 Miller OTA amplifier design voltage considerations .......................... C-20 Figure C.15 Simulation of the op-amp to extract AC analysis parameters .............. C-22 Figure D. 1 Layout of the ASIC with LCC package .................................................. D-1 Figure D. 2 Layout of the ASIC ................................................................................. D-2 xxi

Figure D. 3 Layout of the first op-amp (direct Miller only) ...................................... D-3 Figure D. 4 Layout of the second op-amp (direct and negative Miller) .................... D-4 Figure D. 5 Layout of the third op-amp (indirect and negative Miller) ..................... D-5 Figure D. 6 Layout of the rail-to-rail input/output op-amp ........................................ D-6 Figure D. 7 Layout of the fully differential op-amp .................................................. D-7 Figure D. 8 Layout of the programmable bandwidth op-amp.................................... D-8 Figure D. 9 Layout of the programmable gain/bandwidth op-amp ........................... D-9 Figure F. 1 Frequency response analyser……………………………………………F-1 Figure F. 2 PCB view ................................................................................................. F-1 Figure F. 3 Prototype PCB ......................................................................................... F-2 Figure F. 4 View of an ASIC IC ................................................................................ F-2 Figure F. 5 ASIC design............................................................................................. F-2 Figure F. 6 PCB configuration ................................................................................... F-3

xxii

List of Tables

Table 1.1 Comparison of the op-amp versus OTA [11] ................................................ 5 Table 1.2 Comparison of compensation techniques .................................................... 11 Table 2.1 Performance gm/ID in the operation of the MOSFET ................................... 29 Table 2.2 Difference between the gm/ID design approach and the conventional design approach ....................................................................................................................... 30 Table 2.3 Design in different inversion regions ........................................................... 33 Table 3.1 Summary between fully-differential and single op-amp.............................. 53 Table 4.1 Dimensions and voltages for transistor operation ........................................ 74 Table 4.2 DC gain in a different stage and class-AB amplifier (TM).......................... 76 Table 4.3 Op-amp design specification (VDD = +2.5 V) .............................................. 83 Table 4.4 Process variations (first op-amp) (no output load)....................................... 84 Table 4.5 Process variations (second op-amp) (no output load) .................................. 85 Table 4.6 Process variations (third op-amp) (no output load) ..................................... 85 Table 4.7 Summary of the SR (TM and CL=5 pF))..................................................... 92 Table 4.8 Summary of the settling time (TM and CL=5 pF) ....................................... 93 Table 4.9 Summary of the output swing range (TM and no output load) .................... 96 Table 4.10 Summary of op-amp comparison works .................................................... 99 Table 4.11 Summary of op-amp simulations ............................................................... 99 Table 4.12 Characteristics of the frequency response analyser (model SF880) ........ 100 Table 4.13 Summary of the physical prototype open- and closed-loop frequency response of the physical op-amps tested (RTest =1 MΩ with CTest =10 pF, no output load)............................................................................................................................ 103 Table 4.14 Summary of the physical prototype open- and closed-loop frequency response of the physical op-amps tested (RTest =1 MΩ with CTest =10 pF and RL= 1 MΩ CL= 10 pF) .......................................................................................................... 105 Table 4.15 Summary of op-amps when PM= 45° (TM)............................................. 105 Table 4.16 Second op-amp CL= 10 pF and RL=1 MΩ (open-loop) ........................... 107 xxiii

Table 4.17 Third op-amp CL= 10 pF and RL=1 MΩ (open-loop) .............................. 107 Table 4.18 Evaluation the open-loop performance of the op-amps ........................... 110 Table 5.1 Current and voltage of transistors operation mode .................................... 114 Table 5.2 Frequency response with process variations of and without I/O and power supply pads (VDD = +3.3 V, no output load) .............................................................. 118 Table 5.3 Summary of frequency response with process variations and with I/O and power supply pads (VDD = +3.3 V, no output load) ................................................... 119 Table 5.4 Open-loop op-amp characteristic with different load resistance values (simulation results using the typical model) .............................................................. 122 Table 5.5 Open-loop op-amp characteristic with different load capacitance values (simulation results using the TM) .............................................................................. 123 Table 5.6 Comparison with reported rail-to-rail op-amp designs .............................. 126 Table 5.7 Open-loop frequency response (TM) ......................................................... 133 Table 5.8 Frequency response with process variations (VDD = +3.3 V, no output load) .................................................................................................................................... 133 Table 6.1 Negative Miller capacitor values and analogue switch control signals ..... 145 Table 6.2 Direct Miller capacitor values and analogue switch control signals .......... 146 Table 6.3 Comparison of op-amp performance using capacitors only and the capacitors with switches (VDD = +3.3 V, no output load and TM) ............................ 152 Table 6.4 Errors introduced by switches (VDD = +3.3 V, no output load and TM) ... 152 Table 6.5 Switch code and tail current transistor operation (VDD = +3.3 V, no output load and TM) .............................................................................................................. 163 Table 6.6 Op-amp performance using tail current control (operation without switches) (VDD = +3.3 V, no output load and TM) .................................................................... 164 Table 6.7 Op-amp performance using tail current control (operation with switches) (VDD = +3.3 V, no output load and TM) .................................................................... 164 Table 6.8 Op-amp performance using tail current control (operation without switches) (VDD = +3.3 V, no output load) .................................................................................. 166 Table 6.9 Op-amp performance using tail current control (operation switches) (VDD = +3.3 V, no output load) .............................................................................................. 167 Table 7.1 Frequency response for the first topology (TM, no output load) ............... 172 Table 7.2 Frequency response for the op-amp alternative topologies (TM, no output load and VDD = +3.3 V) .............................................................................................. 173 xxiv

Table 7.3 Frequency response for the programmable op-amps topology (TM, no output load and VDD = +3.3 V) .................................................................................. 174 Table C.1 Comparison between the simulation and hand-calculation results ......... C-21 Table C.2 Comparison between the simulation and hand-calculation results ......... C-22

xxv

xxvi

Abbreviations ∂

Derivative



µ

Mobility of change carriers of MOSFET

A(s)

Transfer function

ADC

Analogue (Analog) to Digital Converter

AOL

Open-loop differential gain

Av

Voltage gain

B

Bulk

Bi

Bipolar

BiCMOS

Bipolar Complementary Metal Oxide Semiconductor

C1

Input capacitance

C2

Output capacitance

CBC

Channel-bulk junction capacitance

Cc

Total conventional (direct) Miller capacitors

Cc1, Cc2

Conventional (direct) Miller capacitors

CDB

Drain-bulk junction capacitance

CDEP

Depletion capacitances per unit area

CGC

Gate to channel capacitance.

CGD

Overlap capacitance between gate and drain

CGS

Overlap capacitance between gate and source

CIN

Indirect Miller capacitor

CINT

Interface state capacitances per unit area

CMFB

Common-Mode Feedback Circuit

CMOS

Complementary Metal Oxide Semiconductor

CMRR

Common-Mode Rejection Ratio

CNM

Negative Miller capacitor

Cox

Gate-oxide capacitance per unit area

CVD

Chemical vapur deposition

CSB

Source-bulk junction capacitance

D

Drain

DAC

Digital to Analogue (Analog) Converter

dB

Decibel

fT

Transit (unity gain) frequency xxvii

G

Gate

GaAs

Gallium Arsenide

gds

Output conductance

gm(si)

Transconductance in strong inversion

gm(wi)

Transconductance in weak inversion

gm/ID

Transconductance efficiency

Gm1

Total of output transconductance

Gm2

Total of input transconductance

gmN

Transconductance for nMOS

gmP

Transconductance for pMOS

gmTOT

Total transconductance

GND

Ground (common) connnection

Ibias

Bias current

IC

Integrated Circuit

ICMR

Input Common Mode Range

ID

Drain current

ID(si)

Drain current in strong inversion

ID(wi)

Drain current in weak inversion

ID/(W/L)

Normalized drain current

In

Current of nMOS transistor

IN-

Inverting input

IN+

Non-inverting input

Iout

Output current

Ip

Current of pMOS transistor

IQ

Quiescent current

K

Boltzmann’s constant

Kp

Transconductance parameter

KP

Transconductance parameter

LED

Light-Emitting Diode

mi

Moderate inversion

MOSFET

Metal-Oxide-Semiconductor Field-Effect Transistor

n

Substrate factor

nMOS transistor

n-channel MOSFET

Op-amp

Operational Amplifier xxviii

OTA

Operational Transconductance Amplifier

P1

First pole

P2

Second pole

PLL

Phase-Locked Loop

PM

Phase margin

pMOS transistor

p-channel MOSFET

PSRR

Power-supply rejection-ratio

q

Elementary charge

rds

Output resistance

RGB

Red, green, blue

RL

Load resistor

S

Source

si

Strong inversion

SR

Slew rate

T

Temperature

Tox

Gate oxide thickness

TM

Typical model

UGF

Unity Gain Frequency

v

Small-signal voltage

V

Volt

VCCS

Voltage Controlled Current Source

VCVS

Voltage-Controlled Voltage Source

VCMFB

Common-Mode Feedback Circuit Voltage

VCMRef

Reference voltage of fully-differential op-amp

Vcom

Common mode input voltage range

Vcom, n

Common mode input voltage range for nMOS transistor

Vcom,p

Common mode input voltage range for pMOS transistor

VDD

Positive power supply rail

VDImax

The maximum voltage

VDImin

The minimum voltage

VDS

Drain-source voltage

VDS(sat)

Drain-source saturation voltage.

Veff

Effective gate-source voltage xxix

VGS

Gate-source voltage

VLSI

Very Large-Scale Integration

Vsb

Source-bulk voltage

VSS

Negative power supply rail

Vsup(min)

minimum power supply voltage

VT

Threshold voltage

Vth

Thermal voltage

VTo

Threshold voltage at zero bulk-source voltage.

WP

Worst-case power

WS

Worst-case speed

W/L

Width/length of MOSFET

wi

Weak inversion

z

First zero

Z

Impedance

γ

Bulk-threshold parameter

λ

Channel-length modulation

ϕf

Surface potential.

xxx

Chapter 1 Introduction

1.1 Overview Operational amplifiers (op-amps) are one of the most common circuits in electronic design and are employed in analogue circuits or as analogue sub-circuits within mixedsignal design. For example, the op-amp can operate as an intermediate analogue circuit between the analogue signal and the digital signal. Op-amps are available in different versions of discrete package designs or can be integrated with other digital or analogue circuits to create a specific integrated circuit (IC). A common op-amp configuration is shown in Figure 1.1. The input stage contains a differential input. This stage typically provides most of the voltage gain for the amplifier and establishes the input impedance of the op-amp. The intermediate stage of the op-amp transfers the input stage signal to the output stage amplifier. The output stage provides additional signal amplification and transfers the signal to the output load.

+ VDD Non-inverting input

Input stage

Intermediate stage

Output stage

Output

Inverting input

- VSS

Figure 1.1 Block diagram of a common operational amplifier (op-amp) 1

The output stage extends the output voltage swing and creates the output current capability of the op-amp. It also has a low output resistance. The fabrication of an op-amp can be based on four processes: Bipolar (Bi), Complementary Metal-Oxide-Semiconductor (CMOS), Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS), and Gallium Arsenide (GaAs) [1]. CMOS technology is the dominant process with the high demand for miniaturisation of transistor size and reduction in power supply voltage requirements. As the demand for the CMOS op-amp is increasing in specific markets [2], such as low-power portable battery-operated electronics, the need to improve the op-amp performance at lower power supply voltages is increasingly. An op-amp, which has two inputs and one output, is called a signal-ended op-amp, and an op-amp which has two inputs and two outputs is called a fully-differential op-amp. These configurations offer different performances, but their performances can be improved through circuit optimisation. In the context of design, an op-amp would be based on two or multiple (more than two-stage) stages of amplification where each type of op-amp has its own performance characteristics and applications. However, when an op-amp is used in a feedback configuration, there are major drawbacks in performance related to stability and frequency response. To achieve stable op-amp operation, the designer can add capacitors between specific nodes in the circuit which will purposely reduce the open-loop gain magnitude at higher signal frequencies. This technique, known as compensation, is usually applied by bypassing one of the internal op-amp gain stages with a high-pass filter. Direct (conventional) and indirect Miller compensation are the compensation techniques typically used in a two-stage opamp. Additionally, there are other op-amp designs which require [3, 4] the insertion of more than two gain stages. With a decrease in the size of IC geometries, op-amps with multiple gain stages are known to achieve sufficiently high open-loop gain and stability. This thesis is concerned with compensation techniques for op-amps which enable an improvement in stability and frequency response. It also investigates novel approaches to accomplish compensation by combining negative Miller compensation with direct and indirect Miller compensation. The standard Miller compensation is used for improving stability by reducing the open-loop gain magnitude at high frequency. By adding negative Miller compensation, the unity gain frequency will be extended and also provides an additional margin of stability. This methodology allows an evaluation 2

of the new techniques against standard techniques of compensation. The trend for lowvoltage and low-power applications demands different op-amp architectures where a high accuracy design, high open loop gain, stability, and high-frequency response opamp designs are necessary. In addition, this thesis focuses on low-voltage and lowpower by using the gm/ID approach, which is proposed in [5]. The gm/ID approach is used for designing circuit use the Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) in deep sub-micron process. 1.2 Operational transconductance amplifier and operational amplifier The Operational Transconductance Amplifier (OTA) is a most straightforward version of an amplifier and converts an input voltage into an output current. It is also considered as an example of a Voltage-Controlled Current Source (VCCS). The representation of an OTA is given in Figure 1.2 (a). V+

V+

IN-

iout

-

IN+

IN-

-

OUT

OUT

IN+

+ vin- vin+

vin-

+ vout

vin+

V-

V-

(b) Op-amp

(a) OTA

Figure 1.2 Block diagram of an amplifier The inputs are shown as IN- and IN+, and the output is represented by the output current in Figure 1.2 (a). An OTA is a single stage of amplification. Moreover, it is like an opamp in the sense that it has a high impedance differential input stage. The op-amp is considered as an example of a Voltage-Controlled Voltage Source (VCVS). Figure 1.2 (b) represents the primary symbol for an op-amp and the voltage input/voltage output of the op-amp. An op-amp usually has two inputs: the noninverting (IN+) and inverting (IN-) [6], a DC power supply (negative rail (VSS) and positive rail (VDD)), and either one of the voltage outputs. It consists of an OTA stage and, furthermore, a second stage (Figure 1.3). Typically, it contains two or more 3

amplification stages, which consist of transistors, integrated capacitors, and in some designs, integrated resistors.

Figure 1.3 Simple op-amp configuration The op-amp is designed to have specific characteristics, which include a high open-loop differential gain (AOL), a high gain-bandwidth product, a high input impedance, a low output impedance, a low output offset voltage, a high dynamic range, and a high common-mode rejection ratio [7]. Since the voltage gain is high, the differential voltage between the input nodes is usually very small [8]. The op-amp shown in Figure 1.2 identifies the circuits in open-loop without any external feedback components from the signal output to the signal input, an op-amp will have a set of open-loop characteristics. Generally, the op-amp is designed to operate in closed-loop where feedback components, primarily resistors and capacitors, are used to provide either negative (linear operations) or positive (non-linear operations) feedback. The op-amp is a deviation from the usual OTA design. The significant difference between an op-amp and an OTA is that while an op-amp outputs a voltage that is relative to the difference in voltage between its two inputs, the OTA output current is proportional to the difference in voltage between its two inputs [9, 10]. Table 1.1 describes key differences between the op-amp and OTA.

4

Table 1.1 Comparison of the op-amp versus OTA [11] Op-amp

OTA

High input impedance and low output impedance

High input impedance and high output impedance

Modelled as a voltage-controlled voltage source

Modelled as voltage-controlled current source

Used with external feedback for creating circuits. Used as an output buffer. Contains compensation capacitor in its circuitry between the two stages (Miller compensation)

All nodes are at low impedance except for the input and the output nodes

Op-amp becomes unstable with larger load capacitances

Better frequency capabilities than op-amp. As load capacitance increases, the phase margin increases and the OTA is stable

An OTA with output buffer is an op-amp

A single-stage design For most on-chip applications, as loads are capacitive, the design of op-amp is mostly the design of an OTA

1.3 Applications The op-amp is an important circuit that forms the basis of audio amplifiers, buffers, comparators, oscillators, instrumentation amplifiers, filters, and many other analogue circuits. To fully utilise its capabilities, an op-amp is typically used in a negative feedback configuration to provide linear operations. Negative feedback is supplied by elements, such as resistors or capacitors, linked between the op-amp’s output and its inverting input. For non-linear circuit design, such as oscillators and comparators, op-amps are configured in positive feedback by connecting the components between the op-amp’s output and its non-inverting input [8]. There are countless applications of op-amps, most of which are in analogue circuits. These include the differential amplifier, non-inverting amplifier, inverting amplifier, voltage follower (unity buffer amplifier), summing amplifier, instrumentation amplifier, voltage to current converter and current to voltage converter. As mentioned earlier, the analogue op-amp can also be used as an analogue sub-circuit in a mixedsignal IC. In addition, there are other applications such as Digital-to-Analogue Converter (DAC), Analogue-to-Digital Converter (ADC), Phase-Locked Loop (PLL), filters, sensor applications, composite video cable drivers, and micro power active 5

filters. Figure 1.4 presents [12] an example of a Red-Green-Blue Light Emitting Diode (RGB LED) used for op-amp application in an optical fiber (fibre) sensor system. The LED of some optical fiber sensor systems is utilised as the light source. Here, the LED is a semiconductor device that alters an electrical signal into an optical signal. The properties of the semiconductor material produce photons of a specific wavelength to be emitted, an electronic circuit is applied to control the emission of light. The voltage output from the Pulse-Width Modulation (PWM) signal conditioning circuit are directed to the non-inverting input of the op-amp that is performing as a unity voltage gain buffer then that the inverting input node is tied to the Bipolar junction transistor (BJT) emitter before the op-amp output directly. The BJT represents a current amplifier and the op-amp negative feedback connectivity will ensure that the voltage across the resistor (RSENSE) tracks the op-amp non-inverting input voltage.

SPI communications

Serial communications interface

Digital control and timing

Clock Reset

Internal control signals Data registers VDD (LED) PWM signal generator

PWM signal conditioning

+ -

C1

RSENSE

Figure 1.4 RGB LED driver circuit design for an optical fibre sensor system [12]

6

1.4 Design issues 1.4.1 Low-voltage issues Low-voltage ICs are required in portable systems [13]. Designing and operating analogue circuits at low-power supply voltages are challenging tasks. In the past, the circuits typically encountered were designed to work at higher voltage levels (typically 5 V to 15 V or higher) and, therefore, circuit performance limitations due to limited voltage range was not an issue for many designs. However, today, the operation of electronic circuits with low-voltage power supplies [14] is a requirement for electronic systems where size, weight, and power consumption are especially important. For example, in battery-operated portable equipment, a reduction in the battery requirements in terms of size, weight, and energy capacity can provide cost-reduction benefits in equipment production, purchase, and use along with rendering the equipment more portable. This move towards low-voltage operation can be considered from three different perspectives [15]: 1. The increasing use of battery-operated portable systems requires low-power dissipation in order to extend battery life. 2. Reducing feature sizes in modern Very-Large-Scale Integration (VLSI) fabrication processes results in increased electric field that, unless the power supply voltages are reduced, result in reliability problems. 3. Reduced feature sizes in modern VLSI fabrication processes result in a higher density of the electronics that increase the power dissipation per unit area. In analogue circuits, power dissipation is a combination of static biasing of circuits, leakage, and dynamic effects. This thesis considers low-voltage CMOS with circuit operation at 3.3 V or lower power supply. The low-voltage operation is often associated with low-power operation as reducing the operating voltage can also reduce the power consumption of a circuit, but low-voltage does not necessarily indicate low- power. There are different issues to be considered for analogue circuits. As device geometries in CMOS are reduced (device scaling), the benefits include reduced size (IC area), high operating speeds, and reduced power consumption (due to the ability of designs to operate on lower power supply voltage levels). However, this move comes at the cost of introducing device characteristics not seen with larger device geometries. In analogue circuits, utilising 7

reduced geometry and voltage operation accounts for a range of circuit performance limiting issues. For example, reducing device geometries and power supply voltage levels have an enormous impact on the analogue circuit capability and: •

As the device geometries become smaller and circuit densities increase, currents in the circuit may need to be reduced to prevent localised excessive temperature rises due to the power consumption per unit area since this may cause the device to overheat [16] resulting in device damage and failure.



As CMOS device geometries reduce, this creates increased transistor leakage currents [17].



A reduction in circuit signal bandwidth due to low currents [18].



As CMOS technology is moved to the lower sub-micron level, the transistor threshold voltage (VT) remains relatively constant. So, when the power supply voltage is reduced, it causes a reduction in the available voltage range for circuit operation (a reduction in the (VGS –VT) value) [19]. There is a limitation in the dynamic range of signals in the circuit and some circuit structures, such as stacked transistors, which may be possible with a higher power supply voltage operation but not be possible at lower voltage operation.



The need to operate devices in the sub-threshold region of operation means that the conventional design methods, which were previously used, are no longer be valid.



Analogue circuits require the creation of DC bias currents for circuits, such as current mirrors, which are created using transistors. Transistor operation in weak, moderate, or strong inversion regions of operation and the resulting transistor performance differences due to the region of operation would need to be accounted for. The gm/ID technique is now considered as a preferred design methodology for analogue circuits and, therefore, also for controlling transistor dimensions when the different regions of operation are used. For example, operating the transistor in the weak inversion region means that transistor size would be large and the speed would be slow. In such a case, the large dimensions of the transistor will increase the associated transistor capacitances. Transistor capacitance is an enormous issue in the CMOS op-amps design and affects the potential speed of operation of the circuit.

8



The fully-differential design is considered [20] to be more suitable for higher performance with circuit parameters such as Power-Supply Rejection Ratio (PSRR), Common-Mode Rejection Ratio (CMRR), wider signal swing range, and lower signal distortion.



The need to increase dynamic signal range, which regularly requires a rail-torail output voltage range and for op-amps also the input stage, a rail-to-rail common-mode input voltage range is required [21].

In cases where a particular circuit topology cannot be used due to voltage limitation effects, alternative circuit topologies need to be used. Although different topologies for op-amps provide similar functionality, they differ in the performance they provide. For example, the op-amp would consist of two or more gain stages where voltage and current limiting affects the gain of a particular stage within the op-amp. The overall gain of the op-amp can be increased by either cascading additional gain stages or by improving the performance of each stage. 1.4.2 Frequency response issues A high-speed analogue op-amp design requires a fast speed of response to the input signal. The op-amp needs to have a wide bandwidth, high output current, fast settling time, low distortion and a good DC performance, as well as the capability of operating at low supply voltages [22]. Attaining higher bandwidths and low power has to be optimised. There is demand for low-power and, mostly, low-voltage circuits that can operate within the new limitations that created by low-voltage. To account for these limitations, the techniques that are utilised for the frequency compensation of op-amp need reevaluation. For instance, using feedback to an op-amp without concern of its frequency behaviour could cause the op-amp to fall into spontaneous oscillations [23]. Compensation methods aim to avoid oscillation by influencing the frequency response in such a manner that the circuit is stable under any of range of restrictions. In the past, the op-amp designers tried minimising the number of gain stages to keep the frequency compensation as simple as possible. The typical approach to improving the gain of a circuit without reducing the frequency response characteristics is by the incorporation of cascode stages [24]. The drawback of a cascode design is related to the saturation voltage of the transistor, which is required to keep the MOSFET in saturation 9

with sufficient headroom for its operation. Therefore, a CMOS cascode transistor shows higher saturation voltages and its impact on the minimum supply voltage of an op-amp can be a significant issue [25]. Lower power supply voltage, however, reduces quiescent current, which undesirably affects bandwidth. To achieve a high bandwidth, several frequency compensation techniques, such as parallel, Nested Miller compensation [25] and negative Miller compensation can be considered. Miller compensation (direct Miller) technique is usually applied for frequency stabilisation while negative Miller compensation is usually employed to extend the bandwidth and then increase the speed of an op-amp operation. The negative Miller compensation technique is advantageous for achieving bandwidth of an op-amp operation with a considerable stability when compared to a design that uses direct Miller compensation only. The negative Miller compensation technique is presented in this project to extend the op-amp bandwidth and to combine it with another compensation method, for operation at +3.3 V and below. Table 1.2 above shows a summary of basic ideas for the compensation techniques that will be discussed in detail in this thesis. Direct and indirect Miller compensation techniques are the same principle, although, the compensation capacitor connection nodes are different. Negative Miller compensation, however, is based on the same principle as the Miller effect. When the negative Miller compensation combines with direct and indirect Miller compensation, the phase margin (PM) and unity gain frequency (UGF) improves. The disadvantage is that with the inclusion of an additional compensation capacitor, the area of the layout is increased.

10

Table 1.2 Comparison of compensation techniques

11

1.5 Summary of the research This thesis focuses on investigation of the frequency response performance of an opamp design when the op-amp is designed for low-voltage and low-current. In this work: •

When reducing the power supply voltage, this has a negative impact on the UGF as the UGF is reduced when reducing the power supply voltage. In order to enhance the UGF, negative Miller compensation is used.



When reducing the power supply voltage, the transistor no longer operates in strong inversion region and gm/ID design approach for transistor sizing will be utilised.



To increase the UGF and PM, negative Miller is incorporated with direct and indirect Miller compensation.

The aim of this research is the development of an op-amp architecture that focuses on high-speed and low-voltage. This research offers eight contributions: 1. Analogue IC design techniques: Identification of op-amp design structures such as rail-to-rail output op-amp, rail-to-rail input/output op-amp and fullydifferential op-amp. 2. Identification of analogue circuit design and layout design software tools such as LTspice and Cadence Virtuoso. 3. High-speed, low-voltage op-amp design. 4. The gm/ID design approach, which uses a transistor in strong, moderate, and weak inversion regions of operation. 5. Negative Miller capacitance design technique: The research in this thesis is concerned with the investigation of negative Miller, direct Miller and indirect Miller compensation. 6. Process variation analysis (typical, worst case power, worst case speed, and Monte Carlo analysis). 7. Fabrication of op-amp designs using the Austria Mikro Systeme (AMS) 0.35 um CMOS fabrication process accessed via the Europractice scheme. 8. Test and evaluation of a fabricated IC for +3.3 V, +2.5 V and +1.8 V power supply voltage operations. This thesis presents op-amp designs that are internally compensated with combinations of different compensation techniques. Each compensation technique has some key features. For example, Miller compensation is used for creating a margin stability in 12

open-loop configuration in order to attain stability of a closed-loop configuration. Miller compensation is implemented between nodes of the second stage of the op-amp and negative Miller is implemented around the first stage for extending frequency response. In addition, indirect Miller compensation is incorporated with negative Miller compensation to achieve stability and extend frequency response. Additionally, these techniques of compensation are used with a rail-to-rail output, two-stage CMOS opamp, a rail-to-rail input/output two-stage CMOS op-amp and, finally, with a fullydifferential op-amp. The power supply uses single rail operated were considered +3.3 V, +2.5 V, and +1.8 V, and the size of the transistors was based on gm/ID approach since it is suitable for low-voltage analogue circuit design. 1.6 Thesis outline This thesis provides a comprehensive review of op-amp design and evaluation by describing the op-amp construction that also includes compensation techniques as part of the op-amp design. Cadence Virtuoso software was used for circuit and layout design. The Cadence Spectre circuit simulator was used for analogue circuit simulation. In addition, all simulation results were exported from Cadence Spectre to MATLAB for analysis purposes. The main body of the thesis is divided into seven chapters: •

Chapter 1

Introduction.



Chapter 2

Design methodologies.



Chapter 3

CMOS op-amp structures.



Chapter 4

Rail-to-rail output CMOS op-amp design.



Chapter 5

Op-amp alternative topologies.



Chapter 6

Digital programmable op-amp design.



Chapter 7

Conclusions.

Chapter 1: This chapter provides the main ideas for op-amp design and identifies the low-voltage and low power as well as frequency response issues. In addition, provides an outline of the research. Chapter 2: The chapter begins with an analysis of CMOS transistor operating regions. It details the small-signal model and large-signal model and identifies related 13

parameters. Secondly, it offers an overview of the methodology of gm/ID design technique in strong, moderate, and weak inversion regions of operation. Chapter 3: This chapter shows the architecture of a conventional two-stage op-amp and reviews different designs as single-ended output, rail-to-rail input/output op-amp, and fully-differential op-amp. Secondly, the feedback system is introduced and demonstrates the benefits of using negative feedback. Finally, in this chapter, the compensation techniques are introduced. The focus of the discussion will be on the conventional (direct) Miller compensation, cascode (indirect) Miller compensation, and negative Miller compensation. Chapter 4: In this chapter, three different op-amps are proposed: the first circuit is an op-amp using only direct Miller compensation, which is investigated and analysed, the second circuit is the same as first circuit op-amp, except that it also has negative Miller compensation, and the third circuit is similar to the second circuit but indirect Miller compensation replaces direct Miller. In this chapter, the second and third op-amp will have fabricated using AMS 0.35 µm CMOS process, the prototype physical test results will be compared to simulation results. Chapter 5: This chapter illustrates a rail-to-rail input/output op-amp design topology, which uses negative Miller compensation and direct Miller compensation for extending the frequency response and stability. The design is based on constant-gm to control input common mode variations. The fully-differential op-amp topology is presented using negative Miller and indirect Miller compensation. This chapter shows the commonmode feedback circuit and uses AC, DC, and transient analysis for verifying the opamp’s stability. The fully-differential op-amp design is simulated with the typical process model, worst-case power and worst-case speed under different temperature conditions Chapter 6: Investigations of programmable op-amps are presented in this chapter. Initially, it shows programmable negative Miller and Miller compensations for controlling bandwidth frequency and stability. Secondly, in this chapter, the programmable gain/bandwidth op-amp design basis at tail current presents. Chapter 7: This chapter presented conclusions to the study and identifies future research directions.

14

Chapter 2 Design methodologies

2.1 Introduction Transistors and diodes are utilised in electronic circuit design. Moreover, these components are supported with capacitors and resistors to produce electronic circuits. These circuits are identified as discrete circuits as each of their components can be distinguished in a circuit [26]. There is also a form of manufacturing electronic circuits on semiconductor wafers. They are integrated into the semiconductor wafer and the circuit is usually referred to as an Integrated Circuit (IC). The IC is also commonly defined as a chip or microchip. Consequently, computerised circuit simulation tools support the IC design and the manufacturing of Application-Specific Integrated Circuits (ASICs). The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a key element of an integrated circuit, as thousands and millions of these transistors can be manufactured in one a single IC die. The MOSFET’s general operation, as well as small- and large-signal models, will be considered in section 2.2. Section 2.3 discusses the gm/ID design approach as the second methodology that is used in MOSFET circuit design. Section 2.3 will describe the relationship between the temperature and gm/ID in different inversion regions. Finally, section 2.4 will present an example of a MOSFET and details of CMOS technology. 2.2 Metal oxide semiconductor field effect transistor The MOSFET is a semiconductor device. The structure of a MOSFET consists of four terminals: drain (D), source (S), gate (G), and bulk (B) (or substrate). In addition, the insulating layer is usually a silicon dioxide layer located between the gate and main substrate. It is an insulated gate whose voltage controls the conductivity between the source and drain. The MOSFET is formed as one of two types: a pMOS type and a 15

nMOS type (Figure 2.1), that differ in the polarity of the carriers responsible for transistor current flow between the drain and source connections (holes in the pMOS transistor and electrons in the nMOS transistor).

Figure 2.1 Symbols for the MOSFET with voltages and direction of currents Figure 2.2 shows a fundamental nMOS transistor view of the principal structure of a transistor that is designed on a substrate (p-doped silicon) of moderate doping level. The source and drain terminals are made of two isolated regions of heavy doped diffusion (n+ doped silicon) and these regions are connected, through metalisation, to the outer conductors. The pMOS transistor, has a complementary structure with an ndoped silicon bulk and p+ doped drain and source regions. The region between the two diffused islands beneath the oxide layer is called the channel. The channel offers a path for the majority carriers (electrons, for example, in the n-channel device) to flow from the source to the drain [27]. Meanwhile, the drain and source dopants are opposite to the body (substrate) and create p-n junction diodes that are reverse or zero biased in normal operation.

16

Figure 2.2 Cross section of the MOSFET 2.2.1 Large-signal model The large-signal model is utilised to define non-linear devices (e.g., the MOSFET) in expressing the fundamental non-linear equations and curves. The equations and curves that explain the large-signal operation are called I-V (current-voltage) characteristics (Appendix B.1). The current in an nMOS transistor flows from the drain to the source, whilst in the pMOS transistor, the current flows from the source to the drain. Figure 2.3 identifies the voltages and currents for both nMOS and pMOS transistors.

Figure 2.3 Voltage and current description for the MOSFET

17

The threshold voltage (VT) of a nMOS transistor identifies the minimum amount of the gate-to-source voltage (vGS) required to produce surface inversion in order to establish the conducting channel between the source and the drain. The MOSFET operation is that of a voltage-controlled device and the important voltages are: gate-source voltage (vGS), drain-source voltage (vDS) voltage, and threshold voltage (VT). The minority carriers (electrons in case of a nMOS transistor and holes in case of a pMOS transistor) are obtained at the surface to achieve the relationship between the drain current with terminal voltages of the MOSFET. 2.2.2 Small-signal model A small-signal model is a linearization of the equations at the quiescent point of the MOSFET device operation [28]. The concept of a small-signal model has an equivalent circuit that relates the incremental variations in iD, vDS, and vGS. The variations are small and the small-signal equivalent circuit has linear elements only (e.g., capacitors, resistors, controlled sources). The MOSFET must have different models depending on which region of operation it is working within (cut-off, linear, or saturation). Figure 2.4 has a DC bias current with Vgs and vDS, if (vGS > VT) and VDS > (vGS – VT), the transistor operates in the saturation region. A small-signal input applied in series with the DC bias Vgs produces a small variation. The total input voltage (vGS = VGS + vgs) and the total current (iD = ID + id) variations have a small amplitude and are hence called small-signal. The model shown in Figure 2.5 is often suitable and valid, for both nMOS and pMOS transistors as well as the performances that is related to the small signal are presented in Appendix B.2.

Figure 2.4 Test circuit for a nMOS transistor with DC and AC operation 18

Figure 2.5 Complete small-signal model for MOSFET (saturation region) 2.2.3 MOSFET capacitances The MOSFET structure comprises four terminals (gate, source, drain, and bulk). The source and drain regions create a depletion region between the bulk and the gate creates a capacitance with the drain, source and bulk. These types of capacitances are called parasitic capacitances. Parasitic capacitances influence the speed of operation of the MOSFET device at higher frequencies. The main parasitic capacitance of concern is CGD, presented between the input and output nodes (are shown in Figure 2.6). This is called the Miller capacitor, which will be introduced in chapter 3. Constructed on the physical configuration of the MOSFET, its parasitic capacitances can be categorised into two main groups as indicated in [29]: 1. Oxide capacitance (indicated by Cox), which originates from three capacitances: •

An overlap capacitance between gate and source CGS.



A gate to channel capacitance CGC.



An overlap capacitance between gate and drain CGD.

2. Junction capacitance, which originates from three capacitances: •

The channel-bulk junction capacitance CBC.



The source-bulk junction capacitance CSB.



The drain-bulk junction capacitance CDB.

According to [30], the parasitic capacitances CGS, CGD, and CGB depend on bias conditions (they are voltage-dependent). In addition, the capacitances would have a fixed value at the DC bias point, but then alter during active operation. Assuming that a MOSFET transistor has an effective width (W) and length (L) of the channel, a MOSFET can function in different operation regions: 19



In the cut-off region, the channel is not formed, thus, its capacitive effect can be modelled as: CGS = 0, CGD = 0 and CGB = WL Cox



(2.1)

In the linear region, the channel is assumed to be identical from the source to the drain. So, the gate-channel capacitance will be: CGS = CGD =



1 WL Cox → CGB = 0 2

(2.2)

In the saturation region, the channel has a narrowed shape, and it is pinched off at the drain end. Therefore, the channel will not be identical, and the gatechannel capacitance will be: CGS =

2 WL Cox → CGD = and CGB = 0 3

(2.3)

Figure 2.6 MOSFET parasitic capacitances 2.3 Transconductance efficiency design for all inversion regions Generally, MOSFET design depends on the effective voltage (veff = (vgs - VT)) to achieve the desired drain current and it typically operates [31] in the saturation region (strong inversion). As the channel length continues to decrease, MOSFET the models and circuit simulators are altered to allow adequate accuracy for design. In many cases, this set of conditions leads to correct operation description in saturation, but in the weak or moderate inversion region the accompanying electrical behaviour differs significantly from that in the strong inversion region. In designing analogue MOSFET circuits, an understanding of operation outside the strong inversion region is 20

necessary. Moreover, biasing simple amplifier stages near the weak or moderate inversion region can be used to advantage. There are some advantages of the subthreshold region of operation, which are listed as follows [32]: •

Possibilities of achieving higher gain [33].



Low power consumption.



Reduced distortion and improved linearity than saturation region operation [34].

The main difficulty with the subthreshold region of operation is the decrease in the circuit bandwidth that results in a limited frequency range of operation. Adjusting the device structure (dimensions) can help to decrease the intrinsic gate capacitance (CGS and CGD) for improved frequency of operation. When designing a CMOS op-amp using available transistor models, there can be a substantial difference between the hand calculation results using simple first-order models, and simulation results using more complex models (e.g. BSIM3 transistor simulation models that are available for a fabrication process). This would be due to both the complexities of the models used and the accuracy of the models, considering the boundaries of operation at which the models are designed to operate within. In a conventional op-amp design approach, the transistors are supposed to work in the saturation region and in strong inversion where a high gate-source voltage is required. At low-voltage operation, that is appropriate also for low-power design, the transistor gate-source voltage is lower and the transistor may operate in moderate or weak inversion. The transconductance-DC drain current ratio (gm/ID) design approach provides separate analytical formulas for strong, moderate, and weak inversion, to generate simple equations that are useable in all channel inversion conditions. 2.3.1 Inversion regions It is important to establish a distinction between the regions of operation (cut-off, linear, and saturation) and the corresponding inversion regions (weak, moderate, and strong). The inversion regions required to operate in the saturation region. Therefore, the inversion level change form weak, moderate to strong inversion as VGS is increased in the saturation region (Figure 2.7 is shows simulation results using Figure B.3 using AMS 0.35 CMOS process). The range of an inversion model (and the corresponding ranges of VGS values) is divided into three regions, in each of which the transistor will later be seen to exhibit distinct properties. The three regions are called weak (wi), 21

moderate (mi), and strong inversion (si). These regions can be identified in detail by applying the ratio of transconductance over drain current (gm/ID) versus the normalised current or the effective voltage (overdrive voltage). The ratio of transconductance over drain current is also called transconductance efficiency.

Figure 2.7 Properties of MOSFET operation (W=10 µm and L=0.35 µm)

Figure 2.8 Drain current versus gate-source voltage 22

2.3.1.1 Strong inversion The strong inversion region is, possibly, the most typically used among the three inversion regions [34] in conventional amplifier circuits. A MOS transistor operates in the strong inversion region when VGS is larger than the threshold voltage VT. Furthermore, the transistor begins to saturate when vDS ≥ vGS-vT. The drain-source voltage at which a transistor begins to saturate is called the saturation voltage (VDSAT). In this case the, the relationship between the drain current (ID) and the gate-source voltage (Vgs) can be expressed using [35, 36]: ID(si) =

1W μ . C (V − VT )2 (1 + λVDS ) 2 L n ox GS

(2.4)

Where, •

W is the gate width.



L is the gate length.



µ is the mobility of the charge carriers of MOS transistor.



Cox is gate oxide capacitance per unit area.



Λ is channel length modulation

The complete VGS description of a MOS transistor can be done in two parts, the threshold voltage (VT) and the effective voltage (Veff), which drives the transistor VGS = Veff + VT. The threshold voltage can be defined by: VT = VTo + γ (√2ϕf + VSB − √2ϕf )

(2.5)

Where, •

VT0 is the threshold voltage at zero bulk-source voltage.



γ is the bulk-threshold parameter.



ϕf is the surface potential.



VSB is the source-bulk voltage.

The effective gate-source voltage is determined by rewriting equation (2.4): Veff

2 L =√ I μn . Cox W D(si)

(2.6)

The effective gate-source voltage of a MOS transistor is obtained by the square-law model. The strong inversion region is accessed when the drain current is obtainable with

23

a higher gate-source voltage [34], and so, devices that operate in this region are required to supply a high driving current, as shown in Figure 2.7. The transconductance is a small-signal parameter of a MOS transistor. Transconductance is the slope of the plot between the drain current and the gate-source voltage as described in section (B.2.1), and it is given by: gm =

∂iD ∂vgs

(2.7)

Yielding: g m = μn Cox

W V I L eff D

(2.8)

Moreover, by substitution, it can be deduced that: gm

W 2ID = √2 μn Cox ID = L Veff

(2.9)

The above equations mean that Veff determines gm. However, to increases gm, it may not be possible to increase Veff, since this would require a higher supply voltage. Therefore, it is better to increase gm by increasing both W/L and ID. 2.3.1.2 Weak inversion In the actual MOSFET, the drain current is not zero for all values of vGS below VT (Figure 2.7) and this current is referred to as sub-threshold current. The subthreshold region exists for values of vGS less than VT when a positive drain current flows. The drain current continues to increase as vGS increases up to positive value of a few millivolts. The current through the channel is formed by electrons or holes being carried, primarily, by diffusion for slightly negative values of Veff up to a positive value of about 20 mV [6]. This region that includes subthreshold conduction is referred to as the weak inversion region. A MOS transistor operates in weak inversion when VGS < VT. In this mode, the transistor saturates when vDS > 3 to 4 Vth. Vth is the thermal voltage (Vth = kT/q), which is about 25 mV at room temperature. Generally, the saturation voltage of a MOS transistor operating in this mode is lower than that of a device running in strong inversion. The current ID in saturation is described as follows:

24

ID(wi) = Io

(V −V ) ( GS T ) e n Vth

(2.10)

Where n is subthreshold slope factor of a long-channel, and Io is the technology current given by: W Io = 2nμn Cox ( ) (Vth )2 L

(2.11)

These equations can be re-arranged as: W ((VGS −VT )) ID(wi) = 2nμn Cox (Vth )2 ( ) e n Vth L

(2.12)

Assuming that the value of the VGS is equal to zero, the drain current is: ID(wi) = 2nμn Cox (Vth

)2

−VT W (nV ) ( ) e th L

(2.13)

This equation presents the exponential behaviour (as Figure 2.8) of the weak inversion [29]. However, the inverse slope is larger than kT/q, where n is described as the subthreshold slope factor, and as ID is less than Io, Veff has a negative value. Therefore, VGS = VT + Veff for a MOS transistor operating in weak inversion, is smaller than the VGS of a device operating in strong inversion. Thus, a device biased in deep the weak inversion region is more suitable for low-voltage operation. The transconductance in weak inversion is defined as: g m(wi) =

∂ID ID = ∂VGS nVth

(2.14)

The substrate factor (n), conceptually, denotes a loss of connection efficiency between the gate and channel caused by the substrate (body) that works as a back gate. In a weak inversion, n is related to the capacitive voltage division between the gate voltage and silicon surface potential resulting from the gate-oxide, depletion, and interface state capacitances [37]. However, in weak inversion, n is expressed by: n(wi) =

Cox + CDEP + CINT CDEP CINT =1+ + Cox Cox Cox

(2.15)

Where, •

Cox is gate oxide capacitance per unit area: Oxide layer underneath the gate terminal.



CDEP is the depletion capacitances per unit area: The area is between sourcesubstrate and drain-substrate. 25



CINT is interface state capacitances per unit area: Interface state is produced by positive or negative charges at the silicon/silicon dioxide interface or by mobile ionic charges and fixed charges stuck within the oxide and itself, that are often generated through the fabrication process [38].

To achieve a substantial gm, the drain current must increase. However, increasing this current may push the device into the strong inversion mode, and this must be avoided to maintain low-voltage operation by adjusting the W/L. However, the increased device geometries lead to enhanced device parasitic capacitances, thus affecting the highfrequency performance. 2.3.1.3 Moderate inversion As defined above, the MOSFET has two different physical regions of operation: weak inversion and strong inversion. In the weak inversion region, the diffusion current controls the drain current is proportional to the exponential of effective gate-source voltage (see equation (2.10)). In strong inversion region, drift current controls the drain current and is proportional to the square of the effective gate-source voltage (see equation (2.4)). Velocity saturation, small-geometry, and high-field effects reduce drain current below the strong-inversion and square-law value, especially for short-channel devices operating at high effective gate-source voltages [37]. Between weak and strong inversion, there is a transition region known as moderate inversion [39] where both diffusion and drift current are significant. the moderate inversion offers higher gm/ID and lower drain-source saturation voltage compared to strong inversion and when combined with smaller gate area and hence capacitances, provides higher bandwidth compared to weak inversion. 2.3.2 gm/ID design and inversion region The transconductance efficiency (gm/ID) describes the ratio of transconductance (gm) to drain current (ID). Figure 2.9 shows a logarthmic plot of gm/ID versus drain current, where transconductance efficiency, which was maximum in weak inversion, starts reducing in moderate inversion, and falling as the inverse square root of the drain current in strong inversion. The moderate inversion is the transition region between the weak and strong inversion. The centre of the moderate inversion region is the

26

intersection of the weak and strong inversion asymptotes [40, 41]. The three regions are: •

Strong inversion region: When VGS is higher than VT and VDS (sat) < VDS, the inversion channel is created. Hereby, a linear function uses the ID-VGS MOS equation: ID(si) =

1 W μn Cox (VGS − VT )2 (1 + λVDS ) 2 L

(2.16)

The transconductance is the derivative of ID on Vgs. The approximation: is: W 2 ID g m(si) = μn Cox ( ) (VGS − VT ) = (VGS − VT ) L

(2.17)

Figure 2.9 gm/ID versus ID for an nMOS transistor (ratio of W/L=10 µm /0.35 µm) •

Weak inversion region: When the drain-source current is non-zero, the gatesource voltage is smaller than the threshold voltage and it is also called the subthreshold region. Therefore, the drain current is dominated by carrier diffusion and the relationship between the drain-source current and gate-source voltage is exponential [5]: W ((VGS −VT )) ID(wi) = 2nμn Cox (Vth )2 ( ) e nVth L

(2.18)

Generally, [42] the subthreshold current rises considerably with temperature and is typically the main source of power consumption in analogue circuits. The

27

transconductance of the MOSFET in the subthreshold region is defined by obtaining the derivative of iD (wi) on VGS for equation (2.18) : g m(wi) = •

2ID nVth

(2.19)

Moderate inversion region: When the transfer between strong and weak inversion is not well defined, it is referred to as moderate inversion, which is set between weak upper inversion and strong lower inversion.

2.3.3 Conventional and gm/ID design techniques The conventional analogue design approach when used the MOSFET is based on the strong inversion region only and uses MOSFET I-V characteristic curves [43]. Firstly, the drain current (ID) versus gate-source voltage (VGS) is plotted on a logarithmic scale followed by the drain current (ID) versus drain-source voltage (VDS). In these curves, the drain current is not zero and has exponential relations with VGS and VDS. However, the conventional analogue design approach ignores a wide area of transistor operation, such as the weak and moderate inversion regions [44]. The drain current of the MOSFET depends on the gate voltage overdrive (Veff), channel-length modulation (λ), transconductance parameter (KP), the threshold voltage (VT), and µ.Cox (where μ is the carrier mobility and Cox is the oxide capacitance per unit area). In the modern MOSFET simulation models, however, the model parameters such as µ.Cox, KP, λ or any parameter that is familiar cannot be found since the equations used in the model are complicated for investigation and analysis. Furthermore, there are many other differences between the conventional analogue design and modern analogue design approach (Table 2.1). gm/ID is defined as the derivative of the drain current on the gate voltage and the results divided by the drain current are given by: ∂iD g m ∂vGS⁄ = ID ID

(2.20)

Here, ID governs the power dissipation and gm denotes speed. Voltage gain and intrinsic capacitances limit output impedance and speed [11]. gm is associated with performance at the transitions from weak to moderate, and strong inversion (Figure 2.9). The current is affected by the ascpect ratio (W/L), device type (nMOS or pMOS), and fabrication processes features. These transitions are associated 28

with the design of the device. As a result, each inversion region has different properties. They are shown as a summary of high and low gm/ID in Table 2.1. •

Design in weak inversion: Weak inversion has a higher gm/ID value and gm/ID is limited by q/nKT (where n is the slope factor) with lower current. Moreover, a lower VGS and a large geometry device imply lower gm [44].



Design in strong inversion: The strong inversion exhibits lower gm/ID value and the gm/ID is limited by (2/Vov) with higher current. In addition, a higher Vgs and a small geometry device imply higher gm and thus higher transit (unity gain) frequency (fT).



Design in moderate inversion: There is no specific expression in the moderate inversion region, but it does appear as a promising region for low power amplifier design as it provides a compromise between the weak and strong inversion region such as improved speed and power consumption.

Table 2.1 Performance gm/ID in the operation of the MOSFET Transconductance efficiency Low gm/ID

High gm/ID

Strong inversion

Weak inversion

Poor power efficiency

Good power efficiency

Low output voltage range

High output voltage range

High transit (unity gain) frequency (fT)

Low transit (unity gain) frequency (fT)

Low intrinsic gain

High intrinsic gain

Small transistor size

Large transistor size

29

Table 2.2 Difference between the gm/ID design approach and the conventional design approach gm/ID design approach

Conventional design approach using VT, KP and 

Valid in all operating regions (weak, moderate Valid only in a strong inversion of the and strong) of the MOSFET.

MOSFET.

Not necessary to create the condition VGS > VT.

Valid only if VGS > VT.

There are different curves for gm/ID depending on Uses the ID versus VGS and ID versus VDS the inversion region.

curves.

Used for circuits operating on lower power Used for circuits operating a higher power supply voltage levels

supply voltage levels.

A simplified technique is suitable for new Not suitable for new evolving fabrication evolving fabrication process technologies.

process technologies.

A fast design technique for the equations that Is appropriate for a fast design technique. model the electrical behaviour of circuit that can It does not have compact electrical be signified by gm/ID.

models capable of simple current and voltage relationships.

VGS should be kept as small as possible and If (VGS –VT) is small, a large geometry transistor gate-source capacitance should be as device is required and thus a large small as possible.

transistor gate-source capacitance.

The gm/ID ratio is used directly as a central The gm/ID ratio is not directly used to design

variable

to

determine

circuit determine the performance of the circuit.

performance. Links the variables such as gm, fT and ID to Parameters such as µCox, VT and VDS(SAT) specifications such as bandwidth, power and are

considered

as

poorly

defined

Veff.

parameters.

Uses charts and simple equations.

Depends on complex equations and sometimes based on assumptions such as ignoring the effect of channel-length modulation (λ).

The gm/ID ratio associates small-signal and a Small and large-signal models are not large-signal (gm → ID) parameters.

associated.

30

2.3.4 gm/ID design flow Figure 2.10 presents the process flowchart for using the gm/ID design approach. The flowchart starts with selecting the MOSFET model (here the BISM 3V3 model considered) and determines the gain or transient frequency. If the new Av or fT is not acceptable, it is possible to redesign by choosing a new gm/ID from charts that are presented in Appendix B.3 and follow the same process or modify Av (or fT) in order to get the right value. A concise design technique of the gm/ID method is summarised as follows:

Figure 2.10 Flowchart of the gm/ID design process 1. Set up circuit and determine limitations such as fT or DC gain Av and extract the transconductance (gm°). 2. Determine gate length and width (L, W,), respectively. 3. Run circuit (DC sweep), then create two plots, gm/ID versus drain current (or gm/ID versus gate-drain voltage) and gm/ID versus normalised drain current.

31

4. Set a suitable (strong, moderate, weak) inversion region and pick gm/ID ((gm/ID)*) form the chart in step 3. 5. Using the simple equation to extract the new the drain current (ID°) gm° ID ° = ( ) (g m ⁄ID )∗

(2.21)

6. According to the (gm/ID)*, pick the normalised drain current ( (ID/W)*) from the chart in step 3. 7. Use the simple equation to extract the new, normalised drain current ( (ID/W)°). Moreover, find the width of the transistor (consider W°) by using: ID ° W° = ( ) (ID ⁄W)∗

(2.22)

8. Using W° as the new gate width, repeat the steps to get a fixed value of W for the same bias condition. According to [45], to get the exact transistor size for given bias condition in the simulator, design a common-source amplifier, in which VGS and VDS are equal to VGS * and actual VDS in circuit, respectively. 2.3.5 The gm/ID sizing approach The common source amplifier considered for investigation and analysis is shown in Figure 2.11. The length of the transistor M1 is kept as small as possible and it uses an AMS (Austria Mikro System) 0.35 µm CMOS process. The design specifications are: load capacitance CL= 10 pf, unity gain frequency fT = 1 MHz, resistance RD = 10 kΩ, the transistor gate length is 0.35 µm, and the threshold voltage is 0.7 V for an nMOS transistor.

Figure 2.11 Common source amplifier 32

Design process: 1. Determine gm, fT = gm/(2π.CL) → gm° = 62.83 µS. 2. Determine pre- length/width (W=10 µm, L=0.35 µm). 3. Select a transistor operating region and calculate ID by picking (gm/ID)* from the chart in Figure B.4. 4. In accordance with (gm/ID)*, select drain current ID* and find the new current from equation (2.21) and refer to it as ID°. 5. Considering (gm/ID) *, select normalised current (ID/W) * from Figure B.5. 6. Considering (ID/W) *, find the new W° from equation (2.22). The basic circuit is shown in Figure 2.11 and it operates in strong inversion with 0.35 µm and 10 µm gate length and gate width respectively. This process shows the difference between the strong, moderate, and weak inversion to obtain unity gain frequency fT = 10 kHz and the voltage gain Av is 6.5 V/V. To summarise the process, it shows the difference between the drain current and the gate width for the same minimum length in the three inversion regions. Table 2.3 presents four different inversion regions. The weak inversion is at gm/ID = 30.6 V-1, the drain current (ID°) is small and is about 2.053 µA, while the width of the transistor is much larger being about 705.50 µm, moderate inversion between at gm/ID = 29 V-1 and 19 V-1, the gm/ID is 10 V1

at strong inversion, the ID° is 6.159 µA, and width is 1.921 µm. Table 2.3 Design in different inversion regions

L=0.35 µm

gm° = 62.83 µs (gm/ID)* (v-1) ID* (µA) (ID/W)* ID° (µA) W° (µm) Vgs (V)

Weak inversion 30.6 2.91e-03 2.91e-04 2.0532 705.50 0.288

Inversion region Moderate Moderate Inversion (1) Inversion (2) 29 17 58.2e-3 14.6 5.82e-3 1.46 2.167 3.6958 372.25 2.5314 0.388 0.623

Strong inversion 10.2 38 3.80 6.159 1.621 0.712

When the transistor operates in strong to moderate inversion (Vgs > VT), the traditional condition (Vds (sat) = Vgs - VT) is used and Vds(sat) is a positive voltage, so the transistors are in strong to moderate inversion in the saturation region. Moreover, if (Vgs < VT), then the Vds(sat) is a negative voltage when (Vds (sat) = Vgs - VT) and the condition is not 33

valid at weak inversion to check if the transistor is operated into saturation region. Therefore, the Vds must be higher than 4 to 3 Vth to avoid the linear (triode) region.

VGS

VDS

(BSIM3V3)

M11 (nMOS)

Width (µm)

34.5

M12 (nMOS) 22

Length (µm)

0.35

0.35

gm/ID (V-1)

30.12

28.78

ID (nA)

34.5

79.99

1.209

0.07

Vgs (mV)

440.8

389.7

VT (mV)

568.2

569

Vds (sat) (mV)

-35.91

-36.16

Vds (V)

Figure 2.12 Saturation region in weak inversion Figure 2.12 shows MOSFET circuit with certain conditions that are used in Chapter 4. The transistor M11 has high gm/ID that is extracted from the circuit to make sure the transistor is operating at the right point in the saturation region. Figure 2.13 shows the I-V characteristics and the position of the transistor in the deep saturation region. In Figure 2.14, the transistor M12 is operated in weak inversion on the edge of the saturation region. However, the condition Vds > Vds(sat) is still produced in weak inversion.

34

Figure 2.13 IV characteristics of an nMOS transistor (M11) operating in the weak inversion region

Figure 2.14 IV characteristics of an nMOS transistor (M12) operating in the weak inversion region 2.3 Temperature effects and the gm/ID design technique The variations in circuit operating temperature influences many of the MOSFET characteristics and have to be considered in the design creation. Any change in temperature will result in a change in specific MOSFET parameters. For example, an 35

increase in temperature will result in an increase in the thermal voltage and a marginal decrease in the band-gap energy of the semiconductor martial. As the intrinsic carrier concentration within the semiconductor material depends on the value of the bandgap energy, the intrinsic carrier concentration increases with temperature. As the increasing intrinsic carrier concentration increases, the Fermi potential is decreased and increases the thermal voltage [46, 47]. The temperature dependence of the thermal voltage Vth can be given by [46]: Vth =

kT q



k is Boltzmann’s constant.



T is the absolute temperature (in Kelvin (K)).



q is the electronic charge.

(2.23)

In the previous section, the MOSFETs were operated in different inversion regions. Any variation in temperature is effect on the inversion region as each inversion region has different temperature related properties. As the temperature increases, the threshold voltage and mobility decrease. A decrease in mobility then causes a reduction in ID [48]. At the same time, a decrease in the threshold voltage causes an increase in ID. At low VGS (in weak inversion), the changes in Vth dominate and the ID increases with increasing temperature. The MOSFET drain current in weak inversion is proportional to the exponential of the effective gate-source voltage:



W ((VGS −VT )) ID(WI) = 2nμn Cox (Vth )2 ( ) e nVth L n is the substrate factor.



µn is the channel carrier mobility.



Cox is the gate-oxide capacitance per unit area.



W and L are the effective channel width and length.



VGS the gate-source voltage. VT is transistor threshold voltage

(2.24)

Again, ID is given for the MOSFET operating in the saturation region where the drainsource voltage (VDS) exceeds its saturation value (VDS(sat)). The drain current has decreased as the temperature increases due to the reduction in charge carrier mobility [49, 50]. The substrate factor (n) in equation (2.15): n(WI) =

Cox + CDEP + CINT CDEP CINT CDEP = 1+ + ≈1+ Cox Cox Cox Cox 36

(2.25)

Note, CINT is positioned right at the interface or in the oxide and the value of CINT is assumed negligible and is not included in the prediction of n. The interface state capacitance increases as the temperature increases. The transconductance in weak inversion is given by: g m(WI) =

∂𝑖 q KT 2 W −q(Vgs −VT ) q ID = Io ( ) ( ) e( nKT ) = ∂vgs nkT q L nkT

(2.26)

And the transconductance efficiency by: gm q ( ) = ID WI nkT

(2.27)

The transconductance efficiency in the weak inversion reduces with increasing temperature (T) due to a reduction in ID. In addition, the transconductance efficiency, due to the substrate factor (n), is increased as the temperature is increased. Strong inversion appears for MOSFETs operating at sufficiently high Veff where VGS is above the threshold voltage, the channel is strongly inverted and drain drift current dominates. The drain current is defined in equation (B.8) and given by: ID(SI) = μn Cox

2 W Vds sat [(Vgs − VT )Vds sat − ] L 2

(2.28)

And the transconductance (gm) is defined in sub-section B.2.1.

W 2 ID g m(SI) = μn Cox ( ) (Vgs − VT ) = L (Vgs − VT )

(2.29)

gm 2 ( ) = ID SI Vgs − VT

(2.30)

ID depends on charge carrier mobility (that decreases with increasing temperature) and carrier concentration (which is essentially invariant with temperature), and threshold voltage (decrease with temperature) [48]. At VGS levels just above VT, VT variations dominate and ID increases with temperature. Conversely, at significantly higher VGS levels, the mobility term dominates and ID decreases with temperature. gm/ID continues to reduce as the MOSFET inversion (Veff) increases. While increasing temperatures usually lowers the transconductance, voltage gain and bandwidth, increasing 37

temperatures lower VT [48]. This usually favours lower VGS levels since VT usually decreases more compared to the temperature-related increase in Veff. 2.4 CMOS technology 2.4.1 Introduction Complementary metal-oxide-semiconductor (CMOS) is a technology utilised to create integrated circuits (ICs). The both transistors have n-type drains and sources, and the well transistors have p-type drains and sources as shown in Figure 2.15 below. CMOS circuits are used in several kinds of electronic components, such as microprocessors, digital camera image sensors, and batteries [51].

Figure 2.15 CMOS cross-section view of nMOS and pMOS transistors The term "MOS" in CMOS denotes the transistor in a CMOS component, referred to as MOSFET. The "complementary" term of CMOS relats to the two different types of transistor included: n-type (nMOS transistor) and p-type (pMOS transistor). The nMOS transistor have a greater concentration of electrons than holes in the channel. The pMOS semiconductors, on the other hand, have a greater concentration of holes than electrons. These two semiconductor components work together and often form logic gates based on how the circuit is designed. Both nMOS and pMOS devices are fabricated in CMOS technology. The base of these devices needs a substrate material of opposite type of doping for their fabrication [52]. For instance, in n-well CMOS technology, the nMOS transistor is placed directly on the p-substrate, whereas the pMOS transistor is placed in a deep and low doped n-well which acts as the substrate for the pMOS, the opposite of this goes for p-well CMOS technology. 38

2.4.2 AMS 0.35 µm process The Application-Specific Integrated Circuit (ASIC) foundries describe the different capabilities of circuits that can be created using then particular fabriacation process, or processes, and the operating boundaries such as power supply voltage and current density margins for different CMOS technologies to ensure the consistent performance of the IC. Therefore, any ASIC device working at supply voltages and/or current densities more than the maximum limits described by these dependable boundaries can be subject to ASIC device failure. Figure 2.16 presents the cross-section of a shape achieved by the AMS 0.35 µm CMOS process. The structure consists of four metallization layers separated by four dielectric layers of silicon oxide as well as temperature range is between -40°C and 125°C only [53].

Figure 2.16 AMS 0.35 µm CMOS process cross-section [54] The ASIC design in this work was created utilising the AMS 0.35 µm CMOS (n-well) technology due to its low-cost of fabrication along with pMOS and nMOS transistors being available for 3.3 V and 5.0 V use with high current driving capabilities and excellent ESD performance. 2.4.3 Capacitance In an IC, all passive and active elements are fabricated on the same IC area. Capacitors are built on-chip, they are the key element since uses for Miller compensation technique and are most common in op-amp design, analogue filter, converter, and other applications. A capacitor is made with two conductive layers (electrodes) and is

39

insulated with a dielectric layer. The AMS 0.35 µm CMOS process provides five kinds of capacitances: •

Poly 1 to poly 2 (dielectric is thin silicon dioxide or other, e.g. thin sandwich of silicon dioxide, silicon nitride, silicon dioxide).



Poly to the implanted region (high-dose implantation under poly, the dielectric is thin silicon dioxide).



Poly to metal 1 (dielectric is intermediated Chemical Vapur Deposition CVD oxide).



Metal 1 to the diffused active area (dielectric is intermediated CVD oxide).



Metal 1 to metal 2 (dielectric is the intermetal insulator).

2.5 Conclusions This chapter has introduced the structure and behaviour of the MOSFET. The analysis of a MOSFET was established using the small- and large-signal models. The largesignal model comprises non-linear equations and curves while the small-signal is a linear linearization of the equations around a specific operating point. These models are used for creating CMOS analogue and mixed-signal circuits. For example, in an opamp design. This kind of design is called conventional design and is suitable for higher voltage levels that the power supply voltage is 5 V and higher. The transconductance efficiency (gm/ID) was introduced and used as basis for an alternative method of design which was introduced in this chapter. Moreover, the gm/ID is considered as the link between the small-signal and large-signal models. The gm/ID is suitable for low-voltage and low-power circuit design since it is related to the inversion reigns (weak, moderate and strong inversion region). Each inversion region present reliable analytical own performances.

40

Chapter 3 CMOS operational amplifier structures

3.1 Introduction A CMOS operational amplifier (op-amp) structure is discussed in this chapter. The opamp design is identified by two stages of amplification, the first stage being an Operational Transconductance Amplifier (OTA) and the second stage being a class-AB amplifier. The folded cascode and class-AB amplifiers are presented as the key circuits for improving op-amp performance. The folded cascode circuit is incorporated within the first-stage. Moreover, the class-AB amplifier is used as the second stage to achieve a high output signal swing. In addition, in this chapter, the other op-amp designs considered are a rail-to-rail input and output op-amp and a fully-differential op-amp. Additionally, compensation is a part of the op-amp design and is present as an internal feedback component used to improve frequency response and stability. Section 3.2.1 discusses the basic two-stage op-amp design. The first stage is an OTA whilst the second stage is a common-source amplifier. Section 3.2.2 discusses the folded cascode circuit and section 3.2.3 presents a class-AB amplifier. A rail-to-rail input/output op-amp is considered in section 3.2.4, which looks at the complementary input stage technique that is employed for rail-to-rail input performance. Moreover, transconductance (gm) equalisation is used to balance the transconductances of the complementary input stage. A class-AB amplifier is considered in the second stage. Section 3.2.5 reviews a fully-differential amplifier and identifies its design along with common-mode feedback circuit that necessary for correct circuit operation. Section 3.3 introduces the principle of feedback. The feedback system could be positive or negative, the negative feedback providing an advantage that will be introduced.

41

Section 3.4 presents the compensation techniques that are based on Miller effect. These techniques are based on internal feedback applied within the design and are designed direct, indirect, and negative Miller compensation. 3.2 Operational amplifier The op-amp is one of the necessary building blocks of some linear and non-linear circuit designs. The classic configuration contains two input terminals: one is the inverting node (-) and the other is a non-inverting node (+), and an output terminal. The standard symbol of the op-amp is shown in Figure 3.1. It contains the power supply terminals that are required for operation. Positive supply

_

(-) Inputs

(+)

Op-amp

Output

+ Negative supply

Figure 3.1 Operational amplifier (op-amp) circuit symbol The output of an op-amp is sensitive to any changing differential voltage across the input terminals. If the magnitude of differential voltage is more positive on the inverting (-) terminal than on the non-inverting (+) terminal, the output becomes more negative. Conversely, if the magnitude of the differential voltage is more positive on the noninverting (+) terminal than on the inverting (-) terminal, the output voltage will become more positive [55]. An op-amp design has many parameters that should be considered by a designer, such as input common mode range (ICMR), slew ratio (SR), phase margin (PM), unity gain frequency (UGF) and power dissipation. The op-amp performances [56] are listed as following:

42



Open-loop gain: The gain of the op-amp is the ratio of the output signal to the input signal without feedback.



Offset voltage: The dc voltage that must be used between the input terminals to cancel dc offsets within the op-amp.



Input bias current: The difference between the currents into the two input terminals with the output at the specified level.



Common-mode input voltage range: This describes the voltage range where both inputs have to maintain correct operation. When the input common-mode range operates between both power supply rails, VSS and VDD, it is a rail-to-rail input stage.



Maximum output voltage: This identifies how close the output voltage reaches the upper power supply (VDD).



Minimum output voltage: This identifies how close the output voltage reaches the lower power supply (VSS).



Unity gain frequency: This is the frequency when (fT) the gain magnitude has reduced to 0 dB.



Gain bandwidth product: The product of the open-loop voltage gain magnitude and the frequency at which it is measured.



Phase margin: The absolute value of the open-loop phase shift at the frequency where the open-loop amplification first equals 0 dB.



Slew rate: This is the maximum rate of alteration of the output voltage signal at any point in time and has typical units of volts per microsecond



Differential input resistance: This is described as the resistance between the non-inverting and inverting inputs.



Input resistance: This is the resistance between the input terminals with either input grounded and is frequently in the range of many mega-Ohms.



Output resistance: This is the reistsance placed in series with an ideal amplifier output and it is frequently in the 100’s Ohms range at low frequencies and usually increases with frequency.



Common-mode rejection range: This is identified as ratio differential voltage amplification to the common-mode voltage amplification. 43



Power dissipation: The total power dissipated by the op-amp during its operation.



Power supply rejection range: This is a measure of the ratio of power supply voltage change to output voltage change

3.2.1 Two-stage CMOS operational amplifier design The typical block diagram of an op-amp is shown in Figure 3.2 below. It comprises two-stages of amplification, the first stage represents a differential input amplifier and the second stage shows a common source amplifier. Moreover, the simplest OTA contains approximately eight transistors, of which two transistors are nMOS type (M1M2) for the input differential pair block, two are of pMOS type, M3-M4 is for the active load block, and the differential input stage is biased through the current mirror, M5-M6. The second stage is the output stage, thier shows the common-source amplifier associated with M7-M8 transistors. M8 transistor supports the bias current for M7 and also same as an active load. As well as more details are shown in Appendix C.1.

Figure 3.2 Schematic of a simple operational amplifier 3.2.2 Folded cascode amplifier The folded cascode is shown in Figure 3.3. The fundamental concept of cascode is thatit is a two-stage amplifier, M1 is a common-source amplifier, and M2 is a common-gate amplifier Another example of a CMOS amplifier is the folded cascode amplifier. The concept of the folded cascode design is to utilise cascode transistors of types (i.e., nMOS 44

rather than pMOS and vice-versa) opposite from those used in the input stage [42] as shown in Figure 3.3. The objective of using this topology is to reach the simplicity and small size of a single stage amplifier and obtaining high gain [57] as the folded cascode connection provides a high resistance output node. Moreover, the transconductance of the cascode is also nearly equal to the transconductance of the input pair that increases the small-signal gain of the amplifier [37].

Figure 3.3 Concept of a folded cascode Small-signal variations in the drain current of M1 are controlled through M2 in this case because IBIAS is a constant current source. There are two main reasons for using cascode stages [42, 58]: firstly, it has a significant gain for a first stage because and has high impedance at the output, and secondly, it controls the saturation voltage of the input transistor, which suits modern technologies having very short channel length transistors and operated at low power. It also can allow the circuit to have a high output voltage range. Figure 3.4 presents a simplified schematic of a circuit that uses the folded cascode design for both sides of a differential pair. M1 and M7 transistors are the input for the folded cascode amplifier and another input of the folded cascode is formed by M2 and M6. The current mirror converts the differential signal into a single-ended output by sensing variations in the drain current of M6 to the output. The resulting op-amp is called a folded cascode op-amp. The differential input pair is a source-coupled pair input, M1 and M2 (Figure 3.4). The sources of the input pair are connected to drain M3 that provides bias current (2IB), and the current through the input transistor is given as IB. 45

The drain of the pMOS differential input pair is connected to the source of nMOS transistor folded cascode devices, M6 and M7. If the current of the tail transistor is 2IB, the current of the input transistor will be IB. The output currents of pMOS transistors, M3, M10, and M11 (in Figure 3.4) are equal to 2IB. This affords a maximum balanced output current using a minimal power supply voltage. The current source transistors need to have high output resistance, low noise, and low offset. Therefore, comparatively, they have to operate in strong inversion. The mirror connection uses transistors M4 and M5 and this contributes the high-frequency response since the gate capacitors of the nMOS transistor are smaller to that of the pMOS device. The pMOS transistor sizes are typically selected to be three times larger that of the nMOS to compensate gm for having a three times lower mobility [59]. The mirror connected transistors M4 and M5 must approve three times the bias current (3IB) of one differential input transistor. Therefore, their noise and offset will be reflected three times at the input if these transistors were to be biased in weak inversion as with the input transistors. To avoid this significant amount of noise and offset, the bottom mirror transistors have to be biased in the strong inversion (low gm/ID) [37].

Figure 3.4 Folded cascode circuit amplifier The transconductance of the stage is merely the gm2 of the input pair. Therefore, the DC gain is given as: Gm = g m2

46

(3.1)

R o = R o,up || R o,du

(3.2)

Where, Ro is the output resistance of the cascode single-stage amplifier, and the resistance of transistors M6 and M5 is given by: R o,dn = g m6 ro6 (ro5 ||ro2 )

(3.3)

The resistance of the of upper transistors (M8 and M11) is given by: R o,up = g m8 ro8 ro11

(3.4)

Therefore, the DC gain given by the transconductance of the input stage and the output resistance is: Av = Gm R o

(3.5)

3.2.3 Class-AB output Amplifier Amplifier classes used in ICs are categorized as class-A, -B, and -AB. Class-A represents an output stage with bias current greater than the maximum output current. Therefore, the transistor in class-A is drive over the entire cycle of the input signal. In addition, the output of transistor is continuously conducting current that makes the class-A is inefficient and requires a high current to deliver a symmetrical output waveform (Figure 3.5). The main advantage of class-A is that it is most linear and has the lowest distortion [60]. Class-B was created as a solution to the power efficiency problem with class-A. In the class-B amplifier, there is no DC bias current as its quiescent current is zero. While the active device is switched off for half the input cycle, the active device dissipates less power, and therefore the efficiency is improved. The efficiency is much higher than that of the class-A amplifier. A class-B amplifier has a significant advantage over class-A efficiency since class-B has almost zero current conducted with small signals. A significant disadvantage of the class-B is presenting the distortion especially with small signals. The distortion can be significant even with large signals. This distortion is known as crossover distortion since it occurs at the point when the output stage traverses between sourcing and sinking current. The class-AB (Figure 3.5) amplifier can be considered a as having the same as class-B output. However, class-AB amplifiers differ from class-B amplifiers in that they have a small voltage (VGG1 and VGG2) and this creates quiescent current and slightly increases power consumption, but does not increase it anywhere near as much as class-A. This quiescent current also corrects almost all of the non-linearity associated with crossover 47

distortion. These amplifiers are named class-AB rather than class-A since with large signals, class-AB behaves like class-B amplifiers, but with small signals, class-AB behaves like class-A amplifiers [61]. In addition, the efficiency of class-AB is between 50% and 78.5%, the class-A is between 40% and 50% as well as a class-B is 79 % [62].

Figure 3.5 Amplifier Classes and signals [63] Class-AB output stages are progressively typical in today's low-voltage batterypowered electronics, where amplifier applications demand high efficiency as well as rail-to-rail operation [64]. The output stage is a significant circuit part of an op-amp, as it is the stage that transports the input signal to the load. It is also the stage that uses most of the amplifier bias current and eventually sets limits on the linearity of the amplifier and its maximum tolerated capacitive load. The concept of the class-AB output stage is shown in Figure 3.6, in order avoid reduction of the available or any additional dynamic range [65, 66]. The class-AB output must: 1. Control the quiescent and minimum currents in the output stage transistor accurately, independent of the supply voltage [67]. 2. Have a high maximum current to quiescent current ratio [25]. 3. Avoid reducing the signal path DC gain and stability. 48

4. Be low-voltage compatible. 5. Be straightforward to implement and should not demonstrably increase the silicon area of the op-amp. 6. Be as linear as possible at low and high frequencies [68]. An output amplifier (shown in Figure 3.7) should reach a high maximum output current with a low quiescent current [69]. Moreover, the minimum supply voltage is limited by the output stage, which operates transistors running with adequate high gate-source voltages (Vgs) in order to produce high output currents [70]. Moreover, the supply voltage of the output stage is equal to the sum of the gate-source voltage of M1, the voltage VAB and, the gate-source voltage of M2 as can be determined from Figure 3.6.

Figure 3.6 Concept of a class-AB output stage.

Figure 3.7 Diagram of the output currents of a class-AB 49

The typical control strategy for the output transistor currents in the class-AB stage [71] is feed-forward class-AB control (Figure 3.8). The rail-to-rail operation in the output stage is based on floating class-AB control (based on the trans-linear loop). It contains common-source connected output transistors, M1 and M2, which are controlled by two in-phase signal currents, IN+ and IN-. M3 and M4 establish the floating class-AB control. The stacked diode-connected transistors, M5-M6 and M7-M8, bias the gates of the class- AB transistors M3 and M4, respectively.

Figure 3.8 Feed-forward class-AB control structure The class-AB control transistors, the stacked diode-connected transistors, and the output transistors set up two trans-linear loops, M5, M3 and M1, M7, M4, M2, which determine the quiescent current in the output transistors. To decrease the lowest M6, while M4, M7 and M8 realise the other loop. The main disadvantage is that the quiescent current is sensitive to supply voltage variations. The minimum supply voltage as mentioned in [71] for the resulting circuit, equal to two stacked gate-source voltages and one saturation voltage: VDD(min) = Vgs(M1) + Vsg(M2) + Vds(sat)

(3.6)

An output stage can achieve improved class-AB operation based on the principle illustrated by an independent loop to set each floating voltage necessary for the biasing of the output transistor [70]. The two independent trans-linear loops determine the quiescent current running through the output transistors. Consider that the transistors of the same channel type have been designed with identical threshold voltages and 50

mobility parameters with the voltage for the loop including M1, M3, M5, and M6, it provides: VSG1 + VSG3 = VSG5 + VSG6

(3.7)

Based on the square-law characteristic of transistors, the current I1 can be written as:

2

IB2 IB2 IB1 I1 = K P1 (√ +√ −√ ) K P5 K P6 K P3

(3.8)

Where K = 1/2µ.Cox. Considering the loop formed by M2, M4, M7, and M8, the voltage equation is of the form: VGS2 + VGS4 = VGS7 + VGS8

(3.9)

It can, then, be shown that: 2

IB2 IB2 IB1 I2 = K P2 (√ +√ −√ ) K P7 K P8 K P4 W W W W ( L )2 ( L )8 ( L )7 ( L )4 = = = W W W W ( )1 ( )5 ( )6 ( )3 L L L L

(3.10)

(3.11)

Moreover, IB1 = IB2, while the output current Iout is set to zero, and each of the currents I1 and I2 are decreased to the quiescent current (IQ) running through the transistors M1 and M2. Therefore, W W ( L )1 ( L )2 IQ = [ ] IB2 = [ ] IB2 W W ( L )5 ( L )8

(3.12)

3.2.4 Rail-to-rail input/output op-amp The op-amp contains a differential signal amplification input stage with a differential or single-ended output amplification stage and is designed to operate a dual- or singlerail power supply voltage. The design of low-power and low-voltage circuit operation requires a decrease in the op-amp power supply voltage. However, as opposed to the operation of the circuit at higher voltage levels, lowering the power supply voltage results in a decrease in the AC, DC and transient performance of the op-amp. It is 51

therefore necessary to identify the performance parameters of interest and to ensure that these can be attained. Therefore, the low-voltage operation is considered, here, to mean circuit operation at, or below, +3.3 V. Rail-to-rail operation implies that the amplifier operates correctly to, or close to, the positive and negative power supply voltage levels and can be accomplished by using rail-to-rail input/output circuit design techniques [72, 73] (Figure 3.9).

Figure 3.9 Rail-to-rail input/output op-amp concept In CMOS based circuits, the straightforward and common strategy for the rail-to-rail operation of the input stage is by making use of a p-channel MOSFET differential pair and an n-channel MOSFET differential pair in a parallel connection. This arrangement is usually referred to as a complementary input stage [74] as well as the details present in Appendix C.2. However, as the input signal changes, it results in change in the total transconductance (gmTOT) of the complementary input stage and affects the amplifier DC gain and frequency response. Ideally, the transconductance of the input stage is required to be constant through the entire input voltage range (from the lower power supply voltage (VSS) to the upper power supply voltage (VDD)) in order to reduce signal distortion and to maintain circuit performance [75]. 3.2.5 Design of a fully-differential op-amp The fully-differential amplifier is mostly used in analogue and mixed-signal applications. The form of the fully-differential op-amp is presented in Figure 3.10. It has differential inputs (IN- and IN+) with differential outputs (Out- and Out+). 52

Although an ordinary op-amp’s output is single-ended. The fully-differential op-amp has an extra input, called common feedback. The rationale for the VCMRef input in the fully-differential op-amp is to restrict the output common-mode voltage. A standard opamp with single-ended output uses the same input signal as that of common-mode voltage output. Table 3.1 presents the different between the single output ended and fully differential op-amp. The structure of a fully-differential op-amp design is based on two-stage amplification (as shown in Appendix C.3). The first stage is a folded cascode amplifier and the second stage is operated as a class-AB amplifier. A typical feedback circuit is also added to the op-amp circuit design. VDD IN-

Out+

_ + -

VCMRef IN+

+

OutVSS

Figure 3.10 Fully-differential op-amp configuration Table 3.1 Summary between fully-differential and single op-amp Fully-differential op-amp

Single output op-amp

Differential input and differential output

Differential input and a single output

Need to be symmetrical both side of the outputs

Don’t need for balanced branch

Internally, the current mirror load is replaced by Internally, don’t need to replace by two two matched current sources matched current sources Need additional circuit common-mode feedback Don’t need the extra circuit (commoncircuit mode feedback circuit)

3.3 Feedback systems 3.3.1 Introduction The essence of the feedback system is that part of the output signal that is fed back to the input. Feedback comprises a sub-circuit that allows a portion of the output signal from a system to modify the valid input signal in such a way as to produce a response 53

that can differ substantially from the response generated in the absence of such feedback. Feedback systems are advantageous and widely used in amplifier circuits, oscillators, process control systems, as well as in other types of electronic systems. The feedback tends to be a helpful tool and it must be controlled by an independent method as either a linear or non-linear function. Feedback can be positive or negative. 1. Positive feedback connects the output signal to the positive input signal. The signal returned from the output of the amplifier is identical in phase to the input signal, the difference in the phase between the two signals is equal to 0°. 2. Negative feedback is introduced by connecting the output signal to the negative input signal. The phase difference between the signal returned from the output to the input signal is equal to180°. Feedback refers to the return of part of the output signal to its input so that this portion of the output signal [76] is subtracted from the input feeder signal of the amplifier, as shown in Figure 3.11. Although negative feedback in the amplifier reduces the amplification coefficient, it also improves the reliability of many other aspects of performance such as: •

Increase in the value of the input resistance for a input.



Reduction in the value of the output resistance for output voltage.



Control of the frequency response and bandwidth.



Control of the amplification gain.



Increase in the stability of amplification and reduction in its vulnerability to external factors such as temperature.

Figure 3.11 Basic feedback design with open-loop gain (A) and feedback network (ß) 54

3.3.2 Properties of the negative feedback systems 3.3.2.1 Gain stability The negative feedback tends to decrease the external influences on gain which is commonly identified “gain stability”. In [42, 76], the principle of feedback in Figure 3.12 shows an amplifier (A) and feedback circuitry gain (or feedback factor) as (β). In addition, the input signal (U), the output signal (Y), the feedback signal (V), and the difference signal (X) is: X=U−V

(3.13)

V Y

(3.14)

The feedback factor is given by: β= The open-loop voltage gain is given by: AOL =

(3.15)

Y X

By substrate equation (3.15) in (3.14) V = βAX

(3.16)

By substrate equation (2.16)into (2.13): X = U − βAX → X =

U 1 + βA

(3.17)

Using open-loop voltage gain Y = AX =

A A U= U 1+𝐴 1 + Aβ

(3.18)

Therefore, the closed-loop gain is: ACL =

Y A A = U= U 1 + AOL 1 + Aβ

(3.19)

The amplifier has a gain that depends on the small-signal parameters of the transistor (such as the output resistances and transconductance), there are also variations in temperature and between the circuits. The open-loop gain is much larger than unity,

55

while the closed loop is mostly secure against these variations [77]. If negative feedback is depended, the result of Aβ should be much higher than unity, as in the relation below: ACL =

A 1 ≈ 1 + Aβ β

(3.20)

Hereby, the gain now depends on the feedback element. It is unaffected by variations in temperature, changes in transistor parameters, and/or frequency. Therefore, the gain of the amplifier is stable [42].

Figure 3.12 Negative feedback system 3.3.2.2 Reduces non-linear distortion The voltage gain changes at different a input signal, so the signal has non-linear distortion (or amplitude distortion) and the quality of the output signal reduces of the dynamic range of the active circuit [29]. The negative feedback decreases the non-linear distortion in large-signal amplifiers but this is at cost of reduced gain. 3.3.2.3 Control frequency response The voltage gain of an amplifier can be considered stable in a wide range of signal frequencies. The value of the feedback gain is unaffected by the change in signal frequency, only the feedback factor (β) as described in equation (3.20). 3.3.2.4 Increases circuit stability The negative feedback network is used to achieve stable amplification and the same is true in the case of the decreased output voltage. Consequently, the amplifier stability is significantly increased. 56

3.3.2.5 Input/output impedance The other benefits of using negative feedback are increase in input impedance and decrease in output impedance [77] for voltage derived since applied a typical feedback network is as shown in Figure 3.12. Although Vin/Iin = Z′in, the input impedance of the amplifier with negative voltage feedback is given by: Z ′ in = Zin (1 + Aβ)

(3.21)

When negative voltage feedback is applied, a factor 1 + Aβ increases the input impedance of the amplifier. While Aβ is much higher than unity, the input impedance increases substantially. Feedback with output impedance can describe by: Z ′ out =

Zout (1 + Aβ)

(3.22)

When negative feedback is applied, the output impedance of the voltage output amplifier is reduced by a factor (1 + Aβ). 3.4 Compensation techniques 3.4.1 Introduction The reason for considering stability in circuit design is to ensure that the circuit remains stable under the required operating conditions. Instability occurs when the op-amp is configured with negative feedback and under certain conditions, when the negative feedback becomes positive, the circuit output oscillates. Stability under any input condition is referred to as unconditionally stable, or absolutely stable. However, if a system is not unconditionally stable, a margin of stability must be built-in to ensure stable operation under the required operating conditions. To achieve stable op-amp operation in closed-loop, the designer can add a capacitance between specific nodes within the op-amp that deliberately reduces the open-loop gain magnitude at higher signal frequencies. This technique, referred to as compensation, is implemented typically by bypassing one of the internal op-amp gain stages with a high-pass filter. In the most straightforward sense, a capacitor is connected between the output and input nodes of a gain stage, the purpose then is to decrease the gain magnitude to less than unity at frequencies where instability could occur. A single compensation capacitor implementation is widely used in two-stage op-amp designs. However, there are several other techniques used for op-amp compensation. Improvements to the op-amp 57

performance using the single capacitor compensation approach requires the inclusion of a series resistor or buffer with a series resistor. Other techniques, for example, use multiple feedback capacitors connected to different stages of the circuit. These techniques can also be utilised with the two-stage op-amp. Other techniques require the inclusion of more than two gain stages and with decreases in integrated circuit process geometries, op-amps with more than two gain stages have become more common to achieve a sufficiently high open-loop gain. 3.4.1.1 Miller effect and the Miller technique The Miller effect can be recognised within a MOSFET analogue amplifier circuitry in two ways. Firstly, the Miller effect can be achieved through the structure of the MOSFET where it contains five capacitances between its drain (D), gate (G), source (S), and bulk (B) terminals as shown in Figure 3.13. The overlap capacitance between the drain and gate (CDG) creates feedback between the gate (input node) and drain (output node). While CDG is typically a minimal capacitance, it also shows the effects of the high-frequency response of the amplifier. The CGD is called the Miller capacitance, which appears at the amplifier input and output signal.

Figure 3.13 Structure overlap capacitance of MOSFET The Miller effect reduces the speed (bandwidth) of a MOSFET and CMOS amplifier because the overlap capacitance (CDG) increases the input capacitance and reduces the output capacitance equivalent. In order to extend the high-frequency, the Miller effect must be cancelled or at least reduced [60]. 58

Secondly, it can be achieved by adding a regular capacitor between the input and output nodes of an inverting amplifier. Another example of the electronic design is a two-stage amplifier, wherein the Miller capacitor is between the input and output of the second stage. The advantage of the Miller effect increases the stability of an amplifier and is described in detail in the succeeding sections. Miller’s theorem: “Miller’s theorem states that impedance (Z) can be replaced by two impedances: Z1 connected between node 1 and ground and Z2 connected between node 2 and ground” [60]. It is beneficial and a related technique is established on a typical electronic circuit. A general explanation of the Miller theorem is given in Figure 3.14. The impedance Z is connected between node 1 and node 2 of an inverting amplifier circuit and has gain (-A). The equivalent circuit is presented in (Figure 3.14 (b)). I1 and V1 are input current and input voltage, respectively, whereas, I2 and V2 are the output current and output voltage, respectively. In [42, 60, 78] there is an improved current through an impedance matching the equivalent circuit, while ensuring all of the currents and voltages in the circuit stay unchanged: 1. The current flowing through Z from node1 in Figure 3.14 (a) must be equal to that flowing through Z1 in Figure 3.14 (b). 2. The current injected to node 2 in Figure 3.14 (a) must be equal to that inserted by Z2 in Figure 3.14 (b).

Figure 3.14 Miller effect (a) Amplifier with impedance (b) Equivalent circuit Thus, the gain of the amplifier is the ratio of the output to the input voltage. Therefore, the current through the impedance (Z) is: I=

(V1 − V2 ) 𝑍 59

(3.23)

Z1 =

𝑍 𝑍 and Z2 = 1 (1 + A𝑣 ) (1 + A )

(3.24)

𝑣

Current through Z1 I1 = I1 =

Current through Z2

V1 Z1

I2 =

V1 Z (1 + Av )

I2 =

V2 Z2

V2 Z

1 (1 + A ) v

V1 V1 I1 = = Z Z V2 V1 − V2 (1 − ⁄𝑉 ) ( ) V1 1

I2 =

V2 Z (1 − V

(V1 − V2 ) I= Z

= 1

2⁄

)

V2 Z V2 − V1 ( V ) 2

𝑉1

−(V1 − V2 ) Z I2 = − I

I1 = I

I=

Therefore, in both circuits in Figure 3.14, the currents leaving nodes V1 and V2 have equivalent value so that all nodal equations are matching and analysis of the two circuits provides the same results. To calculate the input impedance of the amplifier with the gain (Av = -V2/V1), connect C with input and output nodes. According to the Miller theory, where the impedance (Z=1/sC) where s is Laplace vector, the capacitor may represent by two capacitors in series C1 = C(1 + A𝑣 ) and C2 = C (1 +

1 ) A𝑣

(3.25)

The C1 and C2 are series capacitors, at gain A, 1 1 (1 + A𝑣 )C(1 + )C (A𝑣 + 2 + A )C2 C1 C2 A𝑣 𝑣 = = =C 1 C1 +C2 (1 + A )C + (1 + 1 )C (A𝑣 + 2 + )C 𝑣 A𝑣 A𝑣

(3.26)

Vx is a new node (Figure 3.14 (b)), merely a voltage divider between V1 and V2 so, Vx = V1 +

C2 (V − V1 ) C1 +C2 2

1 (1 + A ) C

𝑣 Vx = V1 + [ ] (−AV1 − V1 ) 1 (1 + A)C + (1 + ) C A𝑣

60

(3.27) (3.28)

(3.29)

1 ((1 + A𝑣 )C) ((1 + A ) C) 𝑣

Vx = V1 − [

(1 + A𝑣 )C + (1 +

1 A𝑣 ) C

(V1 ) = 0 ]

At the node, Vx is equal to zero (i.e. ground) at all times and C1 and C2 present a voltagedivider ratio. The input capacitance C1 = (1+A𝑣 ).C, is higher than the actual capacitor (C) when the gain |A𝑣 | is large. The capacitor C is called Miller capacitor and the effect of capacitance (C1) is the Miller effect. The capability of the Miller theorem is that it significantly simplifies the analysis for the dominant pole [79] of a circuit having a capacitor between the input and output of an inverting amplifier, which is described later. Analysis of Miller technique using the small-signal circuit of the two-stage of OTA is shown in Figure 3.2 and case-study is shown in Appendix C.4. in case study, the op-amp consists of a nMOS differential amplifier in the first stage (M1 and M2) and M7 as pMOS common-source in the second stage including the composting network block around the second stage. 3.4.1.2 Compensation of rail-to-rail output two-stage CMOS amplifier Figure 3.15 presents a two-stage amplifier, the first stage is folded cascode and the second stage is a class-AB amplifier. The VB voltage source is used to control the gatesource voltage of M13 and M14. Miller capacitor (CC = CC1 + CC2) is connected between the gates of M13 and M14 and the output node (Vout). Figure 3.16 is a small-signal model of the folded cascode op-amp as illustrated in Figure 3.15. In Figure 3.16 and Figure 3.15, 1. “Vin” represents a small signal differential input voltage, 2. “gm1” represents a transconductance of the differential transistor M1, 3. “gm10,8” represents a transconductance of the bias circuit M10 or M8, 4. “gm13,14” is a transconductance of the transistor M13 or M14 of the output buffer, 5. “R1” represents a drain-source resistance Rds1 of the differential transistor pair M1, 6. “R2” is a drain-source resistance Rds6,12 of the current mirror M12 or M6, and 7. “R3” represents a drain-source resistance Rds13,14 of the transistor M13 or M14 of the output buffer. 61

8. Req, here, is the equivalent output resistance of the input cascode stage and may be expressed as Req =gm8.Rds8.Rds1/Rds6. Herein, 9. “Rds8,10” is a drain-source resistance of transistor M10 or M8. 10. “C1” represents the sum of the drain-source capacitance Cds1 of the differential transistor pair M1 and the drain-source capacitance Cds6 of the current mirror M12 or M6. Moreover, a drain-source capacitance Cds8 of the bias circuit M10 or M8 may be approximated to the sum of the drain-source capacitance Cds10 of the bias circuit M10 and the drain-source capacitance Cds8 of the bias circuit M8. 11. “C2” may be expressed as C2 = Cds8+Cds13+gm13.Rds13.Cds13, and may be approximated to gm13.Rds13.Cds13. Here, Cds13 represents a drain-source capacitance of the transistor M13 or M14 of the output buffer. The equation that expresses the DC gain of the folded cascode op-amp can be written as: DC gain = g m1 · R eq · g m13 · R 2

(3.30)

The equation expresses a first pole "pole1" of the folded cascode op-amp as: p1 = −

1 g m13 R eq R 2 Cc

(3.31)

The equation expresses a second pole "pole2" of the folded cascode op-amp as: p2 = −

g m13 CL

(3.32)

The equation expresses a first zero "zero1" of the folded cascode op-amp as: z1 = −

g m13 Cc

(3.33)

Equations (3.30) to (3.33) are predicted values attained from the small signal model (Figure 3.16). Furthermore, the load capacitance CL is considered greater than the Miller capacitance Cc. Moreover, the maximum attainable UGF is a factor two below the bandwidth limiting pole, P2, for stability conditions.

62

Figure 3.15 Folded cascode with the class-AB output stage

Figure 3.16 Small-signal model of rail-to-rail two-stage op-amp 3.4.2 Indirect Miller technique 3.4.2.1 Introduction In section 3.4.1.2, a Miller compensation capacitance was connected between the output node and output of the differential input stage to enhance frequency stability, but it creates a RHP zero, which is a reduced speed op-amp. If the compensation current is fed back indirectly from the output node of the second stage to the internal high impedance node (C1 and C2), the compensation is defined as indirect feedback frequency compensation or simply as indirect compensation [80, 81]. 63

Figure 3.17 Two-stage op-amp folded cascode followed by a class-AB stage with indirect Miller compensation Here, the capacitor compensation is tied to an internal low impedance node of the differential input op-amp, which allows indirect feedback current from the output node to the internal high-impedance node. The indirect compensation is avoided by connecting the compensation capacitor directly to the output of the differential input and, thus, avoiding the RHP zero and enhancing the speed of the op-amp [82]. Figure 3.17 shows an indirectly compensated op-amp utilising a class-AB stage [3]. Here, the compensation capacitor is linked between the output node and the internal low impedance node-C1 and C2. The folded cascode stage is forms the first stage and the class-AB the second stage, and the Miller compensation capacitance can be linked between the output of the second stage and the cascode or the folded point of the first stage [83]. 3.4.2.2 Frequency response indirect Miller compensation The frequency response of indirect Miller compensation is considered by using the small-signal circuit shown in Figure 3.18. In the small-signal equivalent, the capacitor C1 denotes the equivalent input capacitance of the input stage M1, M2, while gm1 demonstrates the transconductance of M1, M2. The resistor Req, here, represents the small-signal output resistance of the cascode input stage and CL is the load capacitance. Applying indirect Miller compensation [35], the non-dominant pole is: 64

p2 ≅ −

CIM g m13 . C1 CL + CIM

(3.34)

The indirect Miller similarly presents a second non-dominant pole [35], which arises due to the finite source impedance of the cascode transistor. It is located at: p3 ≅ −g m8

CL + CIM CL CIM

(3.35)

The dominant pole of the op-amp ends, approximately, at the origin of the complex plane, and is given: p1 ≅ −

1 CIM . R eq g m13 R 3

(3.36)

The UGF of the indirect Miller compensated amplifier is: UGF ≅

g m1 CIM

(3.37)

The UGF of an indirect Miller compensated op-amp is larger than that of a regular Miller compensated amplifier because the bandwidth limiting pole [35, 59] of the indirect Miller compensated op-amp remains at a higher frequency and is set at: UGF =

1 P 2 2

(3.38)

Figure 3.18 Small-signal model of the indirect Miller compensation op-amp 3.4.3 Negative Miller technique 3.4.3.1 Introduction A parasitic capacitance of the CMOS op-amp is not affected when the op-amp is operated at low-frequencies because the parasitic capacitance operates as a short circuit However, at high-frequency it becomes problematic for the op-amp frequency response 65

performance. In the frequency response, a parasitic capacitance between the output and the input nodes can operate as feedback (Figure 3.19), causing the circuit to oscillate at high frequency. Negative Miller capacitance is one way of removing the effect of the parasitic capacitance of the input node. The other terminal of the negative capacitance is “neutralisation” technique [28, 84].The negative Miller capacitance is based on Miller theory, but the voltage gain is considered larger than one. An advantage of the negative capacitance is that it cancels the effects of the input capacitance of the amplifier and improves the UGF [65]. Negative capacitance has a unique property in that it brings about a fall in the voltage when the capacitor is trying to charge up, therefore, the capacitor can create negative capacitance [84]. Similar techniques were put to use to cancel or remove effects of the parasitic capacitance [85-90], which takes advantage of the Miller effect.

Figure 3.19 Capacitance modelling of the MOSFET The Miller effect is a one way to create a negative capacitance. The principle of the Miller effect was explained in the section (3.4.1.1). The unity gain frequency is: UGF =

gm 2πCIN

(3.39)

Where, gm is considered trnscondactance of the MOSFET, CIN is considered as the parasitic capacitance. The effect of the negative Miller capacitance is parallel with CIN. The UGF can increased by including a negative capacitance that can be operated to reduce the value of CIN.

66

3.4.3.2 Negative Miller technique implementation Negative Miller compensation is used to extend the frequency response of an op-amp. To attain this, the method has to implement regular capacitance, and this can be achieved using three different approaches: Approach I: Around the first stage The regular capacitor connected between a non-inverting input of the amplifier (Figure 3.20), with gain A, is now replaced with a feedback capacitance, CNM, to apply the Miller effect and creating a negative capacitance circuit at the input node. Considering the impact of the input capacitance CNM,I is given by: CNM,I = CNM (1 − A)

(3.40)

Figure 3.20 (a) Ideal negative capacitance circuit and (b) Negative Miller equivalent circuit If A=1 is, CNM is not affected. Therefore, when the output voltage equals the input voltage, there is no voltage across CNM and no current flows through it. If the gain A increases (A >1), then a negative capacitance values is obtained and the input capacitance can be reduced [87, 88].

Approach II: Around the third stage of the three-stage op-amp The negative Miller capacitance high-speed CMOS op-amp was initially suggested by [89] and [85] and consists of an operational transconductance amplifier (OTA) and 67

buffer stage. The negative Miller compensation CNN between the input and output of the buffer along with the buffer is considered as the third stage of the amplifier (shown in Figure 3.21). The effective capacitance at input buffer is: CNM,I = CNM (1 − A)

(3.41)

The effective capacitance at the output buffer is: 1 CNM,O = CL + CNM (1 − ) A

(3.42)

An amplifier stage shown in Figure 3.22 (a) with output resistance RL and capacitance CL has a reduced capacitance of CL + CNM (1–A) after attaching, as shown in Figure 3.22 (b). Comparable techniques have been employed to cancel capacitance that appropriates the advantage of the Miller effect. Though the applications of these techniques differ, they utilise the same principle architecture. Bandwidth extension and SR increase have been the driving goals of this research for the last twenty-five years [91].

Figure 3.21 Operational transconductance amplifier (OTA) and buffer [109]

Figure 3.22 (a) Amplifier stage (b) Amplifier stage with negative Miller [90] Approach III: Around entire op-amp The feedback capacitors (CNM) in Figure 3.23. is connected to the output nodes , which use the 180° phase shift between the signals in both nodes and add to the gate-drain 68

overlap capacitance (CGD) of transistors M1 and M2 (in the diff-amp input stage) with a negative sign according to [84]. The amplitude of the output signal falls, and its phase is no longer associated with the input signal. The negative Miller capacitance decreases at these frequencies. Moreover, the capacitor CNM presents an additional load to the output of the stage, which reduces its bandwidth. Finally, if too large a C NM is created, then all capacitance at the input stage would become negative, making the amplifier unstable. This connection of negative Miller compensation is suggested in [92]. The overall capacitance of the output is decreased to make it smaller than the original load capacitance because of the negative Miller capacitance. Moreover, as a result, the negative Miller capacitance compensation technique shifts the first non–dominant pole to higher frequency maintaining the position of the dominant pole, this increases both the UGF and PM.

Figure 3.23 Gain stage with negative Miller capacitance [92]

Figure 3.24 Negative Miller capacitance modelled around the amplifier 69

3.5 Conclusions The op-amp considered in this chapter comprised two-stages of amplification. A simple two-stage OTA was designed and the main parts were identified. A differential input, current mirror, and the active load formed the first stage and the second stage (or the output stage) was formed using a common source amplifier. Moreover, the folded cascode amplifier was utilised due to increase in the gain of first-stage and the classAB amplifier was used to reach rail-to-rail output at low-voltage. The rail-to-rail output op-amp was designed in order for the output signal swing to reach the power supply rails and consisted of the first-stage as a differential input with a folded cascode circuit and a class-AB amplifier as a second stage amplification. The other opamp design included a rail-to-rail input and output op-amp and it was proposed that both the input and output were able to reach the power supply voltage. Moreover, the first-stage was considered a complementary input stage that was connected to the folded cascode circuit. The one-times mirror current was employed to control the transconductance of the complementary input stage. Furthermore, the second stage of the rail-to-rail input and output op-amp was achieved using class-AB amplification. The other op-amp consideration in the chapter was a fully-differential op-amp that was based on the two-stage rail-to-rail output op-amp but which had a differential output. However, a fully-differential amplifier uses an extra circuit called the common-mode feedback circuit used for balancing the common mode output level. To ensure for closed-loop stability of the op-amp is achieved, frequency compensation is required at least two dominant poles in the transfer from input to the output voltage. The most efficient way to achieve stability was deemed to be using the Miller effect (or Miller splitting). The Miller compensation technique was used to achieve gain stability at high frequency. A disadvantage of the Miller compensation is that the unity gain frequency of the opamp is decreased. Miller compensation can be extended to indirect Miller (or cascode Miller) compensation and this technique can increase the op-amp bandwidth when compared to simple Miller compensation. Another compensation type was included the negative Miller compensation, and this was used to extend the unity gain frequency by cancelling or removing the effect of the input capacitance by adding negative capacitance.

70

Chapter 4 Rail-to-rail output CMOS operational amplifier design

4.1 Introduction This chapter presents the design and evaluation of a rail-to-rail output CMOS op-amp. The op-amp is considered as a two-stage amplifier where the first stage is a differential input stage connected in folded cascode and the second stage is a class-AB amplifier. The class-AB amplifier is designed to enable the output to reach the rails of the power supply. The power supply voltages of the op-amp are +2.5 V and ground (GND=0 V) as well as +1.8 V and ground (GND=0 V). This chapter presents three different opamps where the Miller compensation techniques are used to evaluate the frequency response. Section 4.2 presents the structure of a two-stage op-amp and describes the implementation design circuit and layout design. In section 4.2.1, an investigation into input stage folded cascode circuits as well as class-AB configuration is provided. Section 4.2.2 provides an introduction to the op-amp layout design. The evaluation of the frequency response of the op-amps are introduced for the three compensation technique implementations presented. In section 4.3, the first op-amp circuit demonstrates only the conventional (direct) Miller compensation technique, the second op-amp was designed using negative Miller compensation with a direct Miller compensation technique and the third circuit design presents negative Miller and indirect Miller compensation techniques. The three op-amp designs use the same circuit topology as well as the same width and length dimensions of the transistors. However, each op-amp uses a different combination of compensation techniques. The op-amp simulations were undertaken to evaluate unity gain frequency (UGF), phase margin (PM), and DC gain. In addition, a transient analysis was performed to estimate the slew rate and settling time. Furthermore, all simulation studies were performed using the 71

Cadence Spectre circuit simulator. Results from tests performed on a prototype fabricated device +2.5 V and +1.8 V power supply voltage operation are also presented. 4.2 Op-amp design structure Low-voltage and low power operation are the new challenges for op-amp design. An op-amp also has to be designed considering the challenging task of keeping the performance as high as possible. Although it has a significantly good frequency response, a single-stage amplifier is not sufficient on it own to achieve high enough a gain. The two-stage op-amp design, as shown in Figure 4.1, is generally considered. This consists of a first stage that receives a differential input signal and a second classAB stage, the output of the op-amp. The compensation is connected around the second stage of amplification. The two-stages are used to control the gain, provide a high output swing and the required frequency response. A schematic of an op-amp in [93] shows the op-amp as a two-stage amplifier, and the power supply voltage operation is +2.5V and +1.8 V. This specific design looks at four different tasks: increasing DC gain by using two-stages of amplification, obtaining rail-to-rail output range by using class-AB as a second stage output, designing the op-amp at low voltage and low current, and achieving the requried open-loop margin stability and increased UGF by using compensation techniques.

Direct Miller

IN+

+ 2nd stage

1st stage IN-

Output

-

Figure 4.1 Two-stage op-amp structure 4.2.1 Design implementation In the previous chapter, the two-stage op-amp structure was considered, so it is used as shown in Figure 4.2. The circuit design is based on the use of MOSFET transistors. The MOSFET dimension width (W) were selected using the gm/ID approach. As discussed in section 2.3, the gm/ID approach is employed for design at low voltage and low power. 72

In addition, the length (L) is kept as small as possible which is 0.35 µm. The aim of selecting the gate length to be as small as possible was: •

Small gate length means a decrease in the parasitic capacitance and improves the speed of op-amp. At high frequency, frequency response performance is sensitive to the effect of the parasitic capacitance.



Using small channel device reduces the gate current and reduces the output resistance resulting in a reduction in gain.

The op-amp circuit was operated at both +2.5 V and +1.8 V power supply voltage VDD. Therefore, the MOSFET transistors in the circuit were operated between weak and moderate inversion in the saturation region. It should also be noted that the AMS 0.35 µm CMOS process is typically used in analogue design to be operated at +3.3 V. In addition, the drain-source voltage (VDS) is higher than the drain-source saturation voltage (VDSsat). Hence, all transistors are operated in the saturation region. The output characteristic of transistors M11 and M12 used in Figure 4.2 were also described in Figure 2.13 and Figure 2.14. The design summary shown in Table 4.1 of the particular design is given by: •

M1 and M2 form the differential input stage.



M3~M6 are used to create the bias current (M3 is a tail current transistor).



M12~M15 create a wide-swing cascode current mirror.



M8-M9 is used to create a bias voltage for M14-M15.



M16~M19 are the current source transistors.



M10-M11 are used to create a bias voltage for M16-M17.



M22-M28 is floating current source.



M20~M31 forms the class-AB second stage output.



CNM is negative Miller capacitor.



CC is Miller capacitor.



CIM is indirect Miller capacitor.

73

Table 4.1 Dimensions and voltages for transistor operation

74

Figure 4.2 Rail-to-rail output CMOS op-amp with compensation techniques 75

First task: To obtain a high DC gain, A folded cascode circuit has been employed since it is used to improve the DC gain as mentioned in sub-section 3.2.2. The folded cascode circuit has a transconductance (gm) equal to that of one input transistor. The current mirror connected transistors (M18 and M19) in the cascode circuits have the same currents as the differential stage input transistors (2IB). The cascode transistors (M14 and M15) and current source transistors (M12 and M13) create the wide-swing current mirror and is used for producing a high output resistance [94] and increased DC gain that was used in equation (3.5). The wideswing current mirror is presented in Figure 4.3. The DC gain of the first stage is shown in Table 4.2 for +2.5 V and +1.8 V power supply voltage (VDD) using 0.35 µm CMOS typical model (TM) process.

Figure 4.3 Wide-swing cascode circuit Table 4.2 DC gain in a different stage and class-AB amplifier (TM) +2.5 V

+1.8 V

DC gain (First stage) (dB)

50.257

45.90

DC gain (Second stage) (dB)

30.40

30.77

DC gain (Two-stage) (dB)

80.65

76.67

76

Second task: To accomplish rail-to-rail output The common-source output stage M20, M26 is provided using a feed-forward class-AB control and is achieved using transistors M21 and M27, biased by two-phase signal currents from the folded cascode transistors M14 and M16. The output stage is described in section 3.2.3. The gate voltages are kept at a constant value by the stacked diode-connected transistors (M23-M24 and M29-M30). The floating current source transistors are M21 and M22, and their transistors are connected to the stacked diode with feed-forward class-AB control. The output stage with transistor coupled feedforward class-AB control and floating current source is appropriate for designing a compact and power efficient op-amp [95]. The class-AB amplifier and floating current source control is implemented in the cascode circuit to decrease the noise and offset. The noise and offset of the amplifier are mainly determined by the input transistors and the summing circuit [96]. Third task: Low voltage and low current A significant design aspect of the low voltage operation is operating the analogue devices in the subthreshold (weak) region. In this op-amp, the input bias current is 6.55 µA and 825 nA at +2.5 V and +1.8 V power supply voltages, respectively. The circuit design has been built using 0.35 µm CMOS process technology utilising the gm/ID approach for determining MOSFET transistor sizes and operation. 4.2.2 Layout design Integrated circuit layout (IC layout), IC mask layout, or mask design [97], is the description of an integrated circuit in terms of planar geometric shapes which resemble the patterns of metal, oxide, or semiconductor layers that are used for creating the IC. In the IC layout, all cells (pMOS, nMOS, capacitors and resistors) require both VDD and GND connections for the power supply ports. The supply nets (VDD and GND) are connected to each cell design and then to a power supply source. In some ICs, one core power port and one core ground port are adequate while in some ICs, such as mixedsignal or low-power designs, it is necessary to have multiple power and ground ports [98]. The input and output nets are connected to the I/O ports and the pad is used to connect the op-amp circuitry within the IC to the IC package and contains circuitry that is primarily for Electrostatic Discharge (ESD) protection. 77

The layout of the circuit concept is shown in Figure 4.4. Routing of supply ports and signals between the transistors (nMOS and pMOS) and capacitors (e.g., polysiliconpolysilicon capacitors) are made in metal 1, metal 2, and polysilicon layers. In this work, each core used two metal protection rings, referred to as guard rings. The two guard rings surround the op-amp circuit, the inner guard ring is connected to VSS (GND) and the outer guard ring is connected to VDD. A guard ring is fabricated to surround the full core area of the IC as well as possibly discrete blocks. The devices are placed in layout in a symmetrical group. The distance between the symmetry pair creates a significant difference between their electrical properties of the core of the symmetric devices and symmetry groups, it was therefor important to place the devices close to each other. In this work, all layout ICs are presented in Appendix D. The layout design must follow a series of checks in a process known as physical verification. The most common checks in this verification process are [99]: •

Design Rule Checking (or DRC): Design rules are boundaries that are given by semiconductor manufacturers, which allow the designer to verify the accuracy of a location mask. A design rule provides certain geometric and connectivity limits to ensure adequate margins to the description of variability in the manufacturing processes and to ensure that the parts are designed correctly.



Layout Versus Schematic (or LVS): The layout is needed to guarantee good operation with the required circuit for fabrication. The next step is LVS verification, where LVS checking distinguishes the shapes of the layout that denote the electrical components of the circuit, in addition to the connections between them.



Layout parasitic extraction: The integrated parasitic circuits are considered as an impact of the wiring, and the wires are considered as electrical elements of the circuit. However, below the 0.5 µm technology, resistance and capacitance effects of the interconnections begin to create a significant influence on circuit performance [100]. In this work, the Cadence QRC extraction tool was used to extract the layout parasitic components (as parasitic capacitances, resistances, or even inductances) which would then be used with the schematic for estimating the performance of the post-layout circuit.

78

Inner ring

I/O

I/O Pads

(VDD)

Outer ring

Pads

(VDD)

GND

Cell 1

Cell 2

I/O Pads

I/O Pads

VDD

Figure 4.4 Concept of layout design 4.3 Compensation techniques Direct Miller compensation, often referred to pole splitting [101, 102], is usually utilised for frequency compensation in a two-stage op-amp. Figure 4.5 shows the general structure for an op-amp using direct Miller compensation and is consider as first opamp configuration. Miller compensation is described in section 3.4.1.2. The dominant pole (P1) was moved closer to the origin, whilst the non-dominant pole (P2) is relocated to a high frequency. The UGF, therefore, is controlled by the domiant pole and Miller capacitance only. Figure 4.2 shows the configuration of a two-stage amplifier employing Miller compensation. The limiting pole frequency, if loaded with a load capacitance CL, is estimated as: p2 =

Gm2 2 π CL

(4.1)

Where, Gm2= gm20 ≈ gm26. UGF is obtained using Miller capacitors Cc1 and Cc2. The Miller capacitors determine the UGF of the amplifier and must be chosen as half of p2, UGF =

Gm1 1 1 Gm2 = p2 = 2 π Cc 2 2 2 π CL

(4.2)

Where, Gm1 is the transconductance of the input transistor, and Gm2 ≈ gm20 ≈ gm26 is the transconductance of the output stage, Miller capacitance is Cc = Cc1 + Cc2. Therefore, the Miller capacitance has to be chosen approximately as follows:

79

Cc = 2 CL

Gm1 Gm2

(4.3)

The UGF and the second pole determine the PM, it is given by PM = tan−1

p2 Gm2 Cc = tan−1 UGF Gm1 CL

(4.4)

The compensation capacitor provides negative feedback around the output stage and also provides a direct feed forward path through the transistor to the output. The feed forward path is produced as a zero and is situated in the Right Half-Plane (RHP). This zero introduces an additional phase shift since the zero is relocated in the RHP and degrades the amplifier’s speed, particularly when the load capacitor value is of the same order as that of the compensation capacitor. Cc1 IN+

+

Folded cascode

1st stage IN-

-

+

A1 A2

2nd stage

Output

Cc2 Direct Miller capacitance

Cc = Cc1 + Cc2 Figure 4.5 Structure of two-stage class-AB output op-amp using Miller compensation (first op-amp) Using negative Miller, as mentioned in chapter 3, it can be used to extend the frequency response since it cancels or removes the effect of input capacitance, as shown in Figure 4.6 and is considered the second configuration. The negative Miller capacitance is used around the first stage of op-amp, which is placed between the input nodes and output nodes of the first stage as presented in Figure 4.2. Negative Miller compensation is divided between two capacitors.

80

Cc1

CNM1 IN+

-

+

Folded cascode

st

1 stage IN-

-

+

A1 A2

2nd stage

Output

Cc2

CNM2

Direct Miller capacitance

Negative Miller capacitance

Cc = Cc1 + Cc2

CNM = CNM1 + CNM2

Figure 4.6 Structure of two-stage class-AB output op-amp using negative Miller and direct Miller compensation (second op-amp) The first capacitor (CNM1) is located between the non-inverting input node and the output node (B1) of the first stage while the other capacitor (CNM2) is between the inverting input and output node (B2) of the first stage. These capacitors present parallel impact with actual input capacitance. The negative capacitance eliminates or reduces the actual input capacitance resulting in an increase in the UGF. As a result, the PM is increased when combining negative Miller with direct Miller. 1. Miller compensation is used to improve the margin stability, but it decreases the UGF. 2. Negative Miller is used to enhance UGF since it is used to reduce the effect of the parasitic input capacitance. The third design configuration of an op-amp incorporates negative Miller with indirect Miller and is described in Figure 4.7. Negative Miller compensation surrounds the first stage and this design is used to cancel or remove the effect of input capacitance. The second stage is incorporated with indirect Miller compensation between the cascode nodes (C1 and C2) of the first stage and the output node and: 1. Indirect Miller capacitors (CIM) are used to improve the margin stability and the UGF. 2. Negative Miller is used to enhance UGF.

81

CNM1 IN+

-

CIM1

Folded cascode

2nd stage

-

+ 1st stage

IN-

C1

Output

+

CNM2

C2

CIM2 Indirect Miller capacitance

Negative Miller capacitance

CIM = CIM1 + CIM2

CNM = CNM1 + CNM2

Figure 4.7 Structure of two-stage class-AB output op-amp using negative Miller and indirect Miller compensation (third op-amp) 4.4 Simulations using Cadence Spectre The op-amps were designed to be operated for power supply voltage (VDD) +2.5 V and +1.8 V and internally compensated utilising three techniques, direct Miller, negative Miller and indirect Miller compensation. The op-amps were designed using a standard 0.35 µm CMOS (n-well) technology. The threshold voltage (typically of 0.35 µm process) of the nMOS transistor was approximately 0.5 V and for the pMOS transistor was approximately 0.71 V. Figure 4.8 shows the circuit diagram block for the op-amp. The ports of the op-amp block are connected to the I/O pads.

Figure 4.8 Op-amp block connected to the I/O pads 82

All the simulations were performed using typical model process transistor models and was undertaken using the Cadence Spectre circuit simulator. The op-amp has been tested for the different process variations as a typical model, worst-case power (WP), worst-case speed (WS). In addition, a full Monte Carlo analysis was performed. The criteria for the design goals are shown in Table 4.3 and are based on hand calculations using equations (4.1), (4.2), (4.3) and (4.4). The design performance specifications are shown without I/O and power supply pads as well as without layout parasitic extraction. The PM is more significant than 60°, UGF is 22.65 MHz, load capacitance (CL) is 2 pF and direct Miller capacitance (Cc) is 540 fF. The input transconductance (gm1) and the output transconductance (gm2) are 77.65 µS and 570 µS, respectively. In addition, these specifications are hand calculated results and are modified for simulation while the values of CC and CL remain unchanged. Table 4.3 Op-amp design specification (VDD = +2.5 V) Specification

Simulation modification (TM)

DC gain (dB)

> 70

80.66

PM (degree)

≥ 60

55.41

UGF (MHz)

22.65

17.58

Load cpacitor CL (pF)

2.0

2.0

Miller capacitor Cc (fF)

540

540

77.25

76.83

570

573.1

Input trnascodactnce gm1 Output trnascodactnce gm2

4.4.1 Frequency response The op-amps were simulated using different approaches. Firstly, the op-amps were simulated with process corners (or process variations). The expression ‘Process Corner’ implies the variations in the performance metrics because of manufacturing variations [102]. The process corners are counted where the op-amp is simulated with worst-case power (WP) and worst-case speed (WS) device models for the Spectre simulation models for the process devices. That means, the typical model is where the nMOS and pMOS transistors operate at normal speed, worst-case speed means slow nMOS and slow pMOS transistors, and worst-case power means fast nMOS and fast pMOS transistors. Secondly, the pad is utilised to link the op-amp circuitry within the IC to the IC package, primarily for electrostatic discharge (ESD) protection. Moreover, I/O pads are semiconductor material which can also an impact on the output signal at higher 83

frequencies. Thirdly, the parasitic capacitance has been extracted and simulated with the op-amp circuit. Finally, the op-amp was simulated using Monte Carlo analysis. The principal purpose of this analysis is that the outcomes are calculated established on random statistical analysis. The operation of the op-amp was evaluated in simulation using Cadence Spectre and considering physical process variations. The simulation results of the first op-amp, as shown in Table 4.4, identify that for the op-amp operating on a +2.5 V and +1.8 V power supply voltage, DC gain, UGF and PM are presented. Each of the UGF and PM is reduced after adding I/O pads while the low frequency gain remains unchanged. The reason is that, the I/O pads also have parasitic capacitance, and these parasitic capacitances have behaved as a closed circuit at high frequency. As a result, the UGF and PM have reduced. While, at low frequency, the parasitic has acted as an open circuit, therefore, this has no impact on the gain. The same phenomena is observed for the second op-amp (Table 4.5) and the third op-amp (Table 4.6)

Process variations

Table 4.4 Process variations (first op-amp) (no output load) Process variations without I/O pads Without layout parasitic extracted +2.5 V

With layout parasitic extracted

+1.8 V

+2.5 V

+1.8 V

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

Gain dB

PM Degree

UGF MHz

Gain dB

PM degree

UGF kHz

TM

80.66

70.38

16.82

77.91

73.29

214.2

80.66

66.51

17.56

77.91

69.9

246.2

WP

71.91

53.64

446.5

36.92

91.32

10,62

71.91

40.9

408.0

36.92

90.24

9,334

WS

87.53

72.77

1,431

79.92

74.24

14.73

87.53

68.98

1.303

79.92

70.79

14.17

Process variations

Gain dB

Process variations with I/O pads Without layout parasitic extracted +2.5 V

With layout parasitic extracted

+1.8 V

+2.5 V

+1.8 V

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

TM

80.66

60.57

15.98

77.91

65.18

225.8

80.66

50.68

16.58

77.91

55.70

236.9

WP

71.91

37.65

394.4

36.92

89.06

10,59

71.91

26.37

326.0

36.92

86.65

9,279

WS

87.53

63.71

1.320

79.92

65.00

14.34

87.53

53.87

1.23

79.92

55.28

13.10

84

Process variations

Table 4.5 Process variations (second op-amp) (no output load) Process variations without I/O pads Without layout parasitic extracted +2.5 V

With layout parasitic extracted

+1.8 V

+2.5 V

+1.8 V

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

TM

79.79

78.24

18.12

76.68

84.18

263.5

79.70

83.07

17.52

76.66

80.24

246.3

WP

71.83

60.68

509.8

34.94

98.89

6,390

71.38

54.25

471.8

34.98

98.28

5,714

WS

86.24

85.06

1.348

78.61

87.75

15.37

86.24

80.71

1.296

78.83

83.28

14.42

Process variations

Gain dB

Process variations with I/O pads Without layout parasitic extracted +2.5 V

With layout parasitic extracted

+1.8 V

+2.5 V

+1.8 V

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

TM

79.12

69.1

17.16

76.68

73.87

244.8

79.85

55.34

18.12

76.66

64.07

224.0

WP

71.83

44.67

419.8

34.94

97.48

6,380

71.83

31.32

343.0

34.90

36.00

5,696

WS

86.25

73.84

1.283

78.61

76.31

14.26

86.24

60.45

1.288

78.40

65.67

12.18

Table 4.6 Process variations (third op-amp) (no output load) Process variations

Process variations without I/O pads

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

TM

79.74

99.48

24.23

76.68

101.06

321.9

78.93

86.18

23.10

76.71

89.3

311.6

WP

71.83

51.8

1,023

34.90

97.61

8,610

71.84

30.74

973.6

34.90

96.32

8,553

WS

86.24

97.34

1.661

79.15

99.63

18.29

86.24

92.45

1.638

78.96

94.51

18.04

Without layout parasitic extracted +1.8 V

+2.5 V

+1.8 V

Process variations

+2.5 V

With layout parasitic extracted

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

Gain dB

PM degree

UGF MHz

Gain dB

PM degree

UGF kHz

TM

79.74

86.94

24.20

76.67

82.62

327.4

78.93

56.62

26.29

78.70

68.27

309.6

WP

71.83

28.83

722.4

34.90

95.82

8,590

71.83

11.31

533.2

35.90

42.98

8,500

WS

86.24

85.31

1.705

79.15

87.56

18.65

86.24

63.01

1.961

78.86

71.40

17.91

Process variations with I/O pads Without layout parasitic extracted +2.5 V

With layout parasitic extracted

+1.8 V

+2.5 V

+1.8 V

Monte Carlo analysis can be applied to calculate circuit metrics, for example, the gain, UGF and PM of an op-amp. Through a Monte Carlo analysis, the netlist parameters change for each Monte Carlo analysis and the output computed. The Monte Carlo 85

analysis, therefore, becomes a tool that predicts and assesses circuit performance variations. Figure 4.9 shows the gain that it is calculated 200 times with frequency for both +2.5 V and +1.8 V power supply varying the netlist parameter using Monte Carlo.

Figure 4.9 Frequency response varying with Monto Carlo (first op-amp) (no output load) Figure 4.10 presentes UGF for both +2.5 V and +1.8 V power supply operation for the first op-amp design. At +2.5 V power supply voltage, UGF has ranged between 2.73 MHz to 95.1 MHz while +1.8 V power supply voltage is between 24.4 kHz to 3.18 MHz. In Figure 4.11, the PM is between 33.35° and 66.54° at +2.5 V whereas the PM varies between 48.59° and 71.54° at +1.8 V operation voltage.

Figure 4.10 Monto Carlo analysis result: no. of samples versus UGF (first opamp) (no output load)

86

Figure 4.11 Monto Carlo analysis result: no. of samples versus PM (first op-amp) (no output load) The gain has been changed 200 times and plotted against frequency as shown in Figure 4.12. The UGF of the second op-amp is shown in Figure 4.13, the UGF is between 1.22 MHz to 82.1 MHz for +2.5 V. For +1.8 V, the UGF is between 11.1 kHz to 2.53 MHz (117 iterations for 11.1 kHz, 30 iterations for 290 kHz. i.e..). For +2.5 V, The PM is varied between 48.63° and 87.71° (6 iterations for 48°, 13 iterations for 52.97°. i.e..). While between 55.44° and 92.30° for +1.8 V power supply operation (2 iterations for 55.44°, 5 iterations for 59.54°. i.e..) as shown in Figure 4.14.

Figure 4.12 Frequency response varying with Monto Carlo (second op-amp) (no output load)

87

Figure 4.13 Monto Carlo analysis result: no. of samples versus UGF (second opamp) (no output load)

Figure 4.14 Monto Carlo analysis result: no. of samples versus PM (second opamp) (no output load) The gain has been altered 200 times and plotted against frequency for third op-amp and presented in Figure 4.15. In the case of +2.5 V power supply operation, the UGF is 88

between 1.37 MHz to 112 MHz, 80 iterations for 1.37 MHz and 48 iterations for 13.7 MHz. i.e. For +1.8 V has UGF between 12.7 kHz and 3.34 MHz (124 iterations for 12.7 kHz, 31 iterations 382 kHz. etc.). The PM for +2.5 V is varied between 56.01° and 109.30° (8 iterations for 56.01°, 11 iterations for 61.93°. etc.). While between 61.46° and 110.20° for +1.8 V power supply operation (2 iterations for 55.44 °, 5 iterations for 59.54°. etc.)

Figure 4.15 Frequency response varying with Monto Carlo (third op-amp) (no output load)

Figure 4.16 Monto Carlo analysis result: no. of samples versus UGF (third opamp) (no output load)

89

Figure 4.17 Monto Carlo analysis result: no. of samples versus PM (third opamp) (no output load) Figure 4.18 shows the frequency response of the op-amp at +2.5 V and VSS=0 V. The simulation has made with a TM (typical model) for the gain that is measured in dB and phase that measured in degrees. All op-amps have the same DC and low frequency gain, it is approximately 80dB while they have a different frequency at 0 dB since a compensation has been made the difference and improved.

Figure 4.18 Frequency response (top) and phase (bottom) at +2.5 V (no output load) 90

Figure 4.19 presents the frequency response for +1.8 V power supply operation. The gain at low frequency is about 76.61 dB for all op-amps. At 0 dB gain, the frequency is different for all op-amps because of the compensation techniques.

Figure 4.19 Frequency response gain (top) and phase (bottom) at +1.8 V (no output load) 4.4.2 Slew rate and settling time Slew rate (SR) describes as fastest possible the op-amp output can follow an input signal. Consider the unity-gain configuration of Figure 4.20 with a step signal used at the input. In order to define a SR) of an op-amp, the SR is described as the maximum rate of output change voltage per unit of time and is expressed as volt per second. Table 4.7 describes the SR at a different rise time of 1 µs and 100 µs for +2.5 V and +1.8 V power supply operation. The input signal is applied from (VDD /2) − 0.5 to (VDD /2) +0.5, i.e. varying over different supply voltage variations with a rise time of 1 µs and 100 µs. In this case, Figure 4.21 to Figure 4.24 present the input signal and output signal transient variations of the op-amps. The third op-amp shows slightly high SR for both power supply voltages. In addition, at the +2.5 V power supply voltage level the high SR is very high and therefore the op-amp has been operated at +1.8 V power supply voltage because of the small current flow through them.

91

Figure 4.20 Concept of SR and settling time Table 4.7 Summary of the SR (TM and CL=5 pF)) Large-signal Power supply voltage

+2.5 V

+1.8 V

1 µs

100 µs

Period SR+ (V/ µs)

SR- (V/µs) SR+ (V/µs)

SR- (V/µs)

First op-amp

4.1617

3.4645

0.0614

0.0661

Second op-amp

5.8892

3.5623

0.0541

0.0440

Third op-amp

5.8503

7.3237

0.0687

0.0701

Small-signal Power supply voltage

+2.5 V

+1.8 V

1 µs

100 µs

Period SR+ (V/ µs)

SR- (V/µs)

SR+ (V/µs)

SR- (V/µs)

First op-amp

6.9451

5.4280

0.0603

0.0666

Second op-amp

5.8068

4.0668

0.0517

0.0548

Third op-amp

5.9477

3.8707

0.0674

0.0764

Settling time is defined as the time it requires for the output response to following settle a step alteration in the inputs. In order to determine the settling time of the amplifier, a 5-mV step was operated at the input. To ensure that the step was utilised within rational ranges between ground (GND = 0) and supply (VDD = +2.5 V and +1.8 V), the input step was applied from (VDD /2) − 0.5 to (VDD /2) +0.5, i.e. varying over different supply voltage variations. If the applied step was close to either rail, the voltage headroom for 92

several devices became too small. Hence they entered the cut-off region. The different input steps over the supply voltage variations is shown in Table 4.8. Table 4.8 Summary of the settling time (TM and CL=5 pF) Large-signal Power supply voltage (V)

+2.5 V

+1.8 V

1 µs

100 µs

Period

Settling time

Settling time

Settling time

Settling time

Hi-Lo (ns)

Lo-Hi (ns)

Hi-Lo (µs)

Lo-Hi (µs)

First op-amp

287.9

911.5

17.21

72.21

Second op-amp

339.4

959.2

19.22

73.69

Third op-amp

298.7

852.9

18.44

69.78

Small-signal Power supply voltage (V)

+2.5 V

+1.8 V

1 µs

100 µs

Period

Settling time

Settling time

Settling time

Settling time

Hi-Lo (ns)

Lo-Hi (ns)

Hi-Lo (µs)

Lo-Hi (µs)

First op-amp

219.2

762.2

5.779

59.70

Second op-amp

204.5

804.9

5.139

60.88

Third op-amp

196.4

804.1

5.364

60.88

Figure 4.21 Step response (large-signal) at +2.5 V, step (period 1 µs, CL= 5 pF and TM) 93

Figure 4.22 Step response (small-signal) at +2.5 V, step (period 1 µs, CL= 5 pF)

Figure 4.23 Step response (large-signal) at +1.8 V, step (period 100 µs, CL= 5 pF)

94

Figure 4.24 Step response (small-signal) at +1.8 V, step (period 100 µs, CL= 5 pF and TM) 4.4.3 Output swing range In addition, transient analysis results are shown in Figure 4.25. The transient analysis was undertaken using the unity gain configuration. The transient simulation was started with the input voltage swept from 0 V to +2.5 V. The VOUT and VIN versus time characteristic was plotted to determine the output swing range, the range of input voltage where the circuit has a gain of approximately one. The output swing is rail-torail as well as producing low and high output voltages of 0.0016 V to 2.4988 V, respectively, for the first op-amp at 10 kHz. At 1 MHz, the first op-amp is clipped because it is not fast enough to be able to follow the input that at high frequency. It is the same for second and third op-amps, Table 4.9 presentes as the output swing for three op-amps at different frequencies.

95

Table 4.9 Summary of the output swing range (TM and no output load) Power supply

+2.5 V

Frequency First op-amp

Second op-amp

Third op-amp

+1.8 V

10 (kHz)

1 (MHz)

1 (kHz)

10 (kHz)

VOH (V)

2.4988

2.1698

1.7999

1.6190

VOL (V)

0.0016

0.0402

8.5390e-04

0.0030

VOH (V)

2.4988

2.2268

1.7999

1.6696

VOL (V)

0.0016

0.04127

9.041e-04

0.0049

VOH (V)

2.4988

2.2523

1.7999

1.6903

VOL (V)

0.0013

0.0141

5.5182e-04

4.045e-05

Figure 4.25 Transient response at +2.5 V, at 10 kHz (TM and no output load)

96

Figure 4.26 Transient response at +2.5 V, at 1 MHz (TM and no output load)

Figure 4.27 Transient response at +1.8 V, at 1 kHz (TM and no output load)

97

Figure 4.28 Transient response at +1.8 V, at 10 kHz (TM and no output load) 4.4.4 Comparison of op-amp works Table 4.10 shows the comparison with other research. The UGF is related to power dissipation. The UGF increases with increasing power dissipation. In this work, the power dissipation is small compared with the other listed work [103-107]. The UGF of the second and third op-amps is 263.5 kHz and 356.4 kHz since the power dissipation is only 1.287 µW. The PM values for the second and third op-amps are also presented and are 84.18° and 94.06°, respectively. While, [104, 105] have power dissipation values 1.44 mW and 2.13 mW, respectively. Table 4.11 is the comparison of the second and third op-amps at +2.5 V with [108-112] that designs with a different process. The third op-amp has substantial power dissipation comparing with other reported work.

98

Table 4.10 Summary of op-amp comparison works Reported work Performance

[103]

[104]

[105]

Third op-amp

(TM)

(TM)

+1.8

+1.8

+1.8

Process (µm)

1.2

0.18

0.18

0.18

0.18

0.35

0.35

DC gain (dB)

80

35.6

60.49

90.79

72.04

76.68

76.68

UGF (MHz)

0.350

134.2

538.3

14.23

13.33

0.2635

0.3564

PM (degree)

50

61

59.64

54.8

62.4

84.18

94.06

11.5

11.63

0.0541

0.0687

19.22

18.44

5

5

94.1

+1.8

Second op-amp

+1.8

Settling time (µs)

+1.8

[107]

Power supply (V)

SR (V/ µs)

+1.8

[106]

0.014

CL (pF)

5.6

1

10

VOH (V)

1.799

1.71

1.7999

1.7999

VOL (V)

0.0018

0.001

0.00904

0.00551

0.35-1.45

0.10-1.7

0-1.42

0-1.42

1.287

1.288

ICMR (V) Power dissipation (µW)

55

1440

2130

167

129.553

Table 4.11 Summary of op-amp simulations Reported work [108]

[109]

[110]

[111]

[112]

Second op-amp (TM)

Third op-amp (TM)

Power supply (V)

2.5

2.5

2.5

2.5

2.5

+2.5

+2.5

Process (µm)

0.13

0.65

0.18

0.35

0.25

0.35

0.35

DC gain (dB)

102

95

46.5

81

61

79.79

79.79

UGF (MHz)

40.5

2.5

9.9

0.820

25

18.43

23.41

Performance

PM (degree)

90

54

75

76

52

80.89

91.67

65.1

1.11

3.2

10

3

4.889

8.850

Settling time (ns)

50

0.65

62

339.4

298.7

CL (pF)

5

1

5

5

VOH (V)

2.47

2.4988

2.4988

0

0.0016

0.0013

0-1.947

0-1.947

146.1

146.1

SR (V/µs)

VOL (mV) ICMR Power dissipation (µW)

10

0.54-2.46 977

155

403.0

12

625

4.5 Physical prototype test The fabricated circuit die was housed within a Ceramic Leadless Chip Carrier (CLCC) package as shown in Figure D. 1. In addition, the physical prototype is shown in Figure D. 4. The physical prototype was tested using an SF880 instrument shown in Figure F. 1. Table 4.12 shows a summary of its characteristics as defined in [113]. The device is 99

used to test open-loop and closed-loop configurations of the op-amp in order to determine the PM and UGF. For the test, the open-loop configuration and the output terminal of SF880 is connected to the inverting input of the op-amp circuit. Table 4.12 Characteristics of the frequency response analyser (model SF880) Performance

Range

Frequency range

1 Hz - 150 MHz

Signal amplitude

0.05 to 6.0 Volts peak-to-peak (Selectable)

Signal offset Integration time Input characteristics

- 1 Volt to + 1 Volt (Selectable) 10 ms to 10 S (Selectable) RTest =1 MΩ in parallel with CTest =10 pF

Figure 4.29 demonstrates the method that is used for physical prototype testing and is considered for investigating open-loop and closed-loop configurations. Then, the output of the op-amp was connected to the CH2 while CH1 was connected to Vref. The closedloop configuration is an inverting op-amp circuit. The output of SF880 is connected to the inverting input and CH1, while CH2 is the output of the op-amp. The ratio CH2/CH1 is the gain of op-amp that is presented on the PC. Table 4.13 shows the test results from the test of physical op-amps.

Figure 4.29 Physical prototype testing open-and closed-loop using the SF880 The results show the op-amp performance in open- and closed-loop circuit configuration. With this implementation, for +2.5 V power supply operation, both opamps are not stable in closed-loop. However, the op-amps are stable in closed-loop for +1.8 V operation. At +2.5 V power supply the input differential tail current is increased, 100

this increment results in an increased UGF but with a reduced margin of stability. Figure 4.30 illustrates the frequency response for the second op-amp at +2.5 V operation showing the open-loop gain and closed-loop gain, while Figure 4.31 presents the frequency response at +2.5 V setup for the third op-amp.

Figure 4.30 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF)

Figure 4.31 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest = 1 MΩ with CTest = 10 pF)

101

For VDD = +1.8 V setup, the UGF reduces, but the margin of stability increases. Figure 4.32 shows the frequency response for the second op-amp operating at +1.8 V showing the open-loop gain and closed-loop gain. Figure 4.33 shows the frequency response at +1.8 V setup for the third op-amp.

Figure 4.32 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF)

Figure 4.33 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF)

102

Table 4.13 shows the test results from the physical op-amps tested. The results show the op-amp performance in open- and closed-loop circuit. With this implementation, for +2.5 V power supply operation, both op-amps are not stable in closed-loop. However, the op-amps are closed-loop stable at +1.8 V operation even with CTest and RTest. Table 4.13 Summary of the physical prototype open- and closed-loop frequency response of the physical op-amps tested (RTest =1 MΩ with CTest =10 pF) Open-loop

Second op-amp Third op-amp

Second op-amp Third op-amp

+2.5 V +1.8 V Gain -3dB PM UGF Gain -3dB PM UGF (dB) (dB) (kHz) (degrees) (MHz) (kHz) (degrees) (kHz) 70.27 16.10 13.97 10.7 56.65 2.10 50.0 481.13 69.75 15.44 19.04 12.5 57.45 1.22 46.87 526.6 Closed-loop +2.5 V +1.8 V Gain -3dB PM UGF Gain -3dB PM UGF (dB) (kHz) (degrees) (MHz) (dB) (kHz) (degrees) (kHz) 20.03 4.2 -23.3 9.6 19.98 58 52.17 476.4 20.05 4.0 -37.6 12.2 20.06 73.50 48.73 515.1

To attain stability of op-amps at a +2.5 V power supply voltage, the effect of CTest and RTest of the test equipment must be reduced. Figure 4.34 presents the op-amp circuit which uses RX and CX and connected series with the CTest and RTest in order for increasing the PM and resulting gain whereas UGF is reduced. Figure 4.35 and Figure 4.36 show open- and closed-loop frequency response respectively.

CX

RX

Figure 4.34 Physical prototype testing open-and closed-loop using the SF880 with CX and RX 103

Table 4.14 shows the test results from the physical op-amps tested. The results present the op-amp performance in the open- and closed-loop. In open-loop, the second and third op-amps show a stability 51.55° and 60.87°, respectively. For the closed-loop performance, the PM is 64.6° and 62.4° for second and third op-amps respectively.

Figure 4.35 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF and RX=1 MΩ with CX =10 pF)

Figure 4.36 Frequency response of the prototype op-amp: top (gain) and bottom (phase) (RTest =1 MΩ with CTest =10 pF and RX =1 MΩ with CX =10 pF)

104

Table 4.14 Summary of the physical prototype open- and closed-loop frequency response of the physical op-amps tested (RTest =1 MΩ with CTest =10 pF and RX= 1 MΩ with CX= 10 pF)

Second op-amp Third op-amp

Gain (dB) 64.2 63.42

Second op-amp Third op-amp

Gain (dB) 14.16 14.16

Open-loop +2.5 V -3dB PM (kHz) (degrees) 3.7 51.55 2.8 60.87 Closed-loop +2.5 V -3dB PM (kHz) (degrees) 3.5 64.6 3.6 62.4

UGF (MHz) 5.5 7.2

UGF (MHz) 3.2 4.2

4.6 Analysis and discussions For adequate stability, an op-amp needs a PM value greater than 45° when making use of the open-loop configuration. Table 4.15 shows the load capacitor (CL), UGF, and frequency at a gain -3dB when the op-amps have 45° PM (without load resistance). In the case of the first op-amp at +2.5 V power supply operation, the load capacitance is 1.2 pF, resulting in value of 15.77 MHz for UGF and 1.703 kHz for the -3dB frequency. Table 4.15 Summary of op-amps when PM= 45° (TM) +2.5 V

+1.8 V

CL (pF)

UGF (MHz)

-3dB (kHz)

CL (pF)

UGF (MHz)

First op-amp

1.2

15.77

1.703

2.7

217.21

0.3236

Second op-amp

3.6

11.83

2.013

6.1

157.56

0.3697

Third op-amp

3.68

16.77

2.000

6.3

218.08

0.3697

-3dB (kHz)

The improvement is very well-defined when the op-amps are operated with a +1.8 V power supply. The load capacitance increases from 2.7 pF to 6.3 pF, and as Figure 4.37 and Figure 4.38 show the PM and UGF versus load capacitance when the op-amps work at +2.5 V and +1.8 V power supply operation.

105

Figure 4.37 PM and UGF versus load capacitance (CL) (+2.5 V)

Figure 4.38 PM and UGF versus load capacitance (CL) (+1.8 V) The input characteristic of the SF880 model is 1 MΩ paralleled with 10 pF [113]. The equivalent deign for test using Cadence Spectre is given in Table 4.16 and Table 4.17 for the second op-amp and third op-amp, respectively, considering the I/O pads and layout parasitic extraction. The open-loop of the second op-amp is operated with RL=1 MΩ and is paralleled with CL=10 pF. For a +2.5 V power supply voltage, PM is not stable at all process variations for both op-amps. In the case of +1.8 V power

106

supply, PM is stable in both WP (worst-case power) and WS (worst-case speed) process variations, but it is not stable at TM (typical model). Table 4.16 Second op-amp CL= 10 pF and RL=1 MΩ (open-loop) +2.5 V Gain (dB)

-3dB (kHz)

PM (degrees)

+1.8 V UGF (MHz)

Gain (dB)

-3dB (kHz)

PM (degrees)

UGF (kHz)

TM

79.02

1.831

35.24

9.409

67.99

0.8306

37.92

157.7

WP

71.80

104.7

18.19

153.7

36.31

102.6

84.98

5,700

WS

81.23

0.9102

38.47

0.733

42.22

0.2092

82.27

2.861

Table 4.17 Third op-amp CL= 10 pF and RL=1 MΩ (open-loop) +2.5 V Gain (dB)

-3dB (kHz)

PM (degrees)

+1.8 V UGF (MHz)

Gain (dB)

-3dB (kHz)

PM (degrees)

UGF (kHz)

TM

79.07

2.002

32.88

11.76

67.95

0.9688

38.05

225.6

WP

71.81

121.6

13.07

218.3

36.31

138.6

77.81

8,169

WS

81.23

0.100

39.19

1.031

42.24

0.3331

80.11

4.696

4.7 Applications Op-amps are a significant electronic circuit that aid the use of an analogue and mixed signal circuits. Through utilising a ratio of two resistors to attain a preferred gain, an output voltage equal to the input voltage can be defined and measured. The tests accomplished for this experiment demonstrates the desired output that can be achieved through the use of an op-amp. Here R1 is 1 kΩ and R2 =10 kΩ the closed-loop gain is 10 V/V for inverting op-amp. Moreover, the gain of non- inverting is 11 V/V. Features: Rail-to-rail output op-amp, low voltage (1.8 V) and low current (1.28 µW), stable at open and closed-loop configuration, UGF is 481.13 kHz and PM is 50° for the second op-amp and 526.6 kHz as well as PM is 46.87° for the third op-amp. Application: The second and third op-amp are suitable for: •

Ultra-long-life battery-powered applications.



Power metering. 107



Instrumentation and sensing technology.



Electrochemical and gas sensors.



Pyroelectric passive infrared (PIR) detection.



Battery current sensing.



Medical instrumentation.

𝐴𝑣 = 1 +

𝑅1 𝑅2

Figure 4.39 Non-inverting op-amp

𝐴𝑣 =

𝑅1 𝑅2

Figure 4.40 Inverting op-amp circuit

circuit

Figure 4.41 Non-inverting second op-

Figure 4.42 Inverting second op-amp

amp 2.5 V (no output load)

2.5 V (no output load)

108

Figure 4.43 Non-inverting second op-

Figure 4.44 Inverting second op-amp

amp 1.8 V (no output load)

1.8 V (no output load)

Figure 4.45 Non-inverting third op-

Figure 4.46 Inverting third op-amp 2.5

amp 2.5 V (no output load)

V (no output load)

Figure 4.47 Non-inverting third op-

Figure 4.48 Inverting third op-amp

amp 1.8 V (no output load)

1.8 V (no output load)

4.8 Conclusions Miller (direct) compensation was used to improve the PM but resulted in a reduction in the UGF due to the splitting of the poles and the creation of a RHP zero that further reduced the UGF. In addition, the indirect Miller effect was utilised to adjust PM and improve the UGF, since indirect Miller eliminates the first zero as well as splitting the poles. Negative Miller compensation was chosen for extending UGF. In these works described in chapter work, two op-amp designs were introduced, analysed, implemented, fabricated and experimentally verified. The op-amps were designed utilising the AMS 0.35 µm n-well CMOS fabrication process. Both op-amp designs 109

were operated at +2.5 V and +1.8 V power supply voltage. Direct Miller, indirect Miller and negative Miller compensation techniques were presented. The second op-amp was compensated using a direct Miller capacitor and negative Miller compensation. The third op-amp was compensated using indirect Miller and negative Miller compensation. Simulation results were obtained using Cadence Spectre and showed that the second op-amp design had a significant improvement in UGF and PM. In addition, physical op-amp prototypes were tested and analysed using the Analog Arts model SF880. These also showed an improvement in the UGF and PM for the second op-amp design. Table 4.18 presents a summary of the gain, PM and UGF of the open-loop configuration. Table 4.18 Evaluation the open-loop performance of the op-amps Open-loop of the first op-amp (without load capacitance) 2.5 V

Specifications TM

1.8 V

Gain

PM

UGF

Gain

PM

UGF

(dB

(degrees)

(MHz)

(dB)

(degrees)

(kHz)

>70

> 60

22.65

80.66

70.38

16.82

77.91

73.29

214.2

Open-loop of the second op-amp (without load capacitance) TM Physical test

(RTest with CTest)

79.79

78.24

18.12

76.68

84.18

263.5

70.27

13.97

10.70

56.65

50.0

481.13

Open-loop of the third op-amp (without load capacitance) TM Physical test

(RTest with CTest)

79.74

99.48

24.23

76.68

101.06

321.9

69.75

19.04

12.50

57.45

46.87

526.6

110

Chapter 5 Operational amplifier topology alternatives

5.1 Introduction The internal structure of an operational amplifier (op-amp) is built on the concept of the performance required by the user application. In this chapter, investigations were undertaken into two topologies of an op-amp design. The rail-to-rail input/output operation amplifier topology and the fully-differential amplifier topology. Evaluation of their specific performances, for instance frequency response performance, of a rail-to-rail input/output and fully-differential op-amp were established. Moreover, this chapter proposes the use of negative Miller compensation in combination with direct and indirect Miller compensation to enhance the op-amp frequency response. The rail-to-rail input/output op-amp is presented in section 5.2. The design considers two stages of amplification. The first amplification is a complementary stage with summing circuit and the second amplification is a class-AB output stage amplifier. The complementary stage is often used to reach rail-to-rail input and improves the input common mode, as shown in section 5.3.1. In addition, the one-times current mirror is used for transconductance (gm) equalisation in the complementary stage. The op-amp is designed with negative Miller and direct Miller compensation. The fully-differential op-amp is introduced in section 5.3 and is also based on a two-stage design. The first stage is a differential input with folded cascade, and the second stage is a class-AB amplifier. The fully-differential amplifier requires the use of an additional circuit, the common-mode feedback circuit, and this is presented in section 5.3.1 along with the compensation techniques used. Both op-amp circuits were simulated using the Cadence 111

Spectre circuit simulator for undertaking AC, transient and DC analysis in evaluating DC gain, unity gain frequency (UGF), phase margin (PM), slew rate (SR), and settling time. For the fully-differential op-amp, the DC gain, unity gain frequency (UGF), and phase margin (PM) values were determined under different operating temperatures. 5.2 Rail-to-rail input-output op-amp Reducing the power supply voltage decreases the available input and output signal range of an amplifier. The rail-to-rail input/output approach allows the input commonmode range to be extended to the power supply voltage as well as the output range. This section will discuss the design of an op-amp to operate from a single rail +3.3 V and ground (GND = 0 V) power supply voltage. 5.2.1 Architecture and schematic of a rail-to-rail op-amp The rail-to-rail input/output op-amp has been used and is based on the two-stage amplifier. In this particular, the op-amp design was motivated by five main interests: 1. Rail-to-rail input to reach a suitable input common mode range. 2. Constant-gm to avoid the undesirable variations of frequency compensation. 3. Rail-to-rail output to reach a wide output swing voltage. 4. Direct Miller and negative Miller compensation enhancing the for developing frequency response with significant margin stability. 5. Connection to the bulk of the nMOS transistors in order to avoid body effect. 5.2.1.1 Design and schematic The rail-to-rail op-amp topology is shown in Figure 5.1. The block of the input nMOS differential pair is closely located with the input of the pMOS differential pair, IN- and IN+. The outputs of the differential input pairs are connected to the summing circuit. The summing circuit is a folded cascode circuit and this acts as an intermediate circuit between the input pairs and the second stage class-AB amplifier. The equalising gm circuit is connected between the differential input pairs. The negative Miller capacitors are connected around the complementary stage whilst the direct Miller capacitors are connected around the second stage. The input stage uses complementary differential pairs, pMOS input pair (MA1 and MA2) and nMOS input pair (MB1 and MB2) with connected gate terminals (Figure 5.2). The complementary input stage allows the 112

common-mode range to reach the power supply rail voltage. The disadvantage of using this sort of technique is the common input voltage is created by a varying gmTOT as described in section 3.2.4. If the gmTOT in middle of operation has been changed, the frequency compensation will change two times when the gmP and gmN are equal. The UGF is then dependent on the transconductance of the input stage. These variations can be avoided by making the gmTOT to be constant for all values of the common mode input voltage.

CNM1 CNM2

IN+

B1

Summing circuit

IN-

gm equalisation circuit

nMOS differential input pair

Cc1

B2

pMOS differential input pair

C1

C2

A1

Class-AB

Output

amplifier A2

Cc2

Complementary input stage

Figure 5.1 Block diagram of the rail-to-rail op-amp The second stage is a feed-forward class-AB control and is created by transistors M20 and M26 which are controlled by transistors M21 and M27 (Figure 5.2). The expression "feed-forward biasing" is utilised if the biasing is controlled by components in series or parallel with the signal path [59]. The output stage, however, has a drawback in that the quiescent current in the output transistors is sensitive to supply voltage variations. This problem is alleviated by using a transistor coupled AB-control stage instead. Class-AB biasing of the output stage can be achieved by setting the voltage between the transistor gate terminals. M20 is the nMOS output transistor, and it is biased by M21, M23 and M24, whilst, M27, M29 and M30 bias pMOS transistor M26. These two loops are resolved the gate-source voltage between the gates of the output transistors. The (W/L) 113

of the M20 transistor has to be three times larger than the (W/L) of the M26 transistor to compensate for the charge carrier mobility difference and to maintain the gm of the M20 and M26 transistors equal at equal currents. In this design, the bulk of each nMOS transistor is connected to the VSS (ground) node as the fabrication process is an n-well CMOS process. The bulk (body) is the p-substrate, and the source is n-type. Table 5.1 Current and voltage of transistors operation mode

MA1, MA2 MB1, MB2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M-switch M34 M35 M36

pMOS nMOS pMOS pMOS pMOS nMOS nMOS pMOS nMOS pMOS nMOS nMOS nMOS nMOS nMOS pMOS pMOS pMOS pMOS pMOS pMOS pMOS pMOS pMOS nMOS nMOS nMOS nMOS nMOS nMOS pMOS nMOS pMOS nMOS nMOS pMOS

ID (µA) -40.64 4.15 -88.77 -22.95 -22.95 22.95 22.95 -22.61 22.61 -29.87 29.87 75.33 75.33 34.69 34.69 -34.69 -34.69 -38.85 -38.85 -269 -29.61 -29.61 -23.22 -23.22 -23.22 269 5.083 5.083 22.37 22.37 22.37 15.80 -7.493 7.5 8.3 -15.80

Width (µm) 160 60 32 8.4 8.4 8.4 8.4 15.6 1.3 2.2 12.75 22.05 22.05 14.2 14.2 12.1 12.1 50 50 180 90 90 90 90 10.5 60 30 30 30 30 9.6 23 26.65 10.05 10.05 0.45

gm/ID (V-1) 20.17 26.43 8.55 8.50 8.50 13.97 13.73 7.35 5.21 3.4 13.06 11.67 11.67 14.28 14.28 8.066 8.066 13.98 13.98 11.79 16.64 16.64 14.38 17.24 13.16 11.51 24.53 24.53 16.78 20.85 7.684 10.7 18.77 22.06 21.84 1.842

114

VDS (mV) 2,179 2,04 -958.3 -909.2 -909.2 813.3 668.3 -2,433 866.8 -1,217 2,083 162.9 162.9 534.3 534.3 -531.4 -531.4 -284.6 -284.6 -1,774 -1,787 -1,787 -800.4 -756.9 -1,743 1,526 1,787 1,787 629.5 730.9 -1,94 1,631 -1,784 557.9 975.9 -1,669

Vgs (mV) -691.7 674.1 -909.2 -909.2 -909.2 813.3 668.3 -909.2 866.8 -1,217 668.3 697.2 697.2 703.9 703.9 -932.2 -932.2 -816 -816 -816 -741.3 -741.3 -800.4 -756.9 -668.3 697.2 663.2 663.2 629.5 730.9 -909.2 668.3 -711 557.9 557.9 -1.669

VDSsat (mV) -83.45 43.03 -221.1 -220.2 -220.2 110.7 105.1 245 244.3 -470.1 105.7 121.4 121.4 103.7 103.7 -231.2 -231.2 -133.2 -133.2 -162.9 -105.5 -105.5 -129.3 -99.93 -106 122.3 47.05 47.05 83.5 69.34 -241.7 130.6 -86.91 54.1 54.21 -751.6

VT (mV) -674.4 764.1 -706.6 -705.4 -705.4 716.9 567.3 -677.4 539.7 -705.8 566.2 569 569 610 610 -716.8 -716.8 -721.3 -721.3 -682.8 -684.4 -684.4 -710.6 -709.5 -565.7 567.4 717.3 717.3 568.4 710.4 -679.1 524.8 -686.9 566.3 566 -768.2

Figure 5.2 Rail-to-rail input/output op-amp schematic 115

The Body effect (or Substrate Bias Effect) denotes the change in the transistor threshold voltage (VT) with a voltage difference between the bulk and source (VBS) create a change in the width of the depletion layer. In an n-well process, the nMOS transistors share the same substrate, and the body connections of all the nMOS transistors are connected to the same voltage, typically the lowest voltage in the circuit (VSS). However, pMOS transistors are built into the n-well and can be separated physically from each other. Each well can be biased to a different voltage. To avoid the body effect for a pMOS transistor, the transistor bulk and source needs to be connected together. In this op-amp design, negative Miller and direct Miller compensation are considered. The negative Miller capacitors (CNM1) is connected between the input node IN- and node (B1) of the MB2, while CNM2 is connected between the IN+ and node B2 of the MB1 (Figure 5.2). The op-amp is compensated using the direct Miller technique. The capacitors CC1and CC2 around the output transistors, M20 and M26. The direct Miller capacitor is (CC1+CC2), and CC1 is connected between the output node and the A1 of M20. CC2 is connected between the output node and A2 of M26. 5.2.1.2 Constant-gm The constant-gm rail-to-rail input using a one-times current mirror has been used. The one-times current mirror is used to control the tail current of the nMOS input pair and the tail current of the pMOS input pair. In order to control the current between these input pairs, a transistor is called a current switch transistor is used. The principle of operation was presented in Appendix C section C.2.2. It consists of complementary input pairs and a summing circuit M12-M19. The gmTOT of the input stage is controlled by the current switch (M-switch) and one-time current mirror M34-M35. If low common-mode input voltages (Vcom) are applied to the complementary input stage, the current source (Iref) biases the pMOS input pair. If the common-mode voltage is raised to about VDD -Vsg (M36), the current switch (M-switch) uses a part of the current Iref and feeds it through the current mirror M34-M35, into the nMOS input stage. In this process, the sum of the tail currents of the input pairs is kept equal to Iref. If the common-mode input is increased, the current switch leads the entire current Iref to the current mirror of the nMOS input pair. However, the variation of the gmTOT is a function of Vcom: •

At low Vcom: only the p-channel input pair operates (MA1 and MA2). 116



At intermediate Vcom: the p-channel, as well as the n-channel input pair, operate and share the advantage.



At high Vcom: only the n-channel input pair operates (MB1 and MB2).

5.2.2 Cadence Spectre simulation results Figure 5.3 shows the circuit diagram block for the rail-to-rail op-amp. The nodes of the op-amp block are connected to the I/O pads. All simulation studies were undertaken using the Cadence Spectre circuit simulator. The op-amp was simulated using different process variations, typical model (TM), worst-case power (WP), worst-case speed (WS). In addition, Monte Carlo analysis was performed.

Figure 5.3 Rail-to-rail op-amp block connected to the I/O pads 5.2.2.1 Frequency response The process variation simulations performed on the op-amp using the typical model, worst-case power and worst-case speed are presented in Table 5.2 and Table 5.3. Table 5.2 identifies the op-amp to have a typical model operating from a 0 V to +3.3 V power supply voltage, the DC gain is 85.33 dB, the PM is 63.78° and the UGF is 271.1 MHz. In Table 5.3, the op-amp frequency response with different process variations and considering the effects of the I/O pads is presented. For the typical model, the UGF reduces to 187.4 MHz, and the PM is 45.05°. The DC gain for the typical model is 85.33 dB, 33 dB for worst-case power and 93.94 dB for worst-case speed, which are only marginally different to the results presented in Table 5.2. As presented in Figure 5.4 and Figure 5.5, the frequency response (gain and phase) are varied with process variations without I/O pads but without and with layout parasitic. 117

Table 5.2 Frequency response with process variations of and without I/O and power supply pads (VDD = +3.3 V, no output load) Without layout parasitic extraction

With layout parasitic extraction

Performance

TM

WP

WS

TM

WP

WS

DC gain (dB)

85.33

33.00

93.94

85.33

33.00

93.93

UGF (MHz)

271.1

487.5

55.56

249.6

463.5

53.12

PM (degrees)

63.62

75.44

75.51

56.32

70.33

69.12

High output voltage level (V)

3.291

3.230

3.290

3.291

3.230

3.290

Low output voltage level (mV)

1.730

135.97 3.931

1.73

135.97

3.931

Figure 5.4 Frequency response varying with process variations and without I/O and power supply pads (VDD = +3.3 V, no output load)

118

Figure 5.5 Frequency response varying with process variations and without I/O and power supply pads (VDD = +3.3 V, no output load) In Figure 5.6 and Figure 5.7, the I/O pads have only a marginal effect on DC gain, high output voltage and low output voltage level. In this part of the simulation study, the output pad delivered the only electrical load for the op-amp. Table 5.3 Summary of frequency response with process variations and with I/O and power supply pads (VDD = +3.3 V, no output load) Without layout parasitic extraction

With layout parasitic extraction

Performance

TM

WP

WS

TM

WP

WS

DC gain (dB)

85.33

33.00

93.94

85.33

33.00

93.93

UGF (MHz)

187.4

383.8

45.77

145.8

283.2

34.75

PM (degrees)

45.05

63.54

60.73

35.99

54.18

47.35

High output voltage level (V)

3.291

3.230

3.290

3.280

3.230

3.280

Low output voltage level (mV)

1.78

135.97

3.931

1.366

135.97

1.366

119

Figure 5.6 Frequency response varying with process variations with I/O and power supply pads (VDD = +3.3 V, no output load)

Figure 5.7 Frequency response varying with process variations with I/O and power supply pads (VDD = +3.3 V, no output load) Monte Carlo analysis was performed over 200 samples for DC gain, UGF and PM. The UGF in Figure 5.8 ranges between 59.1 MHz and 266 MHz. In the middle of the UGF range, 128 MHz has 28 iterations, 151 MHz also has 38 iterations, at 174 MHz has 34 120

iterations. The PM in Figure 5.9 shows variations between 40.72° to 92.12°, at 57.85° shows a good matching, about 40 iterations. While, 22 iterations for 69.27°, 80.69° and 86.41°.

Figure 5.8 Monto Carlo analysis result: no. of samples versus UGF (VDD = +3.3 V, no output load, TM)

Figure 5.9 Monto Carlo analysis result: no. of samples versus PM (VDD = +3.3 V, no output load and TM) Figure 5.10 presents the variation of gain and phase along the frequency range. The DC gain is between 30.44 dB and 98.77 dB. The op-amp design at the typical model, DC gain is 85.33 dB, PM is 63.62° and UGF is 271.1 MHz. 121

Figure 5.10 Monto Carlo of the frequency response gain (top) and phase (bottom) (VDD = +3.3 V, no output load and TM)

Table 5.4 shows the results of the simulation approach and the results focused on the frequency response using the op-amp with different output load resistances with values of 0.1 kΩ, 1 kΩ, 10 kΩ and 1 MΩ with a 0.5 pF parallel load capacitance. Figure 5.11 shows the frequency response (gain and phase) with load resistance (RL). The Bode plot has shown the gain and phase changing with 0.1 kΩ, 1 kΩ, 10 kΩ and 1 MΩ. The DC gain reduced with reducing RL, the gain is 85.27 dB, 80. 19 dB, 66.13 and 43.44 dB. Table 5.4 Open-loop op-amp characteristic with different load resistance values (simulation results using the typical model) RL (CL = 0.5 pF) Performance

0.1 kΩ

1 kΩ

10 kΩ

1 MΩ

DC Gain (dB)

43.43

66.133

80.89

85.27

Unity gain frequency (MHz)

29.91

160.10

224.5

233.6

Gain-bandwidth product (MHz)

29.52

148.52

198.7

206.5

Gain margin (dB)

22.45

-9.34

-7.22

-6.979

Phase margin (degrees)

86.07

69.70

56.82

54.68

High output voltage level (V)

1.93

3.133

3.283

3.295

Low output voltage level (mV)

1.73

1.73

1.73

1.73

122

Figure 5.11 Frequency response gain (top) and phase (bottom) (VDD = +3.3 V, with output load and TM) Table 5.5 presents the results of the simulation approach and results obtained focused on the frequency response by using the op-amp with different an output load capacitance with values of 0.1 pF, 0.5 pF and 1.0 pF. The capacitive load has an impact on the UGF and PM, which decreases with increasing load capacitance (CL). The result of the capacitive load stability issue in op-amp is a transfer function pole modelled by the load capacitance and the open-loop output impedance of the op-amp. Table 5.5 Open-loop op-amp characteristic with different load capacitance values (simulation results using the TM) Performance

No load

0.1 pF

0.5 pF

1 pF

DC gain (dB)

85.33

85.33

85.33

85.33

Unity gain frequency (MHz)

271.8

264.4

233.8

214.3

Phase margin (degrees)

63.62

61.42

46.6

49.09

Gain-bandwidth product (MHz)

206.7

206.7

206.7

206.7

High output voltage level (V)

3.298

3.298

3.298

3.298

Low output voltage level (mV)

1.73

1.73

1.73

1.73

123

This output pole increases the phase lag around the loop that decreases the PM. The load resistance has a minor impact on the op-amp performance. If the load resistance is reduced all the way down to 0 Ω, the output voltage will be limited to the short circuit value. The result is that the open-loop gain and the frequency response are decreased. 5.2.2.2 DC operating of rail-to-rail input and output The DC analysis was used for determining the common-mode input range and output voltage swing. The op-amp was used in the unity gain configuration. In Figure 5.12, the red graph shows the input voltage and the blue graph shows the output voltage. The output has been followed by the input signal from GND (0 V) and entirely to the positive rail (3.3 V). The minimum output voltage is 1.734 mV the maximum output voltage is 3.295 V.

Figure 5.12 Rail-to-rail input and output voltage (VDD = +3.3 V, no output load) Figure 5.13 presents the transconductance versus input common mode voltage. The gmN is the transconductance of the nMOS transistor differential input pair, and gmP is transconductance of the pMOS transistor differential input pair. The gmTOT is the sum of gmN and gmP. In addition, the operation is given at: •

Low Vcom is between 0 V to 1.24 V: only the p-channel input pair operates (MA1 and MA2).



Intermediate Vcom between 1.24 V to 2 V: the p-channel, as well as the nchannel input pair, operate and share the advantage of input common-mode range.

124



High Vcom between 2 V to 3.3 V: only the n-channel input pair operates (MB1 and MB2).

Figure 5.13 gmTOT versus common mode (simulation results using the TM) (VDD = +3.3 V, no output load) 5.2.2.3 Slew rate and settling time The op-amp was again simulated in unity gain configuration. The SR and settling time is defined in section 4.4.2. Figure 5.14 presents the step response where the input signal varies between 0.65 V and 2.56 V applied (around dc offset +1.65 V) to the noninverting node. The output signal has SR about 181.7 V/µs on the rising edge and 159.6 V/µs on the falling edge. In addition, the settling time is 16.24 ns at a high level and 69.15 ns at a low level.

Figure 5.14 Step response (VDD = +3.3 V, no output load) 125

5.2.2.4 Comparison with op-amp existing designs In Table 5.6, the simulated op-amp performance (TM) is compared to four reported opamp designs operating at the same power supply voltage (i.e., +3.3 V). The simulation results were obtained using BSIM3v3 transistor models, typical process values and no output load. The design combines negative Miller and direct Miller compensation and demonstrates an improvement in the frequency response at a power supply voltage (+3.3 V) using a standard 0.35 µm CMOS process. A comparison was also made with other previous op-amp designs [102, 114, 115] and [116], where these designs have been designed for particular applications. As shown in Table 5.6, the proposed op-amp has a larger static power consumption than the previous designs, but low-power was not a design constraint in this design. The power consumption increases rapidly with increased UGF [117]. The UGF achieved from the circuit is significantly higher but at the cost of reduced PM. Table 5.6 Comparison with reported rail-to-rail op-amp designs

Performance Technology (µm) Power supply (V) DC gain (dB) Load capacitance (pf) UGF (MHz) PM (degrees) High output voltage level (V) Low output voltage level (mV) Power consumption (mW)

2002 [114] 0.35 3.3 65 600 0.75 50 3.25 50

Reported work 2004 2017 [115] [102] 0.35 0.35 3.3 3.3 74.2 89.8 0.008 81.9 3.28 20 0.00055

59.5 2.72 198.7

2015 [116] 0.35 3.3 70 9.5 73 3.29 0 0.96

This work 0.35 3.3 79.5 1 214.3 49.09 3.298 1.73 2.311

5.3 Fully-differential op-amp design The two-stage fully-differential op-amp design is considered in this section. The first stage is a differential input stage including folded cascode, followed by a class-AB amplifier as the second stage. Further, the fully-differential op-amp has an additional circuit that is the common-mode feedback circuit, as described in sub-section 3.2.5. To achieve the objective of this design, the op-amp has to be fully-differential that has two outputs of which the voltages precisely change opposite to each other with respect to a 126

constant common output reference voltage. A common-mode feedback circuit is used to resolve the balance of the common-mode output. This op-amp design is characterised by: •

Fully-differential op-amp design.



Common-mode output.



Common-mode feedback circuit (CMFB) stability improvement - split bias sources.



Compensation techniques.

Figure 5.15 shows the block diagram of the fully-differential op-amp, the first stage is differential input (IN- and IN+), and the output of the first stage is connected to the folded cascode circuit. The folded cascode is provided with an input signal to the second stage which it is a differential output class-AB amplifier (Out- and Out+). The commonmode feedback circuit (CMFB) is connected between the differential output stage and the folded cascode at the specific node Vcont. In addition, the CMFB is connected to the voltage source by VCMRef. The CNM1 CNM2 are negative Miller capacitors while CIN1 and CIN2 are indirect Miller capacitors

CNM1

IN+

+

-

1st stage IN-

CIN1

-

Folded

nd

2 stage

cascode

+

Out –

IN1

IN2

Out +

CIN2

CNM2

Indirect compensation

Negative Miller compensation

Vcont CMFB VCMRef

Figure 5.15 Block diagram of a fully-differential amplifier

127

5.3.1 Architecture and schematic of a fully-differential op-amp 5.3.1.1 Design implementation This section provides an analysis of the conventional fully-differential folded-cascode structure whose circuit schematic is presented in Figure 5.16. The folded-cascode provides a large DC gain from a single amplification stage. Maximizing DC gain is achieved by creating a high-output impedance (output of the first stage). The foldedcascode op-amp design utilises cascode transistors of opposite type from those used in the input stage [42] and the full schematic is shown in Figure 5.16. In this work, transistors M1 and M2 are pMOS whereas the cascode transistors M9 and M10 are nMOS transistors. This type of connection provides a high resistance output node and the transconductance for the cascode is also nearly equal to the transconductance of the input pair [37]: gm

Kp W = √2ID ( ) ( ) 2 L

gm2 W⁄L = ( ) ID 2 Kp 2

(5.1)

(5.2)

Where kP is the transconductance parameter of the input stage transistor, ID is the current flow through the input stage, and W/L is the ratio of the input device width (W) and length (L). The theoretical formula for the UGF in equation (5.1) is used to improve the UGF by increasing gm. Increasing gm is achieved by increasing the input transistor dimensions (W/L) (as shown in equation (5.2)). This also coincides with the increase of the transistor parasitic capacitance values. It is, however, desirable to reduce the influence of parasitic capacitances of the input stage while maintaining a high amplifier transconductance. A folded-cascode stage can be placed directly on the output of the input pair [59], the transistors M7 and M8 summing the differential currents of the input transistors, A high current results in a large transconductance. In addition, this provides the highest possible high frequency response as the gate capacitors of the nMOS transistors (M7 and M8) are smaller than that of the pMOS transistors. The pMOS transistors are usually chosen to be three times larger in order to compensate the gm for the lower hole mobility in the pMOS transistor channel [59]. A disadvantage

128

Figure 5.16 Schematic of the fully-differential op-amp 129

of the folded cascode is that it has two extra current legs and, therefore, doubles the power consumption. In addition, the folded cascode stage also has more devices, which contribute significant input referred thermal noise to the signal [118]. The output stages are identified by transistors M16, M17 (positive node) and M32, M33 (negative node) in Figure 5.16. The output is feed-forward biased in class-AB by a mesh of head-to-tail connected transistors M21, M22. The criteria utilised in the choice of the class-AB output stage implementation were [119]: •

A straightforward and high-speed design.



No complex active or amplifier feedback paths in the class-AB control circuitry.



Low-VDD operation.



Good power supply rejection ratio.



No direct dependence on supply voltage for bias current setup.



less noise or offset to be added to the first stage of the amplifier.

The schematic in Figure 5.17 shows the implementation of the class-AB output stage integrated together with the first gain stage. The output signals of the first stage are supplied to the output stage at nodes PV and NV.

Figure 5.17 Half circuit of the op-amp showing the class-AB output stage In typical circuit operation, M16 and M17 are biased in the conducting state (saturation). The voltages at nodes PV and NV are created to minimise the quiescent current through 130

the large output driver devices, M16 and M17. This biasing arrangement is established within two translinear loops. The loop that biases M16 consists of M25, M27, M21, and M16. Likewise, M17 is biased by the loop consisting of M18, M15, M22, and M17. A common-mode feedback circuit is shown in Figure 5.18. In this circuit, normally the reference voltage VCMRef is equal to half of the supply voltage.

Figure 5.18 Common-mode feedback circuit 5.3.1.2 Compensation Theoretically, the transconductance is used to improve the UGF by increasing gm. However, increasing gm is also achieved by increasing the input transistor dimensions (W/L) which increases the parasitic capacitances associated with the input transistors. To reduce this effect, negative Miller and indirect Miller compensation are intoduced combination. Negative Miller capacitance is selected to be around the differential input stage. CNM1 is connected around non-inverting input while the CNM2 is around inverting input node. To extend the UGF, indirect Miller compensation is used around class-AB output stage in order to improve the margins of stability. CIN1 is connected between the output node and the gate of the M16 (pMOS transistor) while CIN2 is connected between the output node and the gate of the M17 (nMOS transistor) as shown in Figure 5.17. 5.3.2 Cadence Spectre simulation results The circuit diagram block for the fully-differential op-amp is shown in Figure 5.19. The ports of the op-amp block are connected to the I/O pads. The simulation study was 131

performed using typical model process transistor models and was undertaken using the Cadence Spectre circuit simulator. The op-amp was simulated using different process variations, the typical model, worst-case power (WP), worst-case speed (WS). In addition, a Monte Carlo analysis was performed.

Figure 5.19 Fully-differential op-amp block connected to the I/O pads 5.3.2.1 Frequency response The op-amp was designed to operate on a +3.3 V single rail power supply voltage. Table 5.7 shows the frequency response analysis of the design based on typical device models. The design was simulated with no-load capacitance and load capacitances (CL) of 0.1 pF, 0.5 pF and 1 pF. The capacitive load does not have an effect on the DC gain (84.9 dB). However, the load capacitance effect is noticeable as the signal frequency increases as shown in Figure 5.20. At high frequency, the UGF varies from 707.97 MHz down to 505.23 MHz. In addition, the PM decreases with an increase in load capacitance value from the 77.90° down to 21.17°. Note that with this op-amp design approach, the PM reduces to below the considered minimum preferred value of 45° as the load capacitance increases. The other significant parameter is a gain-bandwidth product (GBP) is seen to be almost constant. The op-amp design was then simulated at the process boundaries using the worst-case speed and worst-case power device models. The typical model means the nMOS and pMOS transistors have normal speed, worst-case speed means slow nMOS and slow pMOS transistors, and worst-case power means fast nMOS and fast pMOS transistors. Table 5.8 summarises the frequency response and stability margins achieved with the different process variation models. 132

Table 5.7 Open-loop frequency response (TM) Load capacitance

No load

0.1 pF

0.5 pF

1 pF

DC gain (dB)

84.9

84.9

84.9

84.9

UGF (MHz)

707.97

693.03

588.04

505.23

PM (degrees)

77.90

65.38

28.91

21.17

GBP (MHz)

543.90

453.83

543.54

543.18

Figure 5.20 Open-loop frequency response for different load conditions (top) gain magnitude and (bottom) phase

Table 5.8 Frequency response with process variations (VDD = +3.3 V, no output load) Process

TM

WP

WS

DC gain (dB)

84.90

58.43

86.12

UGF(MHz)

707.97

2,146

143.1

PM (degrees)

77.90

44.74

85.77

GBP (MHz)

543.90

2,194

122.6

133

5.3.2.2 Frequency response versus temperature Over the temperature range from -40 °C to 125 °C, and with all circuit operating conditions, it can be seen that the temperature has a large influence on the circuit operation and hence changes the op-amp frequency response. Firstly, the operating temperature affects the frequency behaviour of the open-loop gain magnitude curve, Figure 5.21.

Figure 5.21 Open-loop gain versus temperature (VDD = +3.3 V, no output load) As the temperature varies, the open-loop gain magnitude varies between 84.9 dB and 50.71 dB in the typical model, worst-case power between 72.46 dB and 21.07 dB and the worst-case speed between 88.26 and 61.38 dB. The UGF is shown in Figure 5.22. It also changes with temperature. For the typical model, the UGF varies between 395 MHz and 465 MHz. Moreover, for worst-case speed, it varies between 31.1 MHz and 193 MHz. For worst-case power, the UGF varies between 2.56 GHz and 621 MHz. Over the temperature range between -40 °C and 125 °C, as in shown in Figure 5.23, the PM initially reduces as the temperature is increased from the minimum value, However, as the temperature increases further, the PMs for the typical and worst-case power models change in the reverse direction (increase instead of decrease). In the typical model case, the phase varies from 77.1° down to 62° and in the worst-case speed between 96.22° and 70.75°, but in the worst-case power, the PM increases with increasing temperature from 49.13° to 82.64°.

134

Figure 5.22 UGF versus temperature (VDD = +3.3 V, no output load)

Figure 5.23 PM versus temperature (VDD = +3.3 V, no output load) 5.4 Analysis and discussions The two op-amp topologies in this chapter were created using the AMS 0.35 µm fabrication process at single power supply of +3.3 V. The rail-to-rail input/output opamp design presents a suitable UGF and PM since negative Miller compensation is considered to extend the UGF value. In addition, the UGF and PM show improvement in the case of fully-differential op-amp. However, this design does not show any significant improvement in PM when the load capacitance is used and it is necessary 135

for the load capacitance to be about two times larger than the indirect Miller capacitance in order to ensure the stability of the op-amp when using negative Miller compensation. This technique offers the advantage of improvement in UGF by the op-amp in a twostage amplifier since the two-stage amplifier is a simple circuit compared to the three or four stages and this is appreciated for avoiding complicated circuitry. The other advantage is the layout of the two-stage op-amp, which is smaller than the layout of three or four stages and this provides an opportunity to avoid the complex circuit. 5.5 Conclusions In this chapter, two op-amp topologies were presented and simulated that combined compensation techniques. Firstly, a two-stage rail-to-rail input/output op-amp that combines negative Miller and direct Miller compensation was presented. The compensation techniques were used to increase the frequency response and stability with regard to PM, UGF, GPB and GM. A rail-to-rail input/output design was a requirement in particular for this op-amp. The input stage was created on the constant-gm circuit utilising a one-times current mirror. In addition, a class-AB output stage was used in order to increase the output signal swing. The design performance was simulated using three different process models (typical, worst-case power and worst-case speed) to identify the performance of the opamp with process variations and different output load requirements. Secondly, a fully-differential two-stage op-amp design was created based on a foldedcascode input and class-AB amplifier output. The design was considered with the aim to control the op-amp frequency response and stability based on a combination of negative Miller compensation and indirect Miller compensation. The design was simulated using three different process models (typical, worst-case power and worstcase speed) with identify the performance of the op-amp with temperature.

136

Chapter 6 Digitally programmable operational amplifier design and simulation

6.1 Introduction The majority of analogue op-amp circuits designed today have a fixed functionality in that their performance, or performance range, is fixed by the designer at the time that the design is created. This differs from many digital electronic circuits that are programmable, or configurable, using software programming. The programmability of op-amp analogue circuits has been implemented successfully to specific applications. In the case of op-amp circuits with programmable closed-loop gain and it is dominant, amplifier gain control is obtained using external feedback resistors [120-122] which can be either discrete (external to the op-amp package) or integrated (internal, on the same die as the op-amp circuit). In this chapter, two techniques to control the open-loop configuration have been considered. To control the DC gain, unity gain frequency (UGF) and phase margin (PM) of the op-amp are presented. The op-amp open-loop characteristics are adjusted and hence the margin of stability of the op-amp in closed-loop configuration is adjusted. Although the op-amp has a range of DC, transient and frequency response characteristics that change with a change in the tail current, specifically in this design the DC gain and PM were of primary concern. Section 6.2 will present a digitally programmable analogue design. Section 6.3 presents a different technique to design a programmable bandwidth only of single-ended output CMOS operational amplifier (op-amp) using a serial digital interface. The topology was developed to enable the programming of the value of a negative Miller capacitance and

137

the value of a direct Miller capacitance. Therefore, a controllable frequency response op-amp is created that can be digitally controlled from a host digital processor. The purpose of section 6.4 is to permit for the op-amp DC gain and frequency response to be controlled. This is attained by programming the transistor tail current in the differential input stage of the op-amp. Serial peripheral interface (SPI) communications was used here to provide control of the op-amp from an external digital host processor. Both designs are based on a rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and folded-cascode circuits, and the second stage is a class-AB amplifier. In addition, the analogue and digital power supply is +3.3 V and hence, all circuitry operates on the same power supply level, although provided from separate power supply inputs in order to reduce the potential of introducing noise onto the analogue signals from any fast changing digital signals. 6.2 Digitally programmable analogue Electronic circuits can be classified as being analogue, digital or mixed-signal (mixedmode) where certain design performance can be attained, and individual design procedures are followed to create a working design. Fundamentally, all circuits are analogue, but digital design techniques allow for the analogue behaviour to be abstracted into digital signals where working in the digital domain allows for the creation of behaviour not possible in analogue (such as non-linear control algorithms [123]). Mixed-signal combines both analogue and digital circuits into a single design, such as in the analogue-to-digital converter (ADC). Many analogue designs have a functionality fixed at the time the design is created and so the circuit cannot be altered once fabricated. However, many digital designs are programmable and this allows for the design to be programmed and re-programmed to target different design operation scenarios. However, it is possible to create digitally programmable analogue circuits that can be programmed and reprogrammed. A range of digitally programmable analogue circuits have been successfully designed and deployed. This section identifies and discusses different designs that have been deployed and the purpose of the programmability.

138

6.2.1 Circuit performance alteration A key reason for programmability is to alter circuit performance. This can be used to enhance the characteristics of the circuit for specific applications or to ensure that the design operates correctly under all possible operating conditions. An example of correct operation would be to ensure that an op-amp has the correct margins of stability [123] when used in a closed-loop configuration with negative feedback. Instability would occur when the op-amp is used to create an amplifier or filter circuit but rather than acting as an amplifier/filter, under certain conditions the circuit becomes unstable and acts as an oscillator. This condition should therefore never arise if the circuit is designed correctly. 6.2.2 Op-amp performance alteration Op-amps are high-gain differential input voltage amplifiers which have certain ideal characteristics when used with external feedback components (such as resistors, capacitors and inductors), and can form the basis a wide range of linear and non-linear circuits. The op-amp is widely used in electronic circuits due to these features, but real op-amp implementations are required to be designed in order to attain suitable non-ideal characteristics since the ideal case cannot be attained. Many op-amp designs are fixedfunctionality in that they cannot be programmed to alter their characteristics. Other opamps can be programmed by varying bias currents using external resistors [124] or by controlling their margin of stability using external capacitors. Most op-amps include an internal compensation capacitor which has a value that ensures the op-amp cannot become closed-loop unstable. Some op-amps however do not include an internal compensation capacitor and the designer is free to include an external capacitor if required. Other amplifier designs can have their voltage gain controlled using a programmable resistor [125]. 6.2.3 Field programmable analogue array The field programmable analog array (FPAA) is a mixed-signal design that consists of an array of programmable analogue cells [126]. These devices can be digitally programmed to implement linear and non-linear op-amp based circuits. As these circuits require the use of integrated capacitors and resistors, where integrated resistor values are difficult to produce and are physically large, hence expensive accurately, the resistor 139

function is realised using switched capacitor (SC) circuits [127]. An example of the FPAA is the AN120E04 Reconfigurable FPAA [128] from AnadigmTM based on switched-capacitor technology. 6.2.4 Design for testability and built-in self-test In addition to supporting design performance alteration, reprogramming the operation of an electronic circuit design can be undertaken to enhance the testability of an analogue or mixed-signal circuit. It is known that electronic circuits, and in particular microelectronic circuits, designs can be complicated to effectively test once fabricated due to design complexity (size of the design), increasing design operating frequencies and cost. It is therefore currently common practice to include design for testability (DfT) and built-in self-test (BIST) circuitry into a design to enhance the testability (basically the idea of increasing the controllability and observability of circuit nodes within a design). While it is common for digital circuits and systems to include DfT and BIST features, it is not so common for analogue and mixed-signal circuits. This is in part to the increased digitalisation of electronic circuits, a focus in design and fabrication on digital (driven by the microprocessor, memory, communications and multimedia application areas), but in part due to the complexity of incorporating DfT/BIST in analogue. However, specific analogue and mixed-signal DfT features exist such as the swop-amp [129] from Bratt et al, and the IEEE standard 1149.4 (IEEE Std 1149.4™2010 (Revision of IEEE Std 1149.4-1999)) [130]. 6.2.5 Mixed-signal programmable system on a chip The Programmable System-on-a-Chip (pSoC) [131] is a programmable (configurable) device consisting of a CPU (central processing unit) core and mixed-signal arrays (analogue and digital arrays). In addition, integrated memory (I/O registers, SRAM (static random access memory) and Flash memory blocks) provide the memory types and capacities to implement a range of MCU applications. The analogue arrays implement op-amp and switched-capacitor circuits that intern enable functions such as data converters, amplifiers, instrumentation amplifiers, filters, current drive output circuits and comparators to be created. For example, the PSoC™ Mixed-Signal Array family from Cypress Semiconductor [132] provide such capability. The concept behind

140

this family of devices is to replace multiple MCU (microcontroller unit) devices and peripherals with a single programmable device. 6.3 Programmable bandwidth op-amp with negative Miller compensation The op-amp design considered in this section is based on the rail-to-rail output (CMOS) op-amp architecture where the first stage of the op-amp consists of differential input and folded-cascode circuits, and the second stage is a class-AB output stage. Negative Miller capacitance is implemented around the first stage as it is a differential input stage with a differential output. Miller capacitance is applied around the second stage that has a differential input and single-ended output. In addition, a switchable compensation capacitor op-amp is considered and the architecture of this design is shown in Figure 6.1.

+

Figure 6.1 Programmable feedback capacitances around the first amplification stage (negative Miller compensation) and the second amplification stage (Miller compensation) This consists of the two amplification stages with each stage including a switchable capacitor section. The capacitor array is created using parallel connections of capacitors and based on the direct Miller and the negative Miller compensation architectures. Each programmable capacitor is connected or disconnected (switch is ON or OFF) from the circuit using a single analogue switch control bit per capacitor pair (SAn and SBn) as presented in Figure 6.1. As the analogue switch is not a perfect switch (e.g., it has ON and OFF resistances which vary with the size of the switch transistors and signal 141

voltage), the switch must be suitably sized by trading off its finite ON resistance with its non-linear characteristic [133]. The capacitor arrays are connected to the stage input and output nodes by selecting a suitable switch control code (0 = switch OPEN and 1 = switch CLOSED). 6.3.1 Analog sub-system The analogue sub-system consists of a two-stage CMOS op-amp operating on a single rail +3.3 V power supply, as shown in Figure 6.1, with its associated capacitor and switch arrays which are used to create negative Miller capacitance around the first stage and direct Miller capacitance around the second stage. The op-amp schematic, excluding the compensation capacitors, switches and digital control logic is shown in Figure 6.2. 6.3.1.1 Op-amp design A two-stage topology is often used to achieve both the required gain and UGF. For a two-stage op-amp, as shown in Figure 6.2, the first stage is designed using a foldedcascode topology to provide the high gain and minimise the power consumption. The first stage input is connected to its output by the negative Miller capacitor. The second stage was designed to allow a large output swing. A class-AB amplifier with a pushpull output contains the key part of the op-amp. The class-AB amplifier must have a high input signal range to receive the signal from the previous stage [134]. In order to amplify the input signal, the class-AB amplifier must also have a high output voltage swing. The Miller compensation capacitors stabilise the second stage of the op-amp design. 6.3.1.2 Op-amp frequency compensation When considering the stability of the two-stage CMOS op-amp without frequency compensation, it is usually unstable in a unity feedback arrangement. Utilizing magnitude and phase information, techniques to compensate the op-amp must therefore be included [90]. The op-amp then contains an additional capacitance connected between the input and the output nodes of the second stage and this is known as the Miller compensation capacitance (Figure 6.1).

142

Figure 6.2 Programmable bandwidth op-amp with negative Miller schematic 143

Compensation methods have been explored in order to increase op-amp bandwidth whilst maintaining a suitable PM. The other compensation technique is called negative Miller compensation. The negative Miller compensation technique is used to extend the UGF and increase speed and is usually applied for frequency stabilization. The negative Miller and direct Miller have the same principle of operation, but the difference is in the way the feedback capacitors are connected [92, 135] as shown in Figure 6.1 and described in section 3.4. However, the programmable negative Miller capacitance is presented in Figure 6.3.

Figure 6.3 Negative Miller capacitance array (Cadence Virtuoso schematic) The negative Miller capacitor is connected to an analogue switch in order to control the value of capacitance. In this design, each capacitor was divided into two equal size capacitors since the op-amp has two inputs. The values of the capacitor were 0.4 pF, 0.8 pF, 1.2 pF and 1.6 pF and the associated analogue switches were S3, S2, S1, and S0, respectively. In Figure 6.4, the direct Miller capacitor is also connected to an analogue switch in order to control the value of capacitance. At this time, each capacitor was also divided into two equal valued capacitors. The values of the capacitor were 0.4 pF, 0.8 pF, 1.2 pF and 1.6 pF and the associated analogue switches were S4, S5, S6, and S7, respectively.

144

Figure 6.4 Direct Miller capacitance array schematic In this design, each amplification stage consists of four capacitor values, where two equal value capacitors are required to implement a particular value due to the differential signals in the circuit. Table 6.1 shows the negative Miller capacitor values used and their corresponding switch control signals. Table 6.2 shows the Miller capacitor values used and their corresponding switch control signals. These were chosen in increments of 0.2 pF and the absolute values chosen to be representative of typical capacitor values used and which can be fabricated in CMOS technology. Table 6.1 Negative Miller capacitor values and analogue switch control signals Negative Miller capacitor value SA3 SA2 SA1 SA0 0 pF (no compensation)

0

0

0

0

0.4 pF

0

0

0

1

0.8 pF

0

0

1

0

1.2 pF

0

1

0

0

1.6 pF

1

0

0

0

145

Table 6.2 Direct Miller capacitor values and analogue switch control signals Miller capacitor value

SB3 SB2 SB1 SB0

0 pF (no compensation) 0

0

0

0

0.4 pF

0

0

0

1

0.8 pF

0

0

1

0

1.2 pF

0

1

0

0

1.6 pF

1

0

0

0

6.3.1.3 Analogue switches The analogue switch is implemented in CMOS using a CMOS transmission gate (TG) [136] as shown in Figure 6.5. Each switch uses an nMOS and pMOS transistor with minimal gate length (i.e., 0.35 µm) and a transistor width set according to the required ON resistance of the switch. The logical value controls the switch connections between A and B of the ON/OFF control input signal. With this type of solid-state switch, the ON resistance is dependent on the transistor sizes and the value of the applied voltage. The ON resistance varies with the applied voltage with the resistance versus switch voltage of the shape shown in Figure 6.5. This resistance is non-zero, varies with switch input voltage (considering node A as the input signal node and the voltage is applied between A and is a maximum when the switch voltage is between GND and VDD. In addition, switch capacitance and charge injection issues arise if the switch is to be used in a dynamic switching arrangement as is be seen in switched capacitor circuits. However, here charge injection would not be an issue as the switches are set prior to use and so the switching arrangement is static.

Figure 6.5 Analog switch (transmission gate) and resistance versus voltage profile

146

6.3.2 Digital sub-system The principle of operation of the digital sub-system is shown in Figure 6.6. The digital logic is contained in the serial peripheral interface, SPI communications, and this is used to control the analogue switches contained in the capacitor arrays.

Figure 6.6 Host processor to op-amp digital interface 6.3.2.1 SPI communications The op-amp is digitally controlled by a host processor through a simple serial peripheral interface (SPI) [137]. This simple synchronous interface is suited for communications across short distances and is widely used in serial data communications between ICs on a printed circuit board (PCB). It requires only four pins (i.e., SCK, MOSI, MISO and SSn) where the op-amp here acts as the slave and a host digital processor acts as the master. SPI provides a standard way in which a host processor can update the feedback capacitor array settings using a +3.3 V level interface. Here, the host processor will provide an 8-bit code which represents the capacitor switch settings. These codes are stored in the internal SPI communications circuit register that is updated on the falling edge of the eighth SCK clock signal. The interface consists of four digital inputs (three outputs from the host processor for SPI and a master, active low reset) and one digital output (SPI input to the host) as shown in Figure 6.7.a. An asynchronous active low reset (ResetN) signal is a master reset signal to reset all the internal registers within the SPI communications circuit. This is provided for either a power-on master reset or host reset if required in order to set the 147

op-amp into a default feedback arrangement (i.e., no feedback capacitors connected). If a reset signal is not required, it can be left unconnected as the ResetN pin is provided with an “on-chip” internal pull-up. The timing of the control signals is shown in Figure 6.7 b. Loading of the capacitor array analogue switch settings (d7 … d0) is performed on the rising edge of SCK using the MOSI signal once SSn has been asserted low. MOSI will be set before the rising edge of SCK in order to avoid timing issues.

Figure 6.7 SPI and ResetN signal timing For simplicity, the MOSI can change on the falling edge of SSn and SCK. Once the eight switch values have been loaded into the SPI communications circuit, the switch settings are changed at once on the falling edge of the eighth SCK signal. When the MOSI values are loaded into the circuit, the previously stored values are also made available on MISO and change on the falling edge of SCK. The state machine within the SPI communications circuit is set-up so that it would only operate when SSn is low and so would not react to any changes on SCK when SSn is high. In Figure 6.7, dx-1 refers to the last value of dx and dx-2 refers to the version of dx before the last version where x refers to bit 7 … 0. Although these values exist, it would be the user who decides what values to read and use. The signals d7 … d0 connect to the analogue switch control signals for SA3 … SA0 and SB3 … SB0. 6.3.2.2 SPI communications shift register Within the SPI communications circuit (Figure 6.8), a shift register is used to load the switch control signals d7 … d0 into the internal logic on the rising edge of the first eight clock pulses of SCK. On the falling edge of the eighth pulse of SCK, the switch control signals are loaded into an 8-bit register which updates the eight control signals at one 148

time. In the digital design, the shift register is a flip-flops [138] which share the same clock. In addition, the output of each flip-flop is associated to the input of the following flip-flop in the chain.

Figure 6.8 SPI interface communication schematic design schematic That means the output from one flip-flop becomes the input of the next flip-flop, producing in a circuit that shifts by one position at each change of the clock input. The input and output of shift registers can have both parallel and serial inputs and outputs. These are often formed as the serial-in serial-out shift register (SISO), the serial-inparallel-out shift register (SIPO), the parallel-in-serial-out shift register (PISO) and parallel-in parallel-out shift register (PIPO). In this design, the SIPO is used to load the serial data from the MOSI signal to form an internal value and the PIPO is used to update and hold the switch control signals d7 … d0. 6.3.2.3 Capacitor switches The CMOS transmission gate (TG) consists of one nMOS transistor and one pMOS transistor connected in parallel. These transistors require a suitable gate voltage in order to operate the switch. The nMOS transistor requires a high voltage to CLOSE and the pMOS transistor requires the complement (i.e., a low-voltage) to CLOSE. The complement signal is created using a static CMOS logic inverter. The particular TG operates as a switch with contacts between terminals A and B, as shown in Figure 6.5. 149

The ON/OFF control signal CLOSEs the switch when it is a logic 1 (gate voltage = high voltage = VDD = +3.3 V) and OPENs the switch when it is a logic 0 (gate voltage = lowvoltage = GND = 0 V). 6.3.3 Simulation results Figure 6.9 shows the schematic of the programmable op-amp. The SPI communications is considered as the connection between the host processor and the op-amp. The input signals of SPI is loaded by SSn, SCK, MOSI and ResetN. The outputs S0, S1, S2, S3, S4, S5, S6 and S7 are designed to connect to the capacitance array. In addition, the capacitance array is designed to the op-amp which capacitance array is negative Miller capacitors and direct Miller capacitors. In order to verify the operation of the design and to assess the effect of introducing the capacitor switches on the circuit performance, the analogue performance of the design was simulated using the Cadence Spectre circuit simulator [139]. As this mixed-signal design consists of analogue and digital parts, the following simulation approach was undertaken: 1. The analogue circuit operation of the op-amp, capacitors and switches were simulated using Spectre. This was a comprehensive set of tests undertaken to determine the frequency response of the amplifier in different circuit configurations. 2. The digital circuit (SPI communications circuit) operation was initially logically simulated using a Verilog-HDL (hardware description language) test fixture and then the analogue circuit operation was simulated with Spectre. As the digital part requires a long simulation time to simulate the circuit using an analogue simulator, a comprehensive set of tests was undertaken using the Verilog-HDL test fixture and a more straightforward set of tests was undertaken using the Spectre simulator. 3. The analogue and digital parts were combined, and the overall circuit was simulated using a transient analysis.

150

Figure 6.9 Programmable op-amp design schematic schematic For the op-amp frequency response, the Miller and negative Miller capacitors were set to various values and the op-amp performance simulated using an AC analysis. For this study, both capacitor arrays were set to the same values of 0.4 pF, 0.8 pF, 1.2 pF and 1.6 pF. However, the two arrays are independent and so different combinations of capacitor values are possible with sixteen possible combinations of capacitance in each array. For the chosen capacitor values, Figure 6.10 shows the AC analysis results. For each capacitor switch setting, a simulation study was also performed on the op-amp circuit with fixed capacitor values and no switch elements. This enabled the effect of the switch resistance to be considered.

Figure 6.10 Simulated frequency response (VDD = +3.3 V, no output load and TM) 151

Table 6.3 shows the comparison of the op-amp circuit with switched value capacitors and the op-amp circuit with fixed value (no switches) capacitors. For the final selected switch transistor sizes, the switches have an impact on the PM (Figure 6.11), UGF (Figure 6.12) and GM (Figure 6.13) for each set capacitor value and dependent on the capacitor values used. Table 6.3 Comparison of op-amp performance using capacitors only and the capacitors with switches (VDD = +3.3 V, no output load and TM) Design without switches

Design with switches

Capacitor value (pF)

PM (degrees)

UGF (MHz)

GM (dB)

PM (degrees)

UGF (MHz)

GM (dB)

0.2

57.37

290.8

-8.856

57.47

295.7

-9.532

0.4

74.04

166.3

-11.94

78.87

170.1

-14.54

0.6

81.09

118.7

-13.33

87.81

120.6

-17.53

0.8

84.87

90.88

-14.11

91.53

92.53

-19.53

Table 6.4 identifies the percentage error introduced in each selected AC performance parameter. Note that the capacitor values identified in the table are the same value for the Miller and negative Miller capacitors. For the selected op-amp architecture, capacitor values and switch sizes used, selecting different Miller and negative Miller capacitor values showed that the PM, UGF and GM could be controlled. In addition, although the introduction of the switches changed the performance of the circuit, the errors introduced when compared to a non-switched and fixed capacitor value design were identifiable and controllable. Table 6.4 Errors introduced by switches (VDD = +3.3 V, no output load and TM) Error (%) magnitude Capacitance value (pF) 0.2

PM 0.17

UGF 1.69

GM 7.63

0.4

6.52

0.61

21.78

0.6

8.29

1.60

31.51

0.8

7.85

1.82

38.41

152

Figure 6.11 PM versus compensation capacitive (VDD = +3.3 V, no output load and TM)

Figure 6.12 UGF versus compensation capacitive (VDD = +3.3 V, no output load and TM)

Figure 6.13 GM versus compensation capacitive (VDD = +3.3 V, no output load and TM) 153

Figure 6.14 shows an example of the operation programmable bandwidth op-amp. In this example test, the SPI data is loaded in order to activate d0 and d7 (d0 for negative Miller capacitor) and d7 for direct Miller capacitor). The operation of op-amp 1. Before the loading the code is (00000000) and the op-amp is unstable. 2. After loading the code (10000001), the op-amp normal operation commenced and develops a phase shift between the input and output signals.

Figure 6.14 Operation of the programmable bandwidth op-amp (VDD = +3.3 V, no output load and TM) 6.4 Programmable gain/bandwidth op-amp design basis at tail current For this op-amp design, the design has combined the two functions of the programmable gain amplifier and the programmable bandwidth amplifier. In the proposed approach, a controllable differential input stage tail current allows the control of both parameters by using different dimension size (width/length (W/L) ratio) MOS transistors and analogue switches. The MOS transistors set the input stage current level. The digitally controlled analogue switches are used to select the required tail current from a host digital 154

processor. The op-amp consists two-stages of amplification. The first stage is a differential input stage and supported using a folded-cascode circuit. The second stage is the class-AB output stage that it is used for achieving rail-to-rail output (Figure 6.15). Feedback (compensation) capacitance surrounds the first stage and this is called negative Miller compensation (CNM). Negative Miller compensation can reduce the effective magnitude of the differential input stage transistor capacitance. It is employed in this design to improve the UGF. The direct Miller capacitance is connected around the second stage and this is used to improve the margin of stability. The transistor is disconnected or connected (switch is OFF or ON) from the circuit using a single analogue switch control bit (Sn) per MOS transistor. As the analogue switch is not a perfect switch (it has finite OFF and ON resistances that vary with the size of the switch transistors and signal voltage), the switch must be suitably sized by trading off its’ finite ON resistance with its’ non-linear characteristic [140]. The transistor array relates to a suitable switch control code (0 = ON and 1 = OFF).

Figure 6.15 Structure of the programmable op-amp 6.4.1 Op-amp design The two-stage CMOS amplifier architecture has been considered. The op-amp schematic is shown in Figure 6.16. The op-amp input is a differential stage followed by a folded-cascode and a class-AB output stage. The first compensation capacitor (CNM) is connected around the first stage forming negative Miller compensation. The second compensation capacitor (Cc) is connected around the second stage forming direct Miller compensation. These techniques are used for improving the stability (direct Miller) and 155

frequency response (negative Miller). The op-amp design was created using the transconductance-drain current ratio (gm/ID) design technique suited low-power and low-voltage analogue circuits [141]. Using the basic op-amp design, the tail current transistors and analogue switches (transmission gates) are then added (referring to Figure 6.17) in order to allow for the selection of the required open-loop characteristics. For this particular op-amp implementation, the key design parameters were: •

Two-stage planning with a differential input and folded-cascode first stage and class-AB second stage.



Single rail +3.3 V operation.



Open-loop PM of greater than 60° with stage gain and Miller capacitance values based on a two-pole system assumption (based on simplified equations for (4.1), (4.2), (4.3) and (4.4)). The tail current design value was 90 µA based on a tail current transistor size of 30 µm gate width and 0.35 µm gate length.



DC gain > 70 dB.



Design specification verification based on typical process model simulation studies.



Input transistors are operating in saturation and weak inversion.

6.4.1.1 Tail current A typical differential input amplifier is formed from at least two matching MOS transistors, organised with the MOS transistors connected in parallel and sharing the same source connection. A source combined pair is a pair of transistors where the shared source terminal current is provided from a more or less constant current source. In Figure 6.18, a pMOS input stage is shown with a resistor/current source combination (left) that represents a MOS transistor current source (right). Ideally, a large value resistor (RTail in Figure 6.18) connected to the positive supply would be required (left). The higher the resistance of the current source, the lower the common mode gain and the better the common mode rejection ratio (CMRR) [142]. A simple design considers the component connected between VDD and the transistor common source connection as a single high-value resistance. In more typical designs, an active constant current source replaces this high-value resistance. With two inputs, this forms the differential input amplifier stage.

156

Figure 6.16 Programmable gain/ bandwidth op-amp design schematic 157

Figure 6.17 Selectable transistors to adjust the tail current The two transistor gate nodes form the amplifier input that is differentially amplified by the transistor pair (Figure 6.18). Therefore, the requirement of the MOS transistor of the tail current is a high output impedance and high drain-source voltage (Vsd(sat)) [143, 144]. The current that flows through the transistor can be approximated by: ITAIL = (

kp W 2 ) ( ) ( Vsg − |VT |) (1 + λVsd ) 2 L

(6.1)

Here, kP is transistor transconductance, W and L are the transistor width and length, Vsg is the source-gate voltage and VT is the transistor threshold voltage (approximately -0.5 V for a pMOS transistor with this 0.35 µm CMOS technology), Vsd is source-drain voltage and λ is channel-length modulation. The drain current through the transistor is dependent on the transistor width with the transistor operating in the saturation region (low gm/ID value). However, the transistor tail current is possible to control by using a number of transistors connected in parallel. Figure 6.17 shows a 5-bit digitallyprogrammed current circuit. The value of the current is based on the transistor dimensions according to the transistor operated in the saturation region. As a result, this technique can be used to control the op-amp UGF. Strong inversion region transistor operation requires an increased tail current to achieve a given level of transconductance. gm increases directly with input device drain current, that is given by [37]: g m1 =

2 ID1 (Vsg − |VT| )

=

I 2 ( Tail ⁄2) (Vsg − |VT |)

=

ITail

(6.2)

(Vsg − |VT |)

Here, gm1 is input transistor transconductance and ID1 is the drain current of the input transistor. Varying the value of ID1 has the effect of increasing or decreasing the 158

transconductance of the input differential amplifier. This results in an increase or decrease in the UGF whilst using a fixed value compensation capacitor. However, the PM also varies and so this side-effect must also be taken in consideration.

Figure 6.18 Input stage with tail current source 6.4.1.2 Programmable frequency response The frequency response and stability of an op-amp are based on the UGF and PM. These two characteristics can be improved by using direct Miller compensation [44] and negative Miller [145] techniques. Direct Miller compensation is a method to increase stability, but at the cost of reducing the UGF as the Miller effect results in an effective increase in the input capacitance of the second stage. Negative Miller compensation is usually employed to decrease the input capacitance of the first stage. The principles of a negative capacitance are comparable to the Miller effect [146]. To achieve a negative Miller effect, the amplification stage gain must be much higher than unity. The UGF can be varied by changing the transconductance of the differential input stage. The transconductance varies with tail current as: ITail (Vsg − |VT |) g m1 ITail ft = = = 2π. Cin 2π. Cin (2π. Cin )(Vsg − |VT |)

(6.3)

Any change in the tail current, controlled by an analogue switch, also changes the UGF and the PM.

159

6.4.1.3 Programmable DC gain The amplification stage gain is affected by the tail current. An increasing tail current means an increase in the drain current of input transistors as well as an increased transistor transconductance. The effect is an increase in the stage gain. The gain (Av) is given by: AV = g m1 R1 g m2 R 2

(6.4)

Where gm1 is the transconductance of the first stage, R1 is the output resistance of the first stage, gm2 is the transconductance of the second stage and R2 is the output resistance of the second stage. The open-loop DC gain can be by controlled to the required current level through the input stage. 6.4.2 Programmable control system The principle of operation of the programmable control system is shown in Figure 6.19. The digital logic is contained in the serial peripheral interface block, SPI communications. The SPI communications is connected to the array transistors since the array transistors are tail current to the op-amp. This is used to control the analogue switch positions in the tail current transistor array.

Figure 6.19 Host processor to op-amp digital interface 6.4.2.1 Analogue switches The design of the analogue switch [147] is important in IC circuit designs that require analogue signal paths to be controlled. An ideal analogue switch has infinite OFF 160

(switch open) resistance and zero ON (switch closed). However, a practical implementation of the solid state switch within an IC is non-ideal and these non-ideal aspects need to be controlled to ensure they do not significantly impact the circuit performance. In CMOS, as shown in Figure 6.20, the switch is based on the transmission gate with one nMOS (M1) transistor and one pMOS (M2) transistor connected in parallel. This structure operates forms the switch action. The basic operation is determined by the state of the control signal (clk)and the nMOS transistor requires a high voltage (VDD) to CLOSE and the pMOS transistor requires the complement (i.e., a low voltage (GND)) to CLOSE [140]. The complement input signal to the pMOS transistor gate is generated using a static CMOS logic inverter (M3 and M4). Consideration has to be taken in that there is a finite ON resistance that varies with signal level and the potential for charge injection from the digital control signal to the analogue signal when switching between states.

Figure 6.20 Basic CMOS analogue switch schematic (left) and operating characteristics (right) 6.4.2.2 SPI communications shift register A host processor digitally controls the tail current of the op-amp differential input through a simple SPI protocol. In the SPI communications circuit, a host processor acts as the master and the op-amp acts as the slave. A shift register of D-type flip-flops [148] serially shifts in and stores the analogue switch control signals from the master through the MOSI signal. Once loaded into the design, the shift register contents are loaded into a 5-bit register simultaneously so that the analogue switch control signals d4 … d0 are 161

updated simultaneously. The basic operation is that the MOSI signal is stored on the rising edge of the first five pulses of SCK. On the falling edge of the fifth clock pulse, the switch control signals are loaded into a 5-bit register. The interface consists of four digital inputs (three outputs from the host processor for SPI and a master, active low reset) and one digital output (SPI input to the host) as shown in Figure 6.21. The timing of the control signals is shown in Figure 6.22. The digital logic operates on a separate power supply to that of the analogue circuitry at +3.3 V. ResetN SSn SCK MOSI MISO

d4 SPI communications d0 Analog switch side

Host processor side

Figure 6.21 Block diagram of SPI communication

Figure 6.22 SPI interface communication schematic design 6.4.3 Simulation results The programmable op-amp design was simulated using the Cadence Spectre circuit simulator using typical process models, with the op-amp in open-loop and no output load. Table 6.5 shows the switch operation and the tail current transistor output 162

resistance (RTail) variation with switch position. For the chosen transistor dimensions (and hence tail current), the transistor output resistance varies from 128 kΩ down to 26 kΩ. This will affect the CMRR of the op-amp. For the particular op-amp design, transistor values and switch sizes utilised, choosing different transistor sizes to generate the differential input tail current values show that open-loop DC gain and UGF can be controlled.

Figure 6.23 Programmable op-amp design schematic Table 6.5 Switch code and tail current transistor operation (VDD = +3.3 V, no output load and TM) Switch

Code

S0 S1 S2 S3 S4

00001 00010 00100 01000 10000

W/L (µm) 10/0.35 19.5/0.35 29.55/0.35 39.35/0.35 48/0.35

RTail (kΩ) 128 65 43 32 26

ITail (µA) -29.65 -58.61 -88.97 -118.2 -143.6

Vds (V) -2.563 -2.512 -2.473 -2.439 -2.412

Vds(sat) (mV) -215.9 -217.2 -217.5 -217.4 -217.1

Saturation region yes yes yes yes yes

The tail current transistor has been scaled from (10/0.35) µm and increased to (48/0.35) µm. The current increased from 29.75 µA to 146.2 µA when the op-amp operated without switches (Table 6.6). The tail current transistors have been designed in the saturation region. The drain-source voltage confirms higher than the drain-source saturation voltage. The frequency response can be seen to change with the tail current. For example, the open-loop DC gain varies from 49.27 dB to 80.80 dB. The MTail programmable transistor consists of a 5-bit array [T4 T3 T2 T1 T0], of pMOS transistors 163

in parallel, which is binary weighted to obtain a logarithmic gain ranging from 44.27 dB to 80.08 dB in five steps. Table 6.6 Op-amp performance using tail current control (operation without switches) (VDD = +3.3 V, no output load and TM) Width (µm)

ITail (µA)

DC gain (dB)

UGF (MHz)

PM (degree)

GBP (MHz)

GM (dB)

gm/ID (V-1)

10

29.75

49.27

22.32

97.80

20.55

-22.6

8.83

19.5

59.03

59.88

103.68

92.95

77.18

-15.4

8.77

29.55

89.96

66.86

221.30

72.17

145.49

-11.2

8.74

39.35

119.9

79.95

330.56

54.81

221.40

-8.37

8.74

48

146.2

80.8

353.15

51.41

239.12

-8.17

8.74

The open-loop gain magnitude variation with tail current and frequency is shown in Figure 6.24. Table 6.7, the scheme demonstrates bandwidth (GBP) programmability in a range from 20.39 MHz to 237.82 MHz in five steps when the switches are included. In this circuit, the PM varies between 97.80° and 52.17°. Table 6.7 Op-amp performance using tail current control (operation with switches) (VDD = +3.3 V, no output load and TM) Width (µm)

ITail

DC gain (dB)

UGF (MHz)

PM (degrees)

GBP (MHz)

(µA)

10

GM (dB)

gm/ID (V-1)

29.65

49.20

22.09

97.80

20.39

-22.4

8.84

19.5

58.61

59.79

98.24

93.86

74.36

-15.8

8.79

29.55

88.97

66.57

217.34

73.26

142.75

-11.5

8.78

39.35

118.2

79.74

327.04

54.81

219.49

-8.6

8.79

48

143.6

80.13

350.53

52.17

237.82

-8.3

8.80

In order to prove the operation of the design and to measure the effect of introducing the transistor switches on the circuit performance, the analogue performance of the design was simulated using the Cadence Spectre circuit simulator. With this design and the values of the switch transistor dimensions, the inclusion of the switches whilst did demonstrate an impact the design operation, this impact was negligible. In addition, the switches were not considered for dynamic switching and so charge injection was not an 164

issue. Figure 6.24 compares the PM of the op-amp when the tail current varies in the cases where the switches are included and when no switches are considered. This shows the effects of the switches used in the design. Figure 6.25 is evaluates the UGF of the op-amp when the tail current varies with switches.

Figure 6.24 Frequency response plot (gain magnitude (dB) versus frequency (Hz)) (VDD = +3.3 V, no output load and TM)

Figure 6.25 PM versus tail current (VDD = +3.3 V, no output load and TM)

Figure 6.26 UGF versus tail current ((VDD = +3.3 V, no output load and TM) 165

Table 6.8 and Table 6.9 presents the simulated (TM) PM versus load capacitance (CL) where CL alterations from 0 pF to 80 pF. In addition, in this simulation study, a 1 MΩ resistor (RL) was identified in parallel with CL. The plot identifies the value of CL at which the PM reduces to 45° and therefore the limit of operation for this design. With the design, the PM is seen to be dependent on the process model used (in simulation) and CL. The op-amp was also simulation with the three different processes variation (typical model (TM), worst-case power (WP) and worst-case speed (WS)). Comparing results between op-amp without switches and with switches have shown that the introduction of the switches had a small effect on tail current, DC gain, UGF and PM. Table 6.8 Op-amp performance using tail current control (operation without switches) (VDD = +3.3 V, no output load) Width (µm) 10

19.5

29.55

39.35

48

Process TM WP WS TM WP WS TM WP WS TM WP WS TM WP WS

ITail (µA) 29.75 162.3 5.293 59.03 315.1 10.79 89.96 475.8 16.62 119.9 630.9 22.27 146.2 766.5 27.24

DC gain (dB) 49.27 32.05 44.53 59.88 43.26 57.63 66.86 54.78 63.32 79.95 63.88 59.44 80.8 64.95 83.14

UGF (MHz) 22.320 146.95 1.5335 103.68 396.13 12.504 221.30 798.56 34.859 330.56 1,098 57.214 353.15 1,170 77.84

PM (degree) 97.80 94.19 94.58 92.95 87.28 101.54 72.17 65.58 84.96 54.81 55.05 69.63 51.41 51.87 58.22

GBP (MHz) 20.55 138.65 1.5083 77.18 324.11 9.786 145.49 557.84 22.56 221.40 714.06 37.41 239.12 751.40 53.52

Figure 6.27 presents the simulated (TM) PM versus load capacitance (CL) where CL alterations from 0 pF to 80 pF. In addition, in this simulation study, a 1 MΩ resistor (RL) was identified in parallel with CL. The plot identifies the value of CL at which the PM reduces to 45° and therefore the limit of operation for this design. With the design, the PM is seen to be dependent on the process model used (in simulation) and CL.

166

Table 6.9 Op-amp performance using tail current control (operation switches) (VDD = +3.3 V, no output load) Width (µm) 10

19.5

29.55

39.35

48

Process model TM WP WS TM WP WS TM WP WS TM WP WS TM WP WS

ITail (µA) 29.65 160.4 5.288 58.61 308.1 10.77 88.97 459.7 16.56 118.2 602.5 22.18 143.6 724.8 27.1

DC gain (dB) 49.20 31.88 44.50 59.79 42.81 57.61 66.57 35.33 63.27 79.74 63.40 69.30 80.13 64.77 83.70

UGF (MHz) 22.09 145.07 1.526 98.24 376.0 12.39 217.34 755.53 34.58 327.04 1,064 56.71 350.53 1,151 77.10

PM (degrees) 97.80 94.30 94.58 93.86 88.06 101.64 73.26 71.48 85.29 54.81 56.57 70.14 52.17 53.13 58.74

GBP (MHz) 20.39 136.60 1.503 74.36 315.8 9.745 142.75 530.81 22.44 219.49 701.83 37.17 237.82 741.67 53.32

Figure 6.27 PM versus output load (CL) (RL = 1 MΩ, with switches and TM) Figure 6.28 shows the operation of the programmable op-amp. When SSn is low, the serial data on MOSI is shifted into a 4-bit shift register on the rising edge of the clock (SCK). Hereby, the op-amp is simulated with SPI communications and time is from 0 ms to 1.1 ms. The SPI is loaded from 0 to 1 ms after that time, SPI is activated the switch d3 (S3) and the op-amp is operated after loaded.

167

Figure 6.28 Operation of the programmable gain and bandwidth op-amp (VDD = +3.3 V, no output load and TM) 6.5 Conclusions This chapter has considered the design and simulation of a mixed-signal and programmable open-loop frequency response op-amp. Two programmable op-amp designs were presented. Firstly, a switched capacitor array was utilised to control GM, PM and UGF that would influence the stability of the op-amp at higher frequencies. The circuit could be used in a number of different design applications where it would be suitable to control the op-amp frequency response using a digital host processor. Secondly, employing a switched transistor array to control the open-loop DC gain and bandwidth frequency that would have an effect on the stability of the op-amp at higher frequencies when used in a closed-loop configuration. The designs were developed to be part of an ASIC (application specific integrated circuit) solution using a 0.35 µm CMOS fabrication process. The operation of the amplifier was simulated using the Cadence Spectre circuit simulator. The circuit could be utilised in a number of different design applications where it would be suitable to control the op-amp frequency response and open-loop DC gain using a digital host processor.

168

Chapter 7 Conclusions and future work

7.1 Summary of the work This thesis has demonstrated and evaluated compensation techniques for different operational amplifier (op-amp) designs, identifying their advantages and disadvantages. Additionally, it has aimed to present the design and implementation of the Complementary Metal-Oxide-Semiconductor (CMOS) op-amp with the use of negative Miller compensation that is used in combination with direct and indirect Miller compensation. Five different op-amps topologies have been presented and evaluated. These op-amp designs are summarised below. 7.1.1 Rail-to-rail single ended output op-amp In this prototype, three op-amp design variations were developed using (i) direct Miller only (ii) negative Miller with direct Miller, and (iii) negative Miller with indirect Miller compensation. Figure 7.1 shows the process of developing and evaluating the operation of this first op-amp topology. The first op-amp of the rail-to-rail output op-amp topology was designed using direct Miller compensation only. It includes the initial opamp design and specifications. The op-amp specifications were given by the phase margin (PM), which was greater than 60°, the unity gain frequency (UGF) is approximately 22.65 MHz and the power supply voltage operation is +2.5 V. The second op-amp of the rail-to-rail output topology was the same as the first op-amp except that now negative Miller compensation was included in the first stage. The second stage was provided by direct Miller compensation and the value of negative Miller capacitor was the same as that of direct Miller capacitor. The third op-amp of the rail-to-rail output topology was the same as the second op-amp except that direct Miller was replaced by indirect Miller compensation. Indirect Miller compensation uses the 169

same principle as that of direct Miller compensation except that the connection of the capacitor is made to the folded cascode nodes. Specifications based on direct Miller compensation (first op-amp)

UGF and PM simulation TM, WS, WP and Monte Carlo process variations

Insert a negative Miller with direct compensation (second op-amp)

UGF and PM simulation TM, WS, WP and Monte Carlo process variations

Alteration direct to indirect Miller compensation (third op-amp)

UGF and PM simulation TM, WS, WP and Monte Carlo process variations

Comparison and evaluated the simulation for a PM and UGF

Figure 7.1 Steps in the rail-to-rail output op-amp design and evaluation process using different compensation techniques All capacitors of the direct, indirect, and negative Miller were assigned the same value and the op-amp was set to work on single rail +2.5 V and +1.8 V power supply voltage levels. Therefore, the simulation of the op-amp designs concentrated on PM, UGF, SR, and settling time by comparing the results of these op-amps. The use of negative Miller shows improvements when simulations are carried out under typical model (TM). 7.1.2 Rail-to-rail input and output op-amp The second topology of the op-amp design was a rail-to-rail input and output op-amp using direct and negative Miller compensation. It must be noted that the rail-to-rail input/output op-amp was designed to work on a single rail +3.3 V power supply voltage level only. In the op-amp, a two-stage amplifier was used where the first stage was a complementary input stage that is connected to summing circuit. In addition, the tail current transistor of complementary input stage has used mirror current one-times for controlling the input transconductance and the second stage was a class-AB amplifier.

170

The op-amp was simulated with process variations as typical process, worst-case power and worst-case speed, as well as Monte-Carlo in order to evaluate the PM and UGF. 7.1.3 Fully-differential rail-to-rail output op-amp The fully-differential op-amp was considered as the third topology and the compensation used negative Miller with indirect Miller compensation. The negative Miller was used around first-stage while indirect Miller was utilised between the output nodes and cascode nodes. In the op-amp, the two-stage amplifier was utilised, first stage being a differential input stage with folded cascode circuit while second stage was a class-AB amplifier. The outputs were connected to common-mode feedback circuit in order to balance output common mode. The op-amp has simulated with process variations as worst-case power and worst-case speed varying with temperatures in order to evaluated PM and UGF 7.1.4 Programmable bandwidth op-amp The fourth topology of the op-amp design in this thesis was a programmable bandwidth op-amp. Negative Miller with direct Miller compensation were used. This op-amp has considered as the fourth topology is the programmable bandwidth op-amp, which designs control for the bandwidth of the open-loop configuration by controlling the values of the compensation capacitors to estimate the UGF and PM at op-amp loop configuration. 7.1.5 Programmable gain and bandwidth op-amp The fifth topology of the op-amp design was the programmable bandwidth/gain opamp, which is designed for controlling tail current input transistors in order to control the values of the DC, PM, and UGF. The compensation techniques of programmable op-amps are implemented using direct and negative Miller compensation in order to estimate the UGF and PM at op-amp loop configuration. 7.2 Aims of the research This thesis has aimed to provide an evaluation of different compensation techniques for op-amp designs where the negative Miller technique was used with direct Miller and indirect Miller compensation. It has also aimed to demonstrate the design and 171

implementation and evaluation of the CMOS op-amp with the Miller compensation as described. The principle of using direct Miller compensation has been to split the two dominant poles (it moves first pole P1 to low frequencies and second pole P2 to higher frequencies) for increasing the stability. However, there are three key issues to account for: (i) it creates a feed-forward path from the output to input and produces more poles of the transfer function, (ii) it creates a right-half-plane zero (RHP zero), which reduces the bandwidth at zero dB, and (iii) it has a large layout in comparison to indirect Miller. Indirect Miller compensation was also used to split poles and has the same principle as that of direct Miller, the only difference being the nodes which the capacitors connect to. The other compensation method used was negative Miller, which has the same connection as that of direct and indirect Miller but is used to extend UGF by cancelling or removing the effects of the input capacitance. In this study, 1. The first topology op-amp was a rail-to-rail output two-stage amplifier that operates at +2.5 V and +1.8 V and ground (GND = 0) power supply, moreover, it has shown improvement in PM and UGF when negative Miller compensation was incorporated with direct and indirect Miller under the TM process. The first op-amp has used direct Miller compensation, the second op-amp has incorporated negative Miller with direct Miller compensation, and the third opamp has combined negative Miller with indirect Miller compensation. As shown in Table 7.1, for +2.5 V power supply operation, the gain is almost constant at 79.79 dB. The PM improves from 70.38°, 78.24° and 99.48°, whilst the UFG extends from 16.82 MHz, 18.12 MHz to 24.23 MHz. For +1.8 V power supply operation, the gain is almost constant at 76.68 dB, PM increases from 73.29°, 84.18° and 101.06°, whilst the UGF expands from 214.2 kHz, 263.5 kHz and 321.9 kHz. Table 7.1 Frequency response for the first topology (TM, no output load) +2.5 V

+1.8 V

Performance

Gain (dB)

PM (degrees)

UGF (MHz)

Gain (dB)

PM (degrees)

UGF (kHz)

First op-amp

80.66

70.38

16.82

77.91

73.29

214.2

Second op-amp

79.79

78.24

18.12

76.68

84.18

263.5

Third op-amp

79.74

99.48

24.23

76.68

101.06

321.9

172

2. The second op-amp topology was a rail-to-rail input/output two-stage amplifier and was designed to operate from +3.3 V and ground (GND = 0) power supplies. In the op-amp design, a one-times mirror current was used to control the transconductance of the complementary input stage, since the input transconductance is responsible for accomplishing DC gain and UGF. In Table 7.2, it is shown that the UGF and PM are improved by incorporating negative Miller and direct Miller compensation. 3. The third topology op-amp design was a fully-differential amplifier, which is a rail-to-rail output two-stage amplifier. It is measured to operate at +3.3 V and ground (GND = 0) power supplies, the UGF and PM were improved by incorporating the negative Miller and indirect Miller compensation (Table 7.2). Table 7.2 Frequency response for the op-amp alternative topologies (TM, no output load and VDD = +3.3 V) Second topology

Third topology

Performance

Value

Value

Gain (dB)

85.33

84.9

Unity gain frequency (MHz)

271.1

707.97

Phase margin (degrees)

63.62

77.90

4. The programmable bandwidth op-amp, negative Miller and direct Miller compensation were controlled by monitoring the value of the capacitors. The changing capacitor's value converts to adjustable PM and UGF. The control part was designed using different capacitors for direct Miller and negative Miller compensation, and analogue switches. The analogue switches are transmission gates combined with an inverting amplifier in order to control the inputs of the nMOS and pMOS transistors of the transmission gate. The inputs of analogue switches are connected to the SPI communications and the outputs of analogue switches are connected to the capacitors. 5. The final programmable op-amp was the programmable gain/bandwidth opamp. This op-amp was used to control the open-loop configuration by monitoring the tail current of the input differential stage and this kind of design provides the possibility to control the DC gain, PM, and UGF. 173

The principle of control was the same as the principle of using SPI communications with analogue switches. The SPI communication was used to transfer data from the digital part to the analogue part (op-amp). The frequency response performance is shown below in Table 7.3. It must also be noted that the operation power supply voltage is +3.3 V for all parts of the design as analogue VDD and analogue GND =0 V for the analogue part and digital VDD and digital GND for digital part. Table 7.3 Frequency response for the programmable op-amps topology (TM, no output load and VDD = +3.3 V) Fourth topology

Fifth topology

At CNM and CM = 0.4 pF

At Itial = 88.97 µA

83

66.57

Unity gain frequency (MHz)

170.1

217.34

Phase margin (degrees)

78.87

73.26

Performance Gain (dB)

7.3 Proposed future work 7.3.1 First aspect In this thesis, the frequency response was considered to evaluate the compensation of op-amps. The op-amps in this research consisted of negative Miller incorporated with different compensation techniques. The op-amps display suitable performance without using input/output (I/O) pads, hence they are suitable to be integrated with other electronic circuitry, for example, in data converters. If they were to be fabricated as a discrete package design, they would need to be redesigned since they lack adequate margin stability. This would lead to re-investigation into undertaking: •

The impedance of the printed circuit board (PCB) and wires connections: Any two conductors, which are not short-circuited, have a capacitance between them called stray capacitance. Therefore, on any PCB, there are always a large number of capacitors related to any circuit. The PCB effects become most visible in high-speed analogue circuits. In addition, any wires connection creates stray capacitance. In order to improve the performance at high frequency, the capacitance of the connection between any two conductors has to be reduced.

174



The impedance of test equipment: In addition, the test equipment used has input impedance (e.g., the SF880 test equipment used has a RTest = 1 ΩM and CTest=10 pF) connected to the output of the op-amp. These impedances acted as a load impedance that has impacted on the performance at high frequency.

7.3.2 Second aspect The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has four terminals: gate, drain, source, and bulk. The gate terminal acts as the input node (inverting and non-inverting). In this work, the input nodes of the op-amp were used the gate of the MOSFET. The negative Miller compensation is applied at the gates of the input stage. Some researchers have used the bulk of MOSFET as the input nodes of the op-amp. In future work, negative Miller compensation could be connected around the bulk node that could be reduced the input capacitance. The desirable characteristics of bulk-driven transistors are: (i) low-voltage and low-power consumption, (ii) depletion characteristics that avoid a VT requirement. However, some undesirable characteristics of bulk-driven transistors are: (i) the transconductance of a bulk-driven MOSFET is smaller, which may result in lower UGF in an OTA, and (ii) the polarity of the bulk-driven MOSFET is technology-related, for a P (N) well CMOS process, only N (P) channels bulk-driven MOSFETs are available, this may limit its applications. For example, a rail-to-rail bulk-driven op-amp needs a dual well process to realise it. This fabrication process is more expensive to use than a single-well process, more significant die area is required, and it has the worst matching compared to the single-well process.

175

176

References [1]

C. Toumazou, F. J. Lidgey, and D. Haigh, Analogue IC design: the current-mode approach. Presbyterian Publishing Corp, 1990.

[2]

(2018). Analog IC Market Forecast With Strongest Annual Growth Through 2022. Available: http://www.icinsights.com/data/articles/documents/1036.pdf

[3]

K. N. Leung and P. K. Mok, "Analysis of multistage amplifier-frequency compensation," IEEE transactions on circuits and systems I: fundamental theory and applications, vol. 48, no. 9, pp. 1041-1056, 2001.

[4]

L. Li, "HIGH GAIN LOW POWER OPERATIONAL AMPLIFIER DESIGN," Brigham Young University, 2007.

[5]

P. Jespers, The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches. Springer Science & Business Media, 2009.

[6]

H. Zumbahlen, Basic Linear Design. Analog Devices, 2007.

[7]

M. R. Haskard and I. C. May, Analog VLSI design: nMOS and CMOS. PrenticeHall, Inc., 1987.

[8]

G. B. Clayton and S. Winder, Operational amplifiers. Newnes, 2003.

[9]

F. Maloberti, Understanding Microelectronics: A Top-down Approach. John Wiley & Sons, 2011.

[10]

M. C. Schneider and C. Galup-Montoro, CMOS analog design using all-region mosfet modeling. Cambridge University Press, 2010.

[11]

A. J. Rao, "Analog front-end design using the gm/ID method for a pulse-based plasma impedance probe system," UTAH STATE UNIVERSITY, 2010.

177

[12]

I. A. Grout, M. Zaidi, K. L. Sterckx, and A. K. b. A'ain, "RGB LED driver circuit design for an optical fiber sensor system," in 2016 13th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2016, pp. 1-6.

[13]

L. Ramezani, "A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion," in Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, Berlin, Heidelberg, 2011, pp. 51-61: Springer Berlin Heidelberg.

[14]

S.-S. Edgar and G. A. Andreas, "LowPower CMOS Digital Circuits," in LowVoltage/Low-Power Integrated Circuits and Systems:Low-Voltage MixedSignal Circuits: Wiley-IEEE Press, 1999, p. 592.

[15]

P. E. Allen, B. J. Blalock, and G. A. Rincon, "Low voltage analog circuits using standard CMOS technology," in Proceedings of the 1995 international symposium on Low power design, 1995, pp. 209-214: ACM.

[16]

R. K. Baruah, "Design of a low power low voltage CMOS Opamp," arXiv preprint arXiv:1003.5439, 2010.

[17]

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, 2003.

[18]

R. J. van de Plassche, W. Sansen, and J. Huijsing, Analog Circuit Design: Lowpower Low-voltage, Integrated Filters and Smart Power. Springer Science & Business Media, 2013.

[19]

R. Alini, A. Baschirotto, R. Castello, and F. Montecchi, "Accurate MOS threshold voltage detector for bias circuitry," in [Proceedings] 1992 IEEE International Symposium on Circuits and Systems, 1992, vol. 3, pp. 1280-1283 vol.3.

[20]

S.-S. Edgar and G. A. Andreas, "LowVoltage/LowPower Amplifiers with 178

Optimized Dynamic Range and Bandwidth," in Low-Voltage/Low-Power Integrated Circuits and Systems:Low-Voltage Mixed-Signal Circuits: WileyIEEE Press, 1999, p. 592. [21]

S. L. J. Gierkink, P. J. Holzmann, R. J. Wiegerink, and R. F. Wassenaar, "Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp," Analog Integrated Circuits and Signal Processing, vol. 21, no. 2, pp. 143-152, 1999/11/01 1999.

[22]

W. G. Jung, Op Amp applications handbook. Newnes, 2005.

[23]

"Frequency Compensation Techniques," in Feedback Amplifiers: Theory and Design, G. Palumbo and S. Pennisi, Eds. Boston, MA: Springer US, 2002, pp. 103-135.

[24]

M. S. Oskooei, K. Hadidi, and A. Khoei, "A Novel Method for Bandwidth and Phase Margin Enhancement of Folded-Cascode Amplifier," Analog Integrated Circuits and Signal Processing, vol. 46, no. 2, pp. 91-98, 2006/02/01 2006.

[25]

R. G. Eschauzier and J. Huijsing, Frequency compensation techniques for lowpower operational amplifiers. Springer Science & Business Media, 2013.

[26]

L. Maheswari and M. Anand, Analog electronics. PHI Learning Pvt. Ltd., 2009.

[27]

Y. Yazawa, Y. Kobayashi, A. Fukami, and T. Nagano, "MOSFET with reduced short channel effect," ed: Google Patents, 1989.

[28]

R. Johansson, "Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35 um Process," ed: Institutionen för systemteknik, 2003.

[29]

K. Laker and W. Sansen, "Design of analog integrated circuits and systems," status: published, p. 898, 1994.

[30]

N. Caka, M. Zabeli, M. Limani, and Q. Kabashi, "Impact of MOSFET 179

parameters on its parasitic capacitances," in Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications, 2007, pp. 55-59: World Scientific and Engineering Academy and Society (WSEAS). [31]

D. J. Comer and D. T. Comer, "Operation of analog MOS circuits in the weak or moderate inversion region," IEEE Transactions on Education, vol. 47, no. 4, pp. 430-435, 2004.

[32]

A. Sarkar, S. De, M. Chanda, and C. K. Sarkar, Low Power VLSI Design: Fundamentals. Walter de Gruyter GmbH & Co KG, 2016.

[33]

P. E. Allen and D. R. Holberg, CMOS analog circuit design. Taylor & Francis US, 2002.

[34]

D. J. Comer and D. T. Comer, "Using the weak inversion region to optimize input stage design of CMOS op amps," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 1, pp. 8-14, 2004.

[35]

R. Hogervorst and J. Huijsing, Design of low-voltage, low-power operational amplifier cells. Springer Science & Business Media, 2013.

[36]

P. Antognetti and G. Massobrio, Semiconductor Device Modeling with Spice. McGraw-Hill, Inc., 1990, p. 416.

[37]

D. M. Binkley, "Tradeoffs and optimization in analog CMOS design," in 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems, 2007, pp. 47-60: IEEE.

[38]

W.-C. Kao. (2010). IMPACT OF INTERFACE STATES ON SUBTHRESHOLD RESPONSE OF III-V MOSFETs, MOS HEMTs AND Tunnel FETs. Available: https://etda.libraries.psu.edu/files/final_submissions/6588

[39]

Y. Tsividis, "Moderate inversion in MOS devices," Solid-State Electronics, vol. 25, no. 11, pp. 1099-1104, 1982. 180

[40]

E. A. Vittoz, "Micropower techniques," vol. 5, ed: chapter, 1994.

[41]

M. Bucher, C. Lallement, C. Enz, F. Theodoloz, and F. Krummenacher, "Scalable Gm/I based MOSFET model," in Int. Semicond. Dev. Research Symp.(ISDRS’97), 1997, pp. 615-618.

[42]

D. A. Johns and K. Martin, Analog integrated circuit design. John Wiley & Sons, 2008.

[43]

S. C. Terry, J. M. Rochelle, D. M. Binkley, B. J. Blalock, D. P. Foty, and M. Bucher, "Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 μm CMOS process and implications for analog circuit design," IEEE Transactions on Nuclear Science, vol. 50, no. 4, pp. 915-920, 2003.

[44]

Y.-C. Teng, "Improved Synthesis Tool for Miller OTA Stage Using gm/ID Methodology," The Ohio State University, 2011.

[45]

L. W. Isworo, H. Ochi, and C. Muto, "A low-voltage, low-power, wide gainrange

VGA

design

using

g

m=

I

D

Method,"

in

Electrical

Engineering/Electronics Computer Telecommunications and Information Technology (ECTI-CON), 2010 International Conference on, 2010, pp. 392396: IEEE. [46]

K. Ueno, "CMOS Voltage and Current Reference Circuits consisting of Subthreshold MOSFETs–Micropower Circuit Components for Power-Aware LSI Applications–," in Solid State Circuits Technologies: InTech, 2010.

[47]

D. Wolpert and P. Ampadu, "Temperature Effects in Semiconductors," in Managing Temperature Effects in Nanoscale Adaptive SystemsNew York, NY: Springer New York, 2012, pp. 15-33.

[48]

N. Goel and A. Tripathi, "Temperature effects on threshold voltage and mobility for partially depleted SOI MOSFET," International Journal of Computer Applications, vol. 42, no. 21, pp. 56-58, 2012. 181

[49]

Y. Amhouche, A. El Abbassi, K. Raïs, and R. Rmaily, "Analysis of temperature and drain voltage dependence of substrate current in deep submicrometer MOSFET's," Active and passive electronic components, vol. 24, no. 3, pp. 201209, 2001.

[50]

K. Rais, G. Ghibaudo, and F. Balestra, "Temperature dependence of substrate current in silicon CMOS devices," Electronics Letters, vol. 29, no. 9, pp. 778780, 1993.

[51]

R. M. Marston, Modern CMOS circuits manual. Newnes, 1995.

[52]

M. I. Kazim, "Design of highly linear sampling switches for CMOS track-andhold circuits," ed: Universitetsbibliotek, 2006.

[53]

A. systems, "0.35 μm CMOS C35 Process Parameters," 2003, Available: https://fenix.tecnico.ulisboa.pt/downloadFile/3779572216107/tips%40austriam icrosystems.com.

[54]

L. Rufer, Fabless Approach to the Fabrication of Electroacoustic Microtransducers. 2016.

[55]

C. D. Raj, Electronic devices and circuits. Pearson Education India, 2008.

[56]

C. Bruce and M. Ron, "Op Amps for everyone," ed: Burlington (MA, USA): Newnes, 2009.

[57]

K. Addington, "Design of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process," 2017.

[58]

P. R. Gray and R. G. Meyer, Analysis and design of analog integrated circuits. Wiley.

[59]

J. Huijsing, Operational amplifiers: theory and design. Springer Science & Business Media, 2011.

182

[60]

A. S. Sedra and K. C. Smith, Microelectronic circuits. Oxford university press, 1998.

[61]

M. M. Radmanesh, Advanced RF & microwave circuit design: the ultimate guide to superior design. AuthorHouse, 2008.

[62]

K. L. Du and M. N. s. Swamy, Wireless communication systems: From RF subsystems to 4G enabling technologies. 2010, pp. 1-985.

[63]

(2013). Amplifier Classes and the Classification of Amplifiers. Available: https://www.electronics-tutorials.ws/amplifier/amplifier-classes.html

[64]

G. A. Rincon-Mora and R. Stair, "A low voltage, rail-to-rail, class AB CMOS amplifier with high drive and low output impedance characteristics," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 8, pp. 753-761, 2001.

[65]

M. Loikkanen, "Design and compensation of high performance class AB amplifiers," Academic Dissertation, Faculty of Technology, University of Oulu, 2010.

[66]

J. H. Huijsing, R. Hogervorst, and K. J. d. Langen, "Low-voltage low-power amplifiers," in 1993 IEEE International Symposium on Circuits and Systems, 1993, pp. 1443-1446 vol.2.

[67]

A. Torralba, R. Carvajal, J. Martinez-Heredia, and J. Ramirez-Angulo, "Class AB output stage for low voltage CMOS op-amps with accurate quiescent current control," Electronics Letters, vol. 36, no. 21, pp. 1753-1754, 2000.

[68]

H. Sjöland, Highly Linear Integrated Wideband Amplifiers: Design and Analysis Techniques for Frequencies from Audio to RF. Springer Science & Business Media, 2012.

[69]

K. Joongsik, C. Byungsoo, and J. Deog-Kyoon, "Class-AB large-swing CMOS buffer amplifier with controlled bias current," IEEE Journal of Solid-State 183

Circuits, vol. 28, no. 12, pp. 1350-1353, 1993. [70]

T. Ndjountche, CMOS Analog Integrated Circuits: High-Speed and PowerEfficient Design. CRC Press, 2016.

[71]

V. V. Ivanov and I. M. Filanovsky, Operational amplifier speed and accuracy improvement: analog circuit design with structural methodology. Springer Science & Business Media, 2006.

[72]

B. C. Baker, "What Does ‘Rail-to-rail’Operation Really Mean," Analog Design Note, ADN009, p. 1, 2004.

[73]

Y. Lin, "A NEW ARCHITECTURE OF CONSTANT-gm RAIL-TO-RAIL INPUT STAGE FOR LOW VOLTAGE LOW POWER CMOS OP AMP," The Ohio State University, 2010.

[74]

Z. Qin, A. Tanaka, N. Takaya, and H. Yoshizawa, "0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 11, pp. 1009-1013, 2016.

[75]

R. Hogervorst, J. P. Tero, and J. Hoijising, "Compact CMOS constant-g m railto-rail input stage with g m-control by an electronic zener diode," Solid-State Circuits, IEEE Journal of, vol. 31, no. 7, pp. 1035-1040, 1996.

[76]

N. Bhargava and N. B. S. G. D. Kulshreshtha, Basic Electronics and Linear Circuits. Tata McGraw-Hill Education, 1984.

[77]

V. Mehta and R. Mehta, Principle Of Elect. Engg. & Electronics (ME). S. Chand, 2006.

[78]

B. Razavi, "Fundamentals of microelectronics," Jhon Wiley india Pvt. Ltd, 2009.

[79]

W.-K. Chen, Analog and VLSI circuits. CRC Press, 2009. 184

[80]

R. J. Baker, CMOS: circuit design, layout, and simulation. John Wiley & Sons, 2011.

[81]

V. Saxena and R. J. Baker, "Indirect feedback compensation of CMOS opamps," in 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED '06., 2006, pp. 2 pp.-4.

[82]

I. knausz, "Class AB AMP Design | Operational Amplifier | Amplifier," ed, 2018.

[83]

D. Stefanovic and M. Kayal, Structured analog CMOS design. Springer Science & Business Media, 2008.

[84]

E. Säckinger, Broadband circuits for optical fiber communication. John Wiley & Sons, 2005.

[85]

B. Shem-Tov, M. Kozak, and E. G. Friedman, "A high-speed CMOS op-amp design technique using negative Miller capacitance," in Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on, 2004, pp. 623-626: IEEE.

[86]

D. J. Comer, D. T. Comer, J. B. Perkins, K. D. Clark, and A. P. Genz, "Bandwidth extension of high-gain CMOS stages using active negative capacitance," in Electronics, Circuits and Systems, 2006. ICECS'06. 13th IEEE International Conference on, 2006, pp. 628-631: IEEE.

[87]

F. Aznar, S. C. Pueyo, and B. C. López, CMOS receiver front-ends for gigabit short-range optical communications. Springer Science & Business Media, 2012.

[88]

F. Tavernier and M. Steyaert, High-speed optical receivers with integrated photodiode in nanoscale CMOS. Springer Science & Business Media, 2011.

[89]

M. Kumar, "Design of fully differential operational amplifier with high gain, large bandwidth and large dynamic range," THAPAR UNIVERSITY PATIALA, 2009. 185

[90]

A. P. Genz, "Operational Amplifier Bandwidth Extension Using Negative Capacitance Generation," 2006.

[91]

C. Shankar and M. Kaur, "Stability and Bandwidth Enhacement of Two Stage Op-amp Using Negative Capacitance Generation."

[92]

P. Muller and Y. Leblebici, CMOS multichannel single-chip receivers for multigigabit optical data communications (no. LSM-BOOK-2007-001). Springer, 2007.

[93]

D. M. Monticelli, "A quad CMOS single-supply op amp with rail-to-rail output swing," IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 1026-1034, 1986.

[94]

B. D. Miser, "Design of a Wide-Swing Cascode Beta Multiplier Current Reference," 2003.

[95]

K.-J. De Langen and J. Huijsing, Compact low-voltage and high-speed CMOS, BiCMOS and bipolar operational amplifiers. Springer Science & Business Media, 2013.

[96]

P. Fiedorow, P. Maige, D. Subiela, T. Tixier, and N. Abouchi, "Design and implementation of general purpose opamp using multipath frequency compensation," in New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International, 2011, pp. 446-449: IEEE.

[97]

K. L. Kishore and V. Prabhakar, VLSI design. IK International Pvt Ltd, 2010.

[98]

A. B. Kahng, J. Lienig, I. L. Markov, and J. Hu, "Chip Planning," in VLSI Physical Design: From Graph Partitioning to Timing Closure, A. B. Kahng, J. Lienig, I. L. Markov, and J. Hu, Eds. Dordrecht: Springer Netherlands, 2011, pp. 55-92.

[99]

L. Lavagno, G. E. Martin, and L. Scheffer, Electronic Design Automation for Integrated Circuits Handbook: EDA for IC system design, verification, and 186

testing. CRC/Taylor & Francis, 2006. [100] M. Reinhardt and R. Corporation, "Guide to Physical Design Reuse Tools: Uses and Functions," Automatic Layout Modification: Including design reuse of the Alpha CPU in 0.13 micron SOI technology, pp. 119-132, 2002. [101] K. H. Lundberg, "Internal and external op-amp compensation: a control-centric tutorial," in Proceedings of the 2004 American Control Conference, 2004, vol. 6, pp. 5197-5211 vol.6. [102] A. Sheeparamatti, M. V. Bhat, M. P. Srivatsa, and M. Nithin, "Design of 3.3 V rail to rail operational amplifier for high resolution ADC driver amplifier," in 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), 2017, pp. 317-321. [103] L. S. Y. Wong, "1.8 V low voltage pseudo-differential input operational amplifier," in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002, vol. 1, pp. I-317-I-320 vol.1. [104] R. S. Assaad and J. Silva-Martinez, "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier," IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, 2009. [105] M. K. Hati and T. K. Bhattacharyya, "A power efficient and constant-g m 1.8 V CMOS operational transconductance amplifier with rail-to-rail input and output ranges for charge pump in phase-locked loop," in Devices, Circuits and Systems (ICDCS), 2012 International Conference on, 2012, pp. 38-43: IEEE. [106] K. J. Raut, R. V. Kshirsagar, A. C. Bhagali, and Ieee, "Low-Voltage High-Gain Folded Architecture Operational Amplifier," (in English), 2016 Conference on Advances in Signal Processing (Casp), Proceedings Paper pp. 160-163, 2016. [107] H. Gupta, G. K. Mishra, N. Z. Rizvi, and S. K. Patnaik, "Design of high PSRR folded cascode operational amplifier for LDO applications," in 2016 International Conference on Electrical, Electronics, and Optimization 187

Techniques (ICEEOT), 2016, pp. 4617-4621. [108] H. Guliga, S. H. Herman, and W. F. H. Abdullah, "Design and characterization of three stage CMOS op amps in 130nm technology with indirect feedback compensation technique," in 2015 IEEE Student Conference on Research and Development (SCOReD), 2015, pp. 605-609. [109] G. D. Cataldo, A. D. Grasso, G. Palumbo, and S. Pennisi, "Single-miller allpassive compensation network for three-stage OTAs," in 2015 European Conference on Circuit Theory and Design (ECCTD), 2015, pp. 1-4. [110] S. Gaonkar, P. S. Sushma, and A. Fathima, in 2016 International Conference on Computer Communication and Informatics (ICCCI), 2016, pp. 1-4. [111] Y. Jiang and S. Jiang, "A low noise class-AB amplifier for voice communication," in 2009 IEEE 8th International Conference on ASIC, 2009, pp. 246-249. [112] S. Pennisi, M. Piccioni, G. Scotti, and A. Trifiletti, "High-CMRR Current Amplifier Architecture and Its CMOS Implementation," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1118-1122, 2006. [113] Analog Arts SF990 SF880 SF830 Product Specifications. Available: http://www.analogarts.com/images/AnalogArts/PDFs/Sweep%20Frequency%2 0Response%20Analyzer%20with%20Multifunction%20Oscilloscope%20Spec ifications.pdf [114] M.-C. Weng and J.-C. Wu, "A compact low-power rail-to-rail class-B buffer for LCD column driver," IEICE Transactions on Electronics, vol. 85, no. 8, pp. 1659-1663, 2002. [115] L. H. d. C. Ferreira and T. C. Pimenta, "An ultra low-voltage ultra low power rail-to-rail CMOS OTA Miller," in The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings., 2004, vol. 2, pp. 953-956 vol.2. 188

[116] X. F. Zha, Y. S. Yin, and Ieee, "The Design Rail-to-Rail Operational Amplifier Used in PGA," (in English), 2015 Ieee 9th International Conference on AntiCounterfeiting, Security, and Identification (Asid), Proceedings Paper pp. 6165, 2015. [117] J. Monteiro and R. Van Leuken, Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers. Springer, 2010. [118] D. Vijeta and S. Wairya, "Performance Evaluation of Different Types of CMOS Operational Transconductance," International Journal Of Engineering And Computer Science, vol. 3, no. 10, 2014. [119] D. L. Knee and C. E. Moore, "General-purpose 3V CMOS operational amplifier with a new constant-transconductance input stage," Hewlett Packard Journal, vol. 48, pp. 114-120, 1997. [120] S. R. Dessai, P. Keny, U. Gaitonde, and M. V. S. Chandra, "Design of CMOS based Programmable Gain Operational Amplifier," in RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics, 2013, pp. 139-142. [121] M. Z. Jahangir and C. S. Paidimarry, "Design of programmable Op-Amps with minimized DC variations at output," in 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013, pp. 120-125. [122] J. Hao, Z. Song, and B. Chi, "A reconfigurable analog baseband for low-power Wi-Fi receiver," in 2015 IEEE 11th International Conference on ASIC (ASICON), 2015, pp. 1-4. [123] Stmicroelectronics, "Operational amplifier stability compensation methods for capacitive loading applied to TS507," 2007. [124] "LM4250 LM4250 Programmable Operational Amplifier." 189

[125] C. Wells and J. Becker, "Low-Cost Digital Programmable Gain Amplifier Reference Design." [126] S. George et al., "A Programmable and Configurable Mixed-Mode FPAA SoC," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2253-2261, 2016. [127] H. A. d. A. Serra and N. Paulino, "Switched-Capacitor Circuits," in Design of Switched-Capacitor Filter Circuits using Low Gain Amplifiers, H. A. d. A. Serra and N. Paulino, Eds. Cham: Springer International Publishing, 2015, pp. 3-13. [128] AnadigmTM. (2003). AN120E04 Datasheet – Reconfigurable FPAA. Available: http://www.anadigm.com/_doc/DS021000-U004.pdf [129] A. H. Bratt, A. M. D. Richardson, R. J. A. Harvey, and A. P. Dorey, "A designfor-test structure for optimising analogue and mixed signal IC test," in Proceedings the European Design and Test Conference. ED&TC 1995, 1995, pp. 24-33. [130] "IEEE Standard for a Mixed-Signal Test Bus," IEEE Std 1149.4-2010 (Revision of IEEE Std 1149.4-1999), pp. 1-116, 2011. [131] D. H. Gawali and V. M. Wadhai, "Mixed signal SoC based Bio-Sensor Node for long term health monitoring," in 2016 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE), 2016, pp. 194-198. [132] "PSoC™ Mixed-Signal Array Final Data Sheet," 2004. [133] V. Giannini, J. Craninckx, S. D'Amico, and A. Baschirotto, "Flexible baseband analog circuits for software-defined radio front-ends," IEEE journal of solidstate circuits, vol. 42, no. 7, pp. 1501-1512, 2007. [134] H. Movahedi-Aliabad, M. Maymandi-Nejad, E. Shadkami, N. Khorashahian, and M. Mianji, "Design of an ECG Signals Amplifier with programmable Gain and Bandwidth Based on a New Method in Pseudo-Resistor Circuits," 2014. 190

[135] I. García López et al., "High speed BiCMOS linear driver core for segmented InP Mach-Zehnder modulators," Analog Integrated Circuits and Signal Processing, journal article vol. 87, no. 2, pp. 105-115, 2016. [136] (2002, 3rd October ). Recommended Test Procedures for Analog Switches. Available: https://www.intersil.com/content/dam/Intersil/documents/an55/an557.pdf [137] (November 30, 2010). Serial Peripheral Interface (SPI) Slave. Available: http://www.cypress.com/file/132126/download [138] A. C. Katageri, B. Sheeparamatti, and V. B. Math, "Design of MEMS based 4bit shift register," in Smart Structures and Systems (ICSSS), 2014 International Conference on, 2014, pp. 103-107: IEEE. [139] V. S. C. Simulator, "Cadence Design Systems," Inc., Available at: www. cadence. com, 2005. [140] A. Devices, "Analog Switches and Multiplexers Basics," Analog Devices, Inc., Norwood, 2008. [141] R. Fiorelli, E. Peralías, and F. Silveira, "An all-inversion-region gm/ID based design methodology for radiofrequency blocks in CMOS nanometer technologies," Wireless Radio-Frequency Standards and System Design: Advanced Techniques: Advanced Techniques, p. 15, 2012. [142] B.-S. Song, Micro CMOS design. Boca Raton, FL: CRC Press/Taylor & Francis, 2012. [143] E. Ibaragi, A. Hyogo, and K. Sekine, "A very high output impedance tail current source for low voltage applications," IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol. 83, no. 2, pp. 204-209, 2000. [144] F. You, H. K. Embabi, J. F. Duque-Carrillo, and E. Sanchez-Sinencio, "Am 191

improved tail current source for low voltage applications," IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1173-1180, 1997. [145] U. Yilmazer, C. Yilmazer, and A. Toker, "Design and comparison of high bandwidth limiting amplifier topologies," in 2015 9th International Conference on Electrical and Electronics Engineering (ELECO), 2015, pp. 66-70. [146] M. Farazian, L. E. Larson, and P. S. Gudem, Fast hopping frequency generation in digital CMOS. Springer Science & Business Media, 2012. [147] A. Devices, "Analog Switches and Multiplexers Basics," ed, 2009. [148] Y. Li, D. Yang, F. Liu, Y. Cao, and C. Rehtanz, Interconnected Power Systems: Wide-area Dynamic Monitoring and Control Applications. Springer, 2015. [149] V. Barkhordarian, "Power MOSFET basics," Powerconversion and Intelligent Motion-English Edition, vol. 22, no. 6, 1996. [150] C.

Wie.

(2018).

Available:

http://jas.eng.buffalo.edu/education/mos/mosfet/v10/mos_2/intro.html [151] N. D. Arora, MOSFET models for VLSI circuit simulation: theory and practice. Springer Science & Business Media, 2012. [152] L. Ramezani, "A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion (PDF Download Available)," ed, 2018. [153] G. Cornetta, Wireless Radio-Frequency Standards and System Design: Advanced Techniques: Advanced Techniques. IGI Global, 2012. [154] I. R. M. Association, Nanotechnology: Concepts, Methodologies, Tools, and Applications. IGI Global, 2014. [155] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis \& Design. McGraw-Hill, Inc., 2003, p. 672. 192

[156] J. Park and S. Mackay, Practical data acquisition for instrumentation and control systems. Newnes, 2003. [157] H. Uhrmann, R. Kolm, and H. Zimmermann, Analog filters in nanometer CMOS. Springer Science & Business Media, 2013. [158] W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits: A Special Issue of Analog Integrated Circuits and Signal Processing An International Journal Volume 8, No. 1 (1995). Springer Science & Business Media, 2012. [159] S. Sakurai and M. Ismail, Low-voltage CMOS operational amplifiers: Theory, Design and Implementation. Springer Science & Business Media, 2012. [160] W. Sansen, "Rail-to-rail input and output amplifiers," in Analog Design Essentials: Springer, 2006, pp. 301-336. [161] J. Citakovic, I. R. Nielsen, J. H. Nielsen, P. Asbeck, and P. Andreani, "A 0.8V, 7μA, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18μm CMOS," in 2005 NORCHIP, 2005, pp. 54-57. [162] H. Hong-Yi, W. Bo-Ruei, and L. Jen-Chieh, "High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit," in 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp. [163] R. Beal, A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness. Iowa State University, 2009. [164] R. Hogervorst, J. P. Tero, R. G. Eschauzier, and J. H. Huijsing, "A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries," Solid-State Circuits, IEEE Journal of, vol. 29, no. 12, pp. 1505-1513, 1994. [165] W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, "Digital-compatible high-performance operational amplifier with rail-to-rail input and output 193

ranges," Solid-State Circuits, IEEE Journal of, vol. 29, no. 1, pp. 63-66, 1994. [166] J. H. Huijsing, R. Hogervorst, and K.-J. De Langen, "Low-power low-voltage VLSI operational amplifier cells," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications [see also Circuits and Systems I: Regular Papers, IEEE Transactions on], 42 (11), 1995. [167] S. Sakurai and M. Ismail, "Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage," Solid-State Circuits, IEEE Journal of, vol. 31, no. 2, pp. 146-156, 1996. [168] J. Botma, R. Wassenaar, and R. Wiegerink, "A low-voltage CMOS op amp with a rail-to-rail constant-g m input stage and a class AB rail-to-rail output stage," in Circuits and Systems, 1993., ISCAS'93, 1993 IEEE International Symposium on, 1993, pp. 1314-1317: IEEE. [169] R. Hogervorst, R. J. Wiegerink, P. A. De Jong, J. Fonderie, R. F. Wassenaar, and J. H. Huijsing, "CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage," Analog Integrated Circuits and Signal Processing, vol. 5, no. 2, pp. 135-146, 1994. [170] R. Hogervorst, S. M. Safai, J. P. Tero, and J. H. Huijsing, "A programmable 3V CMOS rail-to-rail opamp with gain boosting for driving heavy resistive loads," in Circuits and Systems, 1995. ISCAS'95., 1995 IEEE International Symposium on, 1995, vol. 2, pp. 1544-1547: IEEE. [171] G. Ferri and W. Sansen, "A rail-to-rail constant-g m low-voltage CMOS operational transconductance amplifier," Solid-State Circuits, IEEE Journal of, vol. 32, no. 10, pp. 1563-1567, 1997. [172] F. Yuan, CMOS circuits for passive wireless microsystems. Springer Science & Business Media, 2010. [173] L.-P. LOW-VOLTAGE, "AN INTRODUCTION TO LOW-VOLTAGE, LOWPOWER ANALOG CMOS DESIGN." 194

[174] M. Borhani and F. Razaghian, "Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation," in Proceedings of the International MultiConference of Engineers and Computer Scientists, 2010, vol. 2: Citeseer. [175] R. Hogervorst and J. H. Huijsing, "An Introduction to Low-voltage, Low-Power Analog CMOS Design," ed: Kluwer Academic Publishers, 1996. [176] J. Citakovic, I. R. Nielsen, J. H. Nielsen, P. Asbeck, and P. Andreani, "A 0.8 V, 7μA, rail-to-rail input/output, constant G m operational amplifier in standard digital 0.18μm CMOS," in 2005 NORCHIP, 2005, pp. 54-57: IEEE. [177] P. Lo, "A fully differential CMOS operational amplifier implemented with MOS gain boosting technique," Texas Tech University, 1996. [178] L. Luh, J. Choma, and J. Draper, "A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application," in 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), 1998, vol. 3, pp. 347350 vol.3. [179] O. Choksi and L. R. Carley, "Analysis of switched-capacitor common-mode feedback circuit," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 12, pp. 906-917, 2003. [180] L. Yonggen, Z. Chenchang, Y. Tak Sang, and K. Wing-Hung, "Continuous-time common-mode feedback detection circuits with enhanced detection accuracy," in 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012, pp. 1-4. [181] E. Sánchez-Sinencio, "Common-Mode Control Techniques for Low Voltage Continuous-Time Analog Signal Processors," Texas A&M University Analog and Mixed-Signal Center Dept. of Electrical Engineering, College Station, TX, vol. 77840, 2000. 195

[182] P. Harikumar, "Building Blocks for Low-Voltage Analog-to-Digital Interfaces," 2014.

196

- Publications Publications summary Book chapters 1

Operational amplifier design in CMOS at low-voltage for sensor input front-end circuits in VLSI devices

Journals 1

RGB LED driver circuit design for an optical fiber sensor system

2

Rail-to-Rail Op-Amp Design Incorporating Negative Miller and Miller Compensation

Conferences

1

RGB LED driver circuit design for an optical fiber sensor system

2

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

3

Pole-Zero Estimation and Analysis of Op-Amp Design with Negative Miller Compensation

4

Programmable bandwidth operational amplifier with negative miller compensation

5

Programmable Gain and Bandwidth Op-Amp Using Controllable Input Stage Tail Current

6

Evaluation of Compensation Techniques for CMOS Operational Amplifier Design

7

Fully Differential Operational Amplifier Design Using Indirect and Negative Miller Compensation

8

Design and Performance Analysis of a Digitally Programmable Op-Amp

A-1

Book title

Very-Large-Scale Integration

Chapter title

Operational amplifier design in CMOS at low-voltage for sensor input front-end circuits in VLSI devices

Publisher

InTechOpen

Open Access Books homepage

www.intechopen.com

Print ISBN

978-953-51-3863-1

Online ISBN

978-953-51-3864-1

On-line access

https://dx.doi.org/10.5772/65525

DOI

10.5772/65525

Publication Date

28 February 2018

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract Today, digital circuit cores provide the main circuit implementation approach for integrated circuit (IC) functions in very-large-scale integration (VLSI) circuits and systems. Typical functions include sensor signal input, data storage, digital signal processing (DSP) operations, system control and communications. Despite the fact that a large portion of the circuitry may be developed and implemented using digital logic techniques, there is still a need for high performance analogue circuits such as amplifiers and filters that provide signal conditioning functionality prior to sampling into the digital domain using an analogue-to-digital converter (ADC) for analogue sensor signals. The demands on the design require a multitude of requirements to be taken into account. In this chapter, the design of the operational amplifier (op-amp) is discussed as an important circuit within the front-end circuitry of a mixed-signal IC. The discussion will focus on the design of the op-amp using different compensation schemes incorporating negative Miller compensation and designed to operate at lower power supply voltage levels. A design case study is included which utilises the gm/ID ratio design approach to determine the transistor sizes. The simulation approach is focused on the open-loop frequency response performance of the op-amp.

A-2

Paper title

RGB LED driver circuit design for an optical fiber sensor system

Journal

ECTI Transactions on Computer and Information Technology (ECTI-CIT)

ISSN

2286-9131

Published

27th December 2017

Journal homepage

http://www.ecti-eec.org/index.php/ecti-eec

On-line access

https://www.tci-thaijo.org/index.php/ecticit/article/view/63707

Authors

Ian A. Grout, Muhaned Zaidi, Karel L. Sterckx and Abu Khari bin A’ain

Abstract In this paper, the design of a programmable mixed signal electronic circuit to control the light output of a red-green-blue (RGB) light emitting diode (LED) to be used in an optical fiber sensor system is presented and discussed. The LED is to be used as a light transmitter (light source) within the sensor system design. The output of each LED color is to be independently controlled using either a d.c. current or a pulse width modulation (PWM) encoded current. This idea for, and architecture of, the mixedsignal electronic circuit design is considered for both a discrete implementation using off-the-shelf components and an application specific integrated circuit (ASIC) solution using a 0.35 µm complementary metal oxide semiconductor (CMOS) fabrication process. In this paper, the design operation principles, circuit architecture, simulation results and hardware requirements for this LED driver circuit are considered.

A-3

Paper title

Rail-to-Rail Op-Amp Design Incorporating Negative Miller and Miller Compensation

Journal

International Journal of Science and Engineering Investigations

Published

28th February 2018

Journal homepage

http://www.ijsei.com

On-line access

http://www.ijsei.com/papers/ijsei-77318-06.pdf

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract This paper considers and presents the design of a rail-to-rail input and output CMOS (complementary metal oxide semiconductor) two-stage operational amplifier (opamp). The design uses two capacitance based compensation techniques for controlling stability and frequency response, the conventional Miller and negative Miller capacitances. The negative Miller capacitance is constructed around the first amplification stage and the conventional Miller capacitance is constructed around the second amplification stage. By setting suitable capacitance values, the conventional Miller and negative Miller capacitances allow the designer to control stability margins and frequency response. The design is based on a low-power design where the first stage consists of complementary differential input and summing circuit, and the second stage is a class-AB amplifier. The design has been created using a 0.35 µm CMOS (n-well) technology, its operation strategy simulated using the Cadence Spectre simulator and operates on a +3.3 V power supply.

A-4

Paper title

RGB LED driver circuit design for an optical fiber sensor system

Conference

13th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)

Location

Chiang Mai, Thailand

Date

28th June – 1st July 2016

DOI

10.1109/ECTICon.2016.7561288

Publisher

IEEE

Authors

Ian A. Grout, Muhaned Zaidi, Karel L. Sterckx and Abu Khari bin A’ain

Abstract In this paper, the design of a programmable electronic circuit for a red-green-blue (RGB) light emitting diode (LED) to be used in an optical fiber sensor system is presented and discussed. The LED is to be used as a light transmitter (source) within the sensor system design. This idea and architecture for the mixed-signal electronic circuit design is considered for both a discrete implementation using off-the-shelf components and as an application specific integrated circuit (ASIC) solution using 0.35 µm complementary metal oxide semiconductor (CMOS) fabrication process. In this paper, the design operation principles, simulation results and the hardware requirements for this LED driver circuit are considered.

A-5

Paper title

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Conference

19th International Conference on Microelectronics, Nanoelectronics and Nanoengineering

Location

Prague, Czech Republic

Date

March 23 - 24, 2017

Publisher

World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering

Publication Date

March 2017

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage railto-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class-AB amplifier. The op-amps have been designed using a 0.35m CMOS fabrication process.

A-6

Paper title

Pole-Zero Estimation and Analysis of Op-Amp Design with Negative Miller Compensation

Conference

6th International Conference on Modern Circuits and Systems Technologies (MOCAST)

Location

Thessaloniki, Greece

Date

4-6 May 2017

DOI

10.1109/MOCAST.2017.7937617

Publisher

IEEE Xplore Digital Library

Publication Date

01 June 2017

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract In this paper, pole-zero estimation, analysis and simplification of the transfer function for a two-stage operational amplifier (op-amp) is presented. The circuit design considered is a folded cascode complementary metal oxide semiconductor (CMOS) op-amp incorporating both Miller and negative Miller frequency compensation. The design was created using a 0.35 µm CMOS fabrication process and analyzed for DC gain, unity gain frequency, gain margin, phase margin and open-loop pole and zero locations. Cadence Virtuoso was used for design entry and the Spectre simulator used for circuit level simulation studies. The extracted poles and zeros were used to create the circuit transfer function which was then analyzed using MATLAB. This allowed the transfer function to be simplified by reducing the numbers of poles and zeros for comparison with the frequency response of the original circuit. Finally, a Verilog-A model was created and compared to the original circuit and the MATLAB simulation study results.

A-7

Paper title

Programmable bandwidth operational amplifier with negative Miller compensation

Conference

2017 International Electrical Engineering Congress (IEECON)

Location

Pattaya, Thailand

Date

8-10 March 2017

DOI

10.1109/IEECON.2017.8075896

Publisher

IEEE Xplore Digital Library

Publication Date

23 October 2017

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract This paper presents a novel technique to design a programmable bandwidth singleended output CMOS operational amplifier using a serial digital interface. The circuit topology enables the programming of the value of a negative Miller capacitance around first amplification stage and programming of the value of a Miller capacitance around the second amplification stage. Therefore, a controllable frequency response op-amp is created that can be digitally controlled from a host digital processor. The design is based on a rail-to-rail output CMOS operational amplifier architecture where the first stage of the op-amp consists of differential input and folded cascode circuits, and the second stage is a class-AB amplifier. The design has been designed using a 0.35 am CMOS technology, its operation simulated using the Cadence Spectre simulator and operates on a +3.3V power supply.

A-8

Paper title

Programmable bandwidth operational amplifier with negative Miller compensation

Conference

2018 International Electrical Engineering Congress (iEECON)

Location

Krabi, Thailand

Date

7-9 March 2018

Publisher

IEEE Xplore Digital Library

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract This paper presents a novel technique to design a programmable open-loop DC gain and bandwidth single-ended output CMOS (complementary metal oxide semiconductor) op-amp (operational amplifier) using a serial digital interface. The circuit topology allows for the programming of the differential input stage tail current. With this variable tail current, a controllable open-loop DC gain and frequency response is created that can be controlled from a host digital processor. The op-amp circuit has a rail-to-rail output where the first stage of the op-amp consists of differential input and Folded cascode circuits that are compensated using a negative Miller capacitor, and the second stage is a class-AB amplifier compensated by a conventional Miller capacitor. The op-amp has been designed using a 0.35 µm CMOS technology, its operation simulated using the Cadence Spectre simulator and operates on a single-rail +3.3V power supply.

A-9

Paper title

Evaluation of Compensation Techniques for CMOS Operational Amplifier Design

Conference

International Conference on IC Design and Technology (ICICDT 2018)

Location

Otranto, Italy

Date

June 4th–6th, 2018

Publisher

IEEE Xplore Digital Library

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract This paper presents and compares two CMOS (complementary metal oxide semiconductor) operational amplifier (op-amp) designs. Each op-amp is based on a two-stage rail-to-rail output where the first stage is a differential input with folded cascode and the second stage is a class-AB amplifier. Each op-amp design incorporates different compensation techniques. The first op-amp uses negative Miller compensation around the first stage and conventional Miller compensation around the second stage. The second op-amp also uses negative Miller around the first stage, but with indirect Miller between the output and cascode node of the first stage. The purpose of this work was to evaluate the DC gain, unity gain frequency (UGF) and phase margin (PM) achieved using the different compensation techniques in simulation and test results from physical prototype devices using a 0.35 μm CMOS technology when operating on a single rail +2.5V and +1.8 V power supply.

A-10

Paper title

Fully Differential Operational Amplifier Design Using Indirect and Negative Miller Compensation

Conference

443rd International Conference on Recent Innovations in Engineering and Technology (ICRIET 2018)

Location

Phuket, Thailand

Date

6th - 7th July, 2018

Publisher

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract This paper presents the design and analysis of a fully differential operational amplifier (op-amp). The amplifier architecture is based on the two-stage op-amp architecture with compensation around each amplification stage. The design operates on a +3.3 V single-rail power supply voltage operation and has been designed using a 0.35 μm CMOS technology. The consideration in choosing the internal compensation method was based on analysis of the op-amp’s frequency response and stability margins. To improve stability, indirect compensation is applied around the second stage of the amplifier architecture. To improve frequency response, negative Miller compensation is applied around the first stage with the aim to reduce the effect of the amplifier input capacitance. The other important influence on performance considered is temperature. The op-amp shows a better performance at lower temperatures whereas the performance reduces at higher temperatures. The design was simulated with a variation of temperature in the range of -40 C to 125 C. The validation strategy was based on simulation using typical, worst-case power and worst-case speed device models using the Cadence Spectre circuit simulator.

A-11

Paper title

Design and Performance Analysis of a Digitally Programmable Op-Amp

Conference

7th International Conference on Intelligent and Advanced System (ICIAS 2018)

Location

Kuala Lumpur, Malaysia

Date

August 13th- 15th 2018

Publisher

IEEE Xplore Digital Library

Authors

Muhaned Zaidi, Ian A. Grout and Abu Khari bin A’ain

Abstract In this paper, the design and simulated response of a digitally programmable operational amplifier (op-amp) is discussed. The purpose of this programming capability is to allow for the op-amp DC gain and frequency response to be controlled. This is attained by programming the transistor tail current in the differential input stage of the op-amp operating at an analog power supply voltage of +3.3 V. Serial peripheral interface (SPI) communications is used here to provide control of the opamp from an external digital host processor. The design is considered as a particular implementation of digital control of analog circuits. Examples of such digital control strategies of analog circuits are identified to create a context for this work before discussing and analyzing the op-amp design of concern in this work.

A-12

- MOSFET operations B.1 Large signal model B.1.1 When vGS < VT The p-n junctions are modelled between source-substrate and drain-substrate regions and are in series with the drain and source connections. These diodes block current from drain to source when VDS is applied (Figure B.1(a)). The space between the drain and source has a high resistance [149]. Figure B.2 presents the cut-off region. B.1.2 When vGS ≥ VT and vDS < vDS(sat) The connection between the source and drain region is established when a high enough number of electrons (or holes) accumulate near the surface of the substrate under the gate. The heavily doped n-type source and drain regions establish a thin conducting layer below the oxide identified as the channel and thus form a current flow from drain to source [60]. The channel conductivity creates by the effect of the electric field caused by the applied vgs. If a small voltage is applied between drain and source, current flows through the channel. When vGS ≥ vT and vDS < vDS(sat) = vGS - vT, the channel is continuous all the way from source to drain (as shown in Figure B.2). Thus, a nMOS transistor acts like a conductor (or resistor) whose conductance is related to the number of electrons generated at the source-end (and thus, inserted from the source into the channel) as shown in Figure B.1 (b). The channel charge density (Q) per unit area in channel length, where V(y) is the channel potential at direction y, and VT is the threshold voltage. |Q(y)| = W Cox ( vGS − v (y) − VT )

(B.1)

An electric field E through the length of the channel is given by: |E| =

∂v(y) ∂L

(B.2)

This electric field produces the channel electrons or holes to drift the drain with a velocity. Therefore, the velocity (v) is given by: Electron drift velocity (v) = μn |E| = μn B-1

∂v(y) ∂L

(B.3)

And the value of iD can be found by multiplying the charge per unit channel length (equation (B.1))by the electron drift velocity (equation (B.3)) and is given by: iD = |Q|. v

(B.4)

The drain current is given by: iD = [μn Cox W( vGS − V(y) − VT )]

∂v(y) ∂L

(B.5)

Integrate along the channel from 0 to L gives vDS

L

∫ iD ∂L = ∫ [μn Cox W( vGS − V(y) − VT )] ∂v(y) 0

(B.6)

0

Estimating the limits is given vDS

iD

W v(y)2 = μn Cox [( vGS − VT )V(y) − ] L 2 0

(B.7)

The drain current in the linear region is given by: iD = μn Cox

W vDS 2 [( vGS − VT )vDS − ] L 2

(B.8)

Where µn is the mobility and Cox is gate oxide capacitance per unit area, W/L is the ratio of the width and length of the channel of gate region (aspect ratio of device), V GS is gate-source voltage, VT is the threshold voltage, and VDS is drain-source voltage. B.1.3 When vGS ≥ VT and vDS ≥ vDS(sat) When vDS = vDS(sat), the drain end of the channel is just pinched off, as shown in Figure B.1(c), at this voltage, and the channel no longer acts as a resistor. The current is defined by the number of carriers that run into the channel at the source-end of the channel. When the substrate vDS = vGS -VT in equation (B.8), the saturated drain current, iD, is given by: iDS =

1 W μn Cox (vGS − VT )2 2 L

B-2

(B.9)

Figure B.1 Structure and operation of the MOSFET When vDS is highly sufficient to the inversion layer and does not increase overall path from source to drain. In this case, the channel charge stops to grow, causing the overall current to stay constant despite increasing in VDS (Figure B.1 (d)). At the end of the channel (pinch-off), all carriers are transported into the drain by the electric field [150]. The drain current iD increases slightly as vDS increases, because the increasing vDS reduces the channel length and this is called channel-length modulation (λ). Figure B.2 shows the iD as function of vDS for an nMOS transistor, in addition, presents the saturation region. iD =

1 W μn Cox (vGS − VT )2 (1 + λvDS ) 2 L

B-3

(B.10)

Figure B.2 iD versus vDS curve for the nMOS transistor B.2 Small signal model B.2.1 Transconductance A significant parameter in analogue circuit design is a device's transconductance (gm). The gm is an Alternating Current (AC) source small-signal model parameter of MOSFET (shown in Figure B.3). The voltage vGS controls the current from drain to source (iD) using a voltage controlled current source with gm [29]. The gm is the derivative of drain current (iD) with respect to the gate-source voltage (vGS) with a constant drain-source voltage (vDS). Additionally, the transconductance is given as: gm

1 W ∂ μn Cox ( vGS − VT )2 (1 + λvDS ) ∂iD L = = 2 ∂vGS ∂vGS g m = μn Cox

W ( Vgs − VT )(1 + λVds ) L

(B.11)

(B.12)

Rewrite equation (B.10) and is given: (vGS − VT )2 =

2 iD W μn Cox L (1 + λvDS ) B-4

(B.13)

Equation (B.10) substrate in equation (B.12) and is given g m = √2iD μn Cox

W (1 + λVDS ) L

(B.14)

Equation (B.14) shows that the transconductance of MOSFET is proportional to the square root of the drain current. Furthermore, the transconductance is dependent on the device geometry (W/L) and drain current. In addition, gm can be expressed using the following equation: gm =

2iD 2iD = (vgs − VT ) veff

(B.15)

Where veff is overdrive voltage, which represents the voltage above the threshold voltage of the MOSFET.

Figure B.3 MOSFET test circuit B.2.2 Output conductance The MOSFET drain current is dependent on vDS and channel-length modulation (λ), thus is more accurately described in equation (B.9). The derivative of the small-signal drain current with respect to the small-signal voltage (vDS) and a constant gate-source voltage (vgs) provides the output conductance (gds) by: g ds

W ∂μn Cox L (vGS − VT )2 (1 + λvDS ) ∂iD = = ∂vDS ∂vDS

Solve equation (B.16) and is given:

B-5

(B.16)

g ds = μn Cox

W (V − VT )2 (1 + λVDS )λ L GS

(B.17)

Substrate (B.10) in eqaution (B.17) and gives: g ds = ID λ

(B.18)

The output resistance is considered to be the inverse of the output conductance: rds =

1 1 = g ds Id λ

(B.19)

In the saturation region, the output resistance is defined only by the drain current and λ. B.2.3 The voltage gain of the small-signal gain stage In the small-signal model in Figure B.3, the voltage gain can be calculated and can be defined as the ratio of the output voltage to the input voltage. Therefore, it is: 𝑣0𝑢𝑡 = − (𝑔𝑚 𝑣𝐺𝑆 𝑟𝑜 )

(B.20)

When vGS is operated as Vin and the voltage gain is the ratio of the output voltage to the input voltage, then 𝐴𝑉 =

𝑉0𝑢𝑡 = − (g m ro) 𝑉𝑖𝑛

(B.21)

Substrate equation (B.12) in equation (B.21), the voltage gain gives: 𝑊 𝐴𝑉 = − 𝜇𝑛 𝐶𝑜𝑥 ( ) ( 𝑣𝐺𝑆 − 𝑉𝑇 )(1 + 𝜆𝑣𝐷𝑆 )𝑟𝑜 𝐿

(B.22)

Thus, the gain can be increased by [151]: 1. Using a thinner gate oxide (tox), to increase Cox. 2. Using devices with higher carrier mobility (µ). Since the mobility of electrons is higher than that of holes, a nMOS transistor has higher gain compared to a pMOS transistor of the same size. 3. Using a larger channel width (W) and a shorter channel-length (L). When decreasing L.

B-6

B.3 gm/ID design technique charts B.3.1 gm/ID as a function of ID Figure B.4 presents gm/ID versus ID. In weak inversion, the gm/ID is a maximum value, whereas the drain current is minimal. Moreover, it moves down the curve when the drain current increases, that means that the amplifier ends up operating in strong inversion. The strong inversion region has a current larger than in the moderate or weak inversion. This region leads to a smaller size of device as well as to a decline of parasitic capacitances and a rise in the transconductance.

Figure B.4 Transconductance efficiency (gm/ID) chart B.3.2 gm/ID as a function of ID/ (W/L) The function of ID/(W/L) is usually called the normalised drain current (In), as shown in Figure B.5. It depends on the geometry of the MOSFET device (L-gate length and W-width). While increasing gm and keeping a high value of the gm/ID, the width should be increased by maintaining constant ID/(W/L) (accordingly gm/ID). Increasing W implies an increasing the parasitic capacitances and hence decreasing fT.

B-7

Figure B.5 gm/ID versus. normalised current (ID/(W/L)) for a nMOS transistor (ratio of W/L=10 µm /0.35 µm) B.3.3 gm/ID as a function of the transition frequency An important figure of merit for a MOSFET is the unity-gain or transition frequency (fT) shown in Figure B.6, and is given by: fT = From [152] CGB = WL (

CDEP n

gm 2π(CGB )

(B.23)

). Moreover, for gm from equation (2.19), the transition

frequency is given by: fT =

ID 2π(Vth WLCDEP )

(B.24)

In equations (B.23) and (B.24), the transition frequency rises with an increase in the transconductance and drain current. However, it also undergoes a reduction with increased dimensions and increased parasitic capacitances. gm/ID increases with gatesource voltage.

B-8

Figure B.6 gm/ID versus. transition frequency (fT) for an nMOS transistor (ratio of W/L=10 µm /0.35 µm) According to [153, 154], in strong inversion, the gate-source voltage is high, the transition frequency is high and reaches a few giga-Hertz while gm/ID is high. In weak inversion, the transition frequency is small, and it only reaches kilo-Hertz. Therefore, this chart (Figure B.6) shows a trade-off between the speed (related to transition frequency) and power (related to gm/ID or gate-source voltage).

B-9

B-10

- CMOS amplifiers C.1 Two-stage CMOS operational amplifier design C.1.1 MOSFET differential input stage Typically, integrated amplifiers have a differential input [42]. This differential input is usually called a differential transistor pair. The differential input pair mainly can be nMOS or pMOS transistors, and in Figure 3.2, consists of two nMOS transistors (M1and M2). These two transistors have identical size and the same value of drain current (bias current (IB)) (IB/2), which biases both transistors at the same time. Transistors M1 and M2 are operated in the saturation region and the currents passing through them are assumed to be dependent of the gate-source voltages. The substrate connection node can be connected either to the source or to VSS. The gates of M1 and M2 are considered the inputs signals IN+ and IN- and they convert a differential input voltage to an output current (single-ended output). When the gate potentials of M1 and M2 are equal, assuming both are operating in the saturation region, the maximum and minimum differential input voltage is as described as follows [80]. The maximum difference in the input voltages, vDImax (maximum differential input voltage), is found by connecting iD1 to IB (M1 conducting all the tail bias current) and iD2 to 0 (M2 off). The maximum voltage is given by: vDImax > vID

2IB L = √ μ. Cox . W

(C.25)

Where L is the gate length, W is transistor width, µ is carrier mobility, and Cox is the gate-oxide capacitance per unit area. The minimum differential input voltage, vDImin, is found by connecting iD2 to IB and iD1 to 0. The minimum voltage is given by: vDImim = −vDImax = vID = −√

2IB L μ. Cox W

(C.26)

C.1.2 Current mirror The current mirror uses the principle shown in Figure C.1. The drain of M6 is linked to the gate of transistor M5, and the gate-source voltage (VGS6) and drain-source voltage C-1

(VDS6) of M6 are equal to the gate-source voltage (VGS5) of M5. This connection is given drain-source current (I6) of output corresponding to the input current (I5).

Figure C.1 Structure of the mirror current The current of M5 (Iout) mirrors that of M6 (Iin). However, M6 is operated in the saturation region as the drain and gate are connected together and acts as a diode connection. The drain-source current is applied, and the ratio of the M5 and M6 is given by: I5 L6 W5 VGS5 − VT5 2 1 + λ VDS5 2K P5 = [ ] [ ][ ] I6 L5 W6 VGS6 − VT6 1 + λ VDS6 2K P6

(C.27)

Where, Kp is µ.Cox, and λ is channel-length modulation. According to the previous assumption that the two MOSFET are identical [58, 80], threshold voltages are equal, VT5 = VT6, VGS5= VGS6 =VDS6 as well the dimensions are matching, equation (C.27) is given as: I5 1 + λ VDS5 = [ ] I6 1 + λ VDS6

(C.28)

If assuming the λ is the same for both transistors, this equation will yield unity. If λ is not the same, the drain-source of both transistors can cause a deviation from the ideal unity current mirroring [80]. C.1.3 Active load stage The differential input is created by transistors M1 and M2 and connected to a current mirror formed using pMOS transistors, M3 and M4. The drain terminals of the input C-2

transistors are fed to drains of M3 and M4. Moreover, the drain-source current of M4 must be equal to M3 as they have the same dimensions (as a Figure 3.2 [155]). M3 is always in the saturation region due to the connection between the drain and gate, and the gate-source voltage VSG3 is the same value of the drain-source voltage VSD3. C.1.4 Common-source output stage The first stage provides a differential input with an active load. The second stage is designed as a common source amplifier (M7, M8), the connection between M2 and M4 feeds the input of the second stage and the nMOS transistor, M8 biases M7. Therefore, the input signal comes from the output of the first stage. The advantages of the second stage are: •

Enhancement in the gain of an amplifier.



Creation of a suitable environment for the compensation.



Enhancement of the output swing range.

C.2 Rail-to-rail input stage C.2.1 Rail-to-rail input stage with complementary differential pairs The key principle of operation of the op-amp input stage is to amplify a differential input voltage and to reject any common mode input voltage charges [156]. A significant specification of the input amplification stage is the common mode input range [35]. The common mode input range is the range of the input DC voltage level at which all transistors in the input stage are in their active [157] (saturation) region. The most common circuit design technique to realise an input stage for single supply (single-rail) op-amp uses a parallel connection of pMOS and nMOS transistors in a differential input stage configuration. This technique combines the benefits of both transistor arrangements to accomplish rail-to-rail input performance [72]. Both input transistor pairs can be arranged as shown in Figure C.2. A pMOS input pair is presented as M1M2 and a nMOS input pair as M3-M4. The input common mode voltage for the nMOS transistor pair is from the positive power supply voltage (VDD) down to (VGSn + Vds(sat)) above the negative power supply (VSS). This is the minimum voltage required to maintain the nMOS transistors in the differential pair and the tail current source

C-3

transistor (M7) in saturation. The common mode input voltage range for a nMOS transistor (Vcom,n) is given by: VSS + VDS(sat) + VGSn < Vcom,n < VDD

(C.29)

Vds(sat) is the drain-source saturation voltage of transistor M7 and VGSn is the gate-source voltage of the nMOS input transistor. A comparable analysis can be performed for the pMOS differential pair shown in Figure C.2. The range extends from (VSGp + VSD(sat)) below the positive power supply voltage down to the negative supply. This minimum voltage is required to maintain the tail current transistor (M6) in saturation. The common mode input voltage range of a pMOS input is given by: VSS < Vcom,p < VDD − VSD(sat) − VSGp

(C.30)

Where VSD(sat) of M6 is a minimum voltage between the transistor source and drain connections necessary for the transistor to operate in the saturation region, VSGp is the source-gate voltage of the pMOS input transistor. Combining both differential pairs to reach complementary input stage shown in Figure C.2, the common-mode input (Vcom) will vary as: VSS + VDS(sat) + VGSn < Vcom < VDD − VSD(sat) − VSGp

(C.31)

To ensure the Vcom can reach rail-to-rail, the minimum supply voltage must be at least [35, 158]: Vsup(min) = VSGp + VGSn + VSD(sat) + VDS(sat)

(C.32)

Figure C.2 Input common-mode range of a pMOS and nMOS transistor differential pairs with resistive loads C-4

The minimum power supply voltage (Vsup(min)) required to operate a MOSFET in saturation is usually formed by two parameters, the transistor threshold voltage VT and the saturation voltage. If the power supply voltage in equation (C.32) is this minimum value, the Vcom range will be identified by three regions of operation. These regions are also related to the MOSFET transconductance. The total transconductance (gmTOT) of the complementary stage in Figure C. 3 is shown in Figure C. 4 by the sum of the transconductances of the nMOS (gmN) and pMOS (gmP) differential pairs. While there are three different regions of operation to determine gmTOT as shown in Figure C. 4, the transconductance of the rail-to-rail CMOS input stage is a function of Vcom [159]: •

Low Vcom, only the p-channel input pair operates.



Intermediate Vcom, the p-channel, as well as the n-channel input pair, operate.



High Vcom, only the n-channel input pair operates.

Therefore, at least one of the two differential pairs will be active for any Vcom between the power supply rails. Assuming that the gmP and gmN are equal for the transistors operating in their saturation regions, an essential issue in the design of the simple complementary input stage shown in Figure C. 3 is that the gmTOT [35] is a result of the complementary input pairs working in the intermediate region. This is where both the pMOS and nMOS transistors contribute to the input stage transconductance. The gmTOT of the input stage in this region is given by: g mTOT = g mN + g mP = 2g m

(C.33)

Figure C. 3 Common-mode input range of a rail-to-rail input stage [35] C-5

The input stage transconductance can vary by a factor of 2 [158, 160] over Vcom and therefore frequency compensation cannot be optimised. Moreover, in the middle part of Vcom, both input pairs are active, and the sum of their drain currents is two times the current in the outer part of the Vcom when only one of the input pairs is active [161]. The variations of the total transconductance results alteration of the voltage gain, unity gain frequency, a non-constant slew rate, and non-optimal frequency compensation of opamps [162, 163] because it requires much more power. To achieve power-optimal frequency compensation, gmP and gmN must be controlled to be a constant value [164].

Figure C. 4 gmTOT versus the Vcom for a rail-to-rail complementary input [59] There are different techniques to operate input stages with a rail-to-rail common mode range and to equalise gmTOT. Approaches for balancing the gmTOT of the complementary input stage can be: •

Approach 1 [165, 166], for input stages with input transistors working in the weak inversion region, using a current complement circuit to keep the sum of IN and IP constant.



Approach 2 [167, 168], The input transistors work in strong inversion region. Using current square root circuit to (√𝑰𝑷 + √𝑰𝑷 ) keep gmTOT constant.



Approach 3 [164, 166, 169], for a MOS transistor working in strong inversion and saturation region, the square law applies, using current switches to change the tail current of input differential pairs Rail-to-Rail Input Stage,



Approach 4 [170], Another constant-gm input stage with a current-switch. When only nMOS (or pMOS) input pair works, activate another nMOS (or pMOS) pair to compensate for the transconductance loss. The structure has two nMOS pairs and two pMOS pairs. One nMOS pair (or pMOS pair) are normally biased. C-6

Although another nMOS pair (or pMOS pair), the backup pair, is biased by the current steered from the main pMOS pair (or nMOS pair) if the main pMOS pair cannot work the current properly may also be controlled by a current switch. •

Approach 5 [75], using an electronic Zener diode to keep (VGSN + VSGP) constant.



Approach 6 [171], using DC shifting circuit to change the input DC level.

For operating the transistor in weak inversion, gmTOT can be kept constant by keeping the sum of the tail currents constant, whereas in strong inversion, gmTOT can be maintained constant by keeping the sum of the gate-source voltages constant [59]. The gmTOT is possible when the transistors operate in three different inversion regions of saturation. These are defined as weak inversion, moderate inversion and strong inversion. In these regions that can be controlled by gmTOT as constant, as follows: 1. If the transistor operates in weak inversion, the total gm is given by: g m TOT =

Ip In + 2np Vth 2nn Vth

(C.34)

Where Vth is the thermal voltage kT/q, which is around 25.9 mV at room temperature (300 K) [172]. The values np and nn are the weak inversion slope factor for the pMOS and nMOS transistors respectively. In the weak inversion, gm can be controlled by changing the tail current of the input stage (complementary stage). 2. If the transistor operates in the strong inversion, the total gm can use the square law models that lead to the gmTOT: g mTOT

W W = √μn Cox ( ) In + √μp Cox ( ) Ip L n L p

W W g mTOT = μn Cox ( ) Vgsn eff + μp Cox ( ) Vsgn eff L n L p

(C.35)

(C.36)

In equations(2.10), (C.35) and (C.36), the gmTOT can be controlled by the tail current of the complementary input or by the transistor width (W) over length (L) ratios (i.e., the transistor dimensions) or by the gate-source voltage. 3. If the transistor operates in the moderate inversion, the total gm is controlled by the transistor in a region between the weak inversion (low current) and the strong inversion (high current). C-7

C.2.2 Constant-gm rail-to-rail input stage using a one-times current mirror The total transconductance can be controlled by the tail current of the complementary input (Figure C.5). The complementary input transistors can operate in strong, moderate or weak inversion. However, weak inversion operation would allow the potential to minimise the power supply voltage. To achieve a minimum power supply voltage, the input stage must operate its transistors in weak inversion. When the gm of a rail-to-rail input stage is working in weak inversion, the sum of tail currents of the complementary input (pMOS and nMOS) pairs used is constant [35, 75]. M1-M4 are complementary input pairs and a summing circuit consists of transistors M13-M18. gm control of the input stage is implemented by the current switch M5 and a current mirror using transistors M7-M8.

Figure C.5 gm control by a current switch and current mirror (1:1) [35] The value of the voltage V3 must be half of the supply, and the W/ L ratio of M5 has to be made small when compared to the input transistor dimensions [35, 173]. If the common mode input range voltage is increased, the current of the p-channel input pair (IREF) would be routed through the current switch to the current mirror and then feeds the n-channel input pair. The currents in the input stage obey to total gm as given by equation (C.34) when the gm of input stage is in weak inversion (Figure C. 6). Moreover, the transistors M1-M4 operate in weak inversion [174]. For achieving a high gm, the transistor of the input stage drain current must be increased. However, increasing this current may push the device into strong inversion, and this must be avoided to maintain C-8

low-voltage operation. However, the device may be keep in the low-voltage mode by modifying the W/L ratio, but the increased device geometries lead to increased device parasitic capacitances, thus affecting the high-frequency performance [173]. The key advantages of gm control by a current switch are [175]: 1. It has a small circuit size and low power consumption. gm control hardly increases the size of the input stage as the current switch and current mirrors are small [2]. 2. gm control does not increase the noise of the input stage as the noise generated by the gm control circuit is inserted into the tails of the complementary input pairs, and thus can be considered as a common mode signal.

Figure C. 6 gm versus Vcom for the rail-to-rail complementary input stage with gm control and without gm control C.2.3 Class-AB output stage The output swing of an op-amp describes how close the output of the op-amp can be operated to the negative or positive supply rails under defined operating and output load conditions [72]. The advantage of the class-AB output is that it is capable of operating at high-speed and close to the power supply voltage levels [70]. To achieve the rail-torail output, the output transistors M27-M28 in Figure C.7 must be in the common-source configuration with control transistors M19-M20 [164, 174, 176]. In Figure C.7, feed-forward class-AB control is achieved by transistors M19 and M20. These transistors are biased by two signal currents from cascode transistors M13 and M16, and their VGS values are kept constant by the connection of transistors M23-M24 and M25-M26. The floating current source (transistors M29-M30) has the same design C-9

as the feed-forward class-AB control, whose quiescent current is made less sensitive to supply voltage changes by using current mirrors biased independently. Therefore, transistors M17, M30, M25, M26 and M12, M29, M23, M24 generate two translinear loops that control the [59] value of the floating current source. The transistor coupled class-AB control is beneficial in that [35]: 1. Less noise additional DC offset voltage are added to the first stage of the amplifier. 2. An excellent high-frequency behaviour is accomplished due to the connection between the gates (M28 and M27) being achieved by a single transistor. 3. It should not reduce the open-loop gain of the amplifier. The class-AB control transistors do not decrease the gain of the first stage amplifier.

Figure C.7 Circuit diagram of the low-voltage class-AB output stage C.3 Fully-differential operational amplifier design C.3.1 Fully-differential operational amplifier design This section provides an analysis of the conventional fully-differential folded cascode structure whose circuit schematic is presented in Figure C.8. The nMOS current mirror can be presented one composed of M4 and M7, the other of M5 and M6. The commonmode feedback has been added as an extra circuit. Vcont of the CMFB circuit controls the mirror currents. The inputs of the CMFB circuit are also the differential outputs of the fully-differential amplifier. The CMFB circuit senses the average of these two C-10

outputs and pushes it to a value equal to a predetermined value [42], as described in the next section. The main concept of the folded cascode op-amp design is the utilisation of cascode transistors of opposite type (i.e., nMOS rather than pMOS and vice-versa) from those used in the input stage [42], as described in section 3.2.2. In the interior of a fullydifferential op-amp design, transistors M1 and M2 are pMOS whereas cascode transistors M6 and M7 are nMOS. This type of connection provides a high resistance output node and the transconductance for the cascode is also nearly equal to the transconductance of the input pair:

gm

Kp W = √2ID ( ) ( ) 2 L

gm2 ⁄ W L =( ) I 2 K p 2D

(C.37)

(C.38)

Where, kP is the transconductance parameter of the input stage transistor, ID is the current flowing through the input stage, and W/L is the ratio of the input device width (W) and length (L).

Figure C.8 Differential input folded cascode stage of the op-amp

C-11

C.3.2 Common-mode feedback amplifier The problem with using a fully-differential configuration is that the output commonmode level is not well-defined if the circuit is used in closed loop [177], as the DC level of common output voltage will not be the same for the differential output. To solve this problem, a common-mode feedback circuit is used to balance the common output voltage. There are three typical approaches taken to design CMFB circuits [178]: •

Switched-capacitor circuits are suitable only for sampled-data circuits. It suffers from clock-injected noise, and its application is limited to sampled data systems. Furthermore, it is sensitive to the power supply due to the power supply dependence on resistive of the switches [179].



Differential-difference amplifier circuits applied by differential-difference amplifiers use four matching transistors to average and compare the commonmode voltages. This desgin is more suitable for low power.



Resistor-averaged common-mode feedback circuits use resistors to average the two differential outputs, however, it suffers from large chip area due to the required for large resistors. It can also work with different supplies but it requires a significant resistance to maintain the high DC gain output swing [180].

The approach (differential-difference amplifier circuits) is aimed at the CMFB amplifier, there are different other topologies explained in the literature [42, 58, 83]. The utilisation of common-mode feedback has as purpose to [181]: •

Sense the common-mode output signals and compare it with the reference voltage (VCMRef).



Fix the DC operating point at the output that maximises the differential voltage gain.

Since the second approach needs a simpler structure, it is utilised in the design of the common-mode feedback circuit. Figure C.9 shows the circuit schematic which contains two differential pairs (Ml5, M16 and M17, M18) that are identical with the transistors of a current mirror load (M19, M20), and two tail current sources (M13 and M14) and are similar with the transistors M10-M11 of the main amplifier. In this circuit, the two differential pairs sum their differential currents into the current mirror load with the

C-12

output taken from M6. The common mode voltage is considered as a reference potential VCMRef, which is usually the analogue ground to maximise the output voltage swing. The differential pair output nodes of the fully-differential configuration are connected in such a manner that the CMFB circuit output voltage, denoted here as VCMRef, becomes a function of the difference between the common-mode output voltage and the reference voltage. VCMRef controls the current sources, M4 and M5, of the main amplifier which minimises the difference between the common-mode output voltage and VCMRef. If VCMRef increases, Vcont also increases, and as a result, the voltage fall across the cascode load (M4, 5 and M6, 7) increases, the DC level of both output voltages decreases, and thus the common-mode output voltage.

Figure C.9 Common-mode feedback circuit C.4 Miller capacitor Figure C.10 shows the small-signal model of the two-stage amplifier as shown in Figure 3.2 without compensation. The transconductance of the input stage (transistor M1) is (gm1 ≡ Gm1), R1 is the input resistance of the differential amplifier (R1= ro2 || ro4), and the total capacitance between first and second stage is C1 and given by: C1 = CDG4 + CBD4 + +CDG2 + CBD2 + CGS7

(C.39)

The transconductance of the second stage is Gm2 (gm2 ≡ gm6), R2 is the input resistance at the output node (R2 = ro7 || ro8), and the total capacitance C2 at the output node of the second stage is: C-13

C2 = CDB8 + CDB7 + CGS7 + CL

(C.40)

Considering the op-amp gain being represented as two poles open-loop transfer function, it is given by: Vout AV = A(s) = s s Vin (1 + p ) (1 + p ) 1 2

(C.41)

Where, AV is the op-amp gain and poles p1 and p2 are defined by the capacitances linked to the high impedance of the op-amp. In addition, the small-signal equivalent circuit of the two-stage amplifier is shown in Figure C.10 when p2 >> p1, which implies p1 is the dominant pole. And the small-signal analysis is presented by: AV = Gm1 Gm2 R1 R 2 , p1 =

Gm1 Gm2 , p2 = C1 CL

(C.42)

Figure C.10 Miller OTA small-signal model without compensation Figure C.11 shows the small-signal model with Miller capacitor and provides a feedback path for an op-amp. Cgd6 must include and be parallel with CC. The capacitor Cc is affected by the transfer function equation at node Vin, yielding: Gm1 Vin +

Vx + sC1 Vx + sCc (Vx − Vout ) = 0 R1

(C.43)

Writing a node equation at node Vout yields, Gm2 Vx +

Vout + sC2 Vout + sCc (Vout − Vx ) = 0 R2

Re-write a node equation at node Vout is given, Gm2 Vx +

Vout + sC2 Vout + sCc (Vout − Vx ) = 0 R2

From equations (C.43) and (C.44) to Find Vx Gm1 Vin +

Vx Vout + sC1 Vx + Gm2 Vx + + sC2 Vout = 0 R1 R2

C-14

(C.44)

Vx [

1 Vout + sC1 + Gm2 ] + Gm1 Vin + + sC2 Vout = 0 R1 R2 V − ( Gm1 Vin + Rout + sC2 Vout ) 2 Vx = 1 [R + sC1 + Gm2 ] 1 V −R1 ( Gm1 Vin + Rout + sC2 Vout ) 2 Vx = [1 + sC1 R1 + Gm2 R1 ]

Substrate Vx in equation (C.43) Vout 1 −R1 ( Gm1 Vin + R 2 + sC2 Vout ) Gm1 Vin + [ ] [1 + sC1 R1 + Gm2 R1 ] R1 Vout + sC2 Vout ) R2 ] [1 + sC1 R1 + Gm2 R1 ]

−R1 ( Gm1 Vin + + sC1 [

V −R1 ( Gm1 Vin + Rout + sC2 Vout ) 2 + sCc [ ] − sCc Vout = 0 [1 + sC1 R1 + Gm2 R1 ] x

Multiply by [1 + sC1 R1 + Gm2 R1 ], is given: Gm1 Vin (1 + sC1 R1 + Gm2 R1 ) − ( Gm1 Vin +

Vout + sC2 Vout ) R2

− sC1 R1 ( Gm1 Vin +

Vout + sC2 Vout ) R2

− sCc R1 ( Gm1 Vin +

Vout + sC2 Vout ) R2

− sCc Vout (1 + sC1 R1 + Gm2 R1 ) = 0 Gather terms for Vout and Vin Vout

1 R1 R1 − sC1 − s2 C1 C2 R1 − sCc − R2 R2 R2 ] = X [ s 2 Cc C2 R1 − sCc − s 2 Cc C1 R1 − sCc Gm2 R1 −sC2 +

Vin [Gm1 + sC1 R1 Gm1 + R1 Gm1 Gm2 − Gm1 − sC1 R1 Gm1 − sCc R1 Gm1 ] = Y

Vin [R1 Gm1 Gm2 − sCc R1 Gm1 ] = Y C-15

Y+X=0 Vin [R1 Gm1 Gm2 − sCc R1 Gm1 ] + Vout

Vout = Vin

1 R1 R1 −sC2 + − sC1 − s 2 C1 C2 R1 − sCc − R2 R2 R2 ] = 0 [ s 2 Cc C2 R1 − sCc − s 2 Cc C1 R1 − sCc Gm2 R1

[R1 Gm1 Gm2 − sCc R1 Gm1 ] 1 R + sC2 + sC1 + s2 C1 C2 R1 + sCc R1 + R [ 2 ] 2 s 2 Cc C2 R1 + sCc + s 2 Cc C1 R1 + sCc Gm2 R1

[R1 Gm1 Gm2 − sCc R1 Gm1 ] Vout = Vin 1 1 + sC2 R 2 + sC1 R1 + s2 C1 C2 R1 R 2 + sCc R1 + s2 Cc C2 R1 R 2 ] R2 [ +sCc R 2 + s 2 Cc C1 R1 R 2 + sCc Gm2 R1 R 2

Vout R 2 [R1 Gm1 (Gm2 − sCc )] = 1 + s(C2 R 2 + C1 R1 + Cc R1 + Cc Gm2 R1 R 2 + Cc R 2 ) Vin [ ] + s 2 R1 R 2 (Cc C2 + Cc C1 + C1 C2 )

sC R 2 R1 Gm1 Gm2 (1 − G c ) Vout m2 = Vin (R 1 + s(C1 R1 + C2 R 2 + Cc 1 + Gm2 R1 R 2 + R 2 )) [ ] + s 2 R1 R 2 (Cc C2 + Cc C1 + C1 C2 )

(C.45)

If s = 0, the ratio Vout/Vin = Gm1R1Gm2R2. If s ≠ 0, the op-amp has zero transmission caused by the Miller effect in the right half plane, which provides the transfer function: 1−

sCc Gm2 = 0, pz = sz = Gm2 Cc

(C.46)

If an op-amp has two poles, the denominator polynomial can be expressed as: Y(s) = (1 +

s s 1 1 1 ) (1 + ) = 1 + s ( + ) + s 2 ( ) p1 p2 p1 p2 p1 p2

(C.47)

If there is one dominant pole, p1 60°: 3. Choose Cc as 0.65 pF to calculate the current through M5 to meet SR specification. Calculate the current for each transistor according to the square root of drain current (saturation region) 4. Decide M1 and M2 size. 5. Determine M3 and M4 size. 6. Determine M5 and M6 size.

C-20

7. Find M7 size and the current through M8 by allowing the second pole to be equal to 2.2UGF. So gm2 > 10gm1. The OTA amplifier has been designed to operate for power supply of ± 2.5 V. The OTA op-amp design is constructed using the conventional design (strong inversion region). The transistor dimensions are based on the saturation region equation, showing the width and length of each transistor. C.4.2 Case-study simulation The two-stage amplifier was simulated using LTspice. The first design uses the equations to find the parameters as well as to make sure that the specifications yield the values precisely when extracting the parameters. Table C.1 and

Table C.2 show the comparison between the simulation and hand-calculation results. Figure C.15 shows frequency response, gain and phase plot, and the op-amp with and without compensation. At gain plot, -3 dB is shifted deep in the low frequency while the 0 dB keeps reducing. The phase shift varies between 0 ° and 180°, which means the Miller capacitance is added 90° while the op-amp contains compensation, and the phase shift is between 0° and 90°. Table C.1 Comparison between the simulation and hand-calculation results Parameters

Width (µm) M1=M2

M3=M4

M5=M6

M7

M8

Hand calculation

5.8935

0.4259

0.578

30.00

19.99

Simulation

5.89

0.43

0.578

29.70

20

Transconductance(µS) Hand calculation

5.29e-05

7.67e-06

2.35e-05

5.39 e-04 8.208e-04

Simulation

5.30e-05

7.66e-06

2.34e-05

5.36e-04

8.21e-04

Source-drain conductance Hand calculation

2.70e-08

1.35e-08

5.39e-08

9.56e-07

1.912e-06

Simulation

2.60e-08

1.33e-08

5.20e-08

9.21e-07

1.80e-06

C-21

Table C.2 Comparison between the simulation and hand-calculation results Parameters

Hand calculation

Simulation

DC gain (dB)

108.09

108.47

UGF (MHz)

12.977

12.097

First pole (Hz)

48.85

48.19

Second pole (MHz)

29.42

28.25

First zero (MHz)

131.24

120.97

4

3.8807

-1.67