Design and Integration Technology for Miniature Medical Microsystems C. Van Hoof1,2, H. Neves1, A.A.A. Aarts1,2, F. Iker1, P. Soussan1, M. Gonzalez1, E. Beyne1, J. Vanfleteren1, R.P. Puers2, P. De Moor1 1
IMEC, Kapeldreef 75, Leuven, B-3001, Belgium,
[email protected] 2 KULeuven, Kasteelpark Arenberg 10, Leuven, B-3001, Belgium
Abstract The electronic subsystem of wearable and implantable devices is constructed using board-level and package-level integration technology and this limits the achievable miniaturization. We will show that this limitation can be overcome by emerging wafer-level integration methods such as chip-in-wire technology. These technologies can even achieve mechanically bendable and stretchable subsystems. Introduction Today’s medical implants and emerging wearable diagnostics are advanced and highly specialized systems. Nevertheless, they rely on rather traditional system design and integration technology. The electronic subsystem of these devices is constructed using board-level and/or package-level integration. Although this has enabled a variety of diagnostic and therapeutic applications, the achievable miniaturization remains limited by the chosen integration technology. The use of advanced 2D and 3D wafer-level integration technologies such as those being developed for nanoelectronics integrated circuit applications, would enable a drastic further miniaturization of the electronic subsystem of these devices. It would also improve yield, testability and cost effectiveness. Alternatively, if this reduction in size is not essential, it would still free space for additional system functionality (sensing, actuation, wireless). It will be shown that emerging wafer-level integration methods such as chipin-wire technology and ultra-thin-chip embedding are resulting in much smaller subsystems that are mechanically bendable and that can even be mechanically stretchable. A driver application needing such mechanical flexibility is the cochlear implant and wafer-level integration technology for the creation of cochlear implants will be shown. Other applications such as neural recording and stimulation have a 3D shape and require out-of-plane solutions. We will also show an out-of-plane modular integration technology that allows the creation of multifunctional neural probes (electronic, sensoric, fluidic).
interconnecting the dies using a thin-film interconnect method similar to that of wafer-level packaging. This embedding method requires extreme thinning (down to 1015micron) and also requires a rather thick dielectric material (BCB, silicone, PI, ideally coated in a single step) to achieve moderate planarization. The aggressive thinning is done on carrier substrates by grinding followed by etching for damage removal (1). Our previous work and that of other groups has demonstrated that digital, analog and mixed-signal electronic circuits retain their functionality after extreme thinning and damage removal (2). The method we developed for chip embedding and interconnection is termed ultra-thin-chipstacking (UTCS). Extending this embedding technology to flexible electronics can be achieved by releasing the embedded chip stack from its carrier substrate. The result is a wafer-level chip-in-flex embodiment (UTCF). Both methods are in principle directly suitable for miniaturizing the electronic subsystem of implantable devices, provided the subsystem is still placed in a hermetic (e.g. Ti) enclosure.
Flexible and Stretchable Electronic Subsystems Drastic miniaturization can be achieved by embedding ultrathin dies in a dielectric matrix on a carrier wafer and
Fig. 1. Flexible chip embedding technology demonstrator consisting of an ultra-thin die interconnected to a flexible dielectric carrier. Top: detail of the pad to carrier interconnection, bottom: embedded die.
Passive electrode array
Meander 2
N leads (for N electrodes)
22 electrode pads
Control Unit
Active electrode array 22 distributed embedded ultrathin ICs
5 leads (for N electrodes) Control Unit
εpl=3.5 %
εpl=5.7 %
Fig. 2. Chip-Embedding and interconnection for stretchable subsystems. Left: FEM of interconnects with minimum plastic strain, right: interconnect demonstrator.
The materials themselves (BCB is used as dielectric material and Cu for chip-to-chip interconnect) nor their sealing properties lend themselves directly for implantable applications. For wearable systems, however, the method is well suited as the biocompatibility requirement is relaxed and these UTCF embodiments allow moderate flexibility as can be seen on Fig. 1. Wearable as well as implantable devices can benefit from a certain amount of stretchability. Such technique could enable more realistic “smart bandages” or smart monitoring patches. One of the critical factors is the stretchability of the interconnect metallization pattern as well as preventing stretching of the electronic dies (without compromising flexibility). We have shown through finite element modeling (FEM) and experimental validation that appropriate horseshoe-shaped meandering of multiple metallic conductors is able to allow for 40% stretchability in one direction with moderate plastic strain (3) (see Fig. 2). However, in practice wearable and implantable devices will be subjected to multiaxial deformations. Therefore biaxial deformation was studied using FEM. Lower strain values are obtained in comparison with the unaxial stressing (4). Wafer-Level Integration for Implantable Devices – Active Electrodes for Cochlear Implants In contrast to the above integration method which still requires subsequent first-level or second-level packaging for hermetic sealing, chip-in-wire integration aims to achieve biocompatible encapsulation directly within the integration process flow by limiting the material choices and encapsulating the electronic dies by a multiple layer stack of parylene-C, platinum and silicone. A driver application requiring such biocompatible flexible embodiment is the electrode array of a cochlear implant.
VDD , VSS , Clock , I/O , Fire/Test
Fig. 3. Schematic cochlear implant using passive electrode pads (top) and active electrodes with embedded ICs (bottom).
These systems provide direct electrical stimulation of the auditory nervous system inside the cochlea and act as an artificial ear for many hearing-impaired people (5, 6). Today, the implant inside the cochlea consists of a flexible strip with 22 stimulation electrodes that each stimulate a different location of the cochlea corresponding to a different frequency (see top of Fig. 3). Passive electrodes are used, consisting of a number of Pt electrodes each connected via an individual Pt wire to a control box outside the cochlea. The number of electrodes is limited because each electrode has its individual wire and this increases the cable diameter inside the cochlea. A new approach involves replacing the current passive electrode array by a wafer-level constructed active-electrode array with tiny stimulation circuit dies (see bottom of Fig. 3). This allows a reduction in the number of leads from the control box to the cochlea from 22 to 5, and a larger number of electrodes even becomes feasible. We have built up a wafer-based process flow to create such active electrodes. First the active wafer is thinned on a carrier to a final thicknes of approximately 15 micron. Subsequently it is transferred to a base wafer which has a sacrificial layer and patterned Pt electrodes. The individual active dies are then singluated using a sloped DRIE etch. This enables the subsequent deposition of a dielectric layer (for electrical isolation) and a Pt metallization. The latter serves both as an electrical interconnect (between the active dies and the backside electrodes) and as a biocompatible encapsulation. The dies are then embedded in Silicone material. After the deposition and patterning of Pt interconnects connecting the different dies, a second Silicone encapsulation layer is deposited. The patterning of the Pt metallization by lift off is simplified by the smooth slope. Releasing the dies from the carrier requires a sacrificial layer, which for reasons of biocompatibility was chosen to be Aluminum, a method based on the work by (8). Test chips as well as a linear array of active electrodes have been embedded in silicone (see Fig. 4) (9,10).
Active Probe Array Passive Probe Array
circuitry on monolithic base
Slim-base Modular Active Probe Array circuitry on hybrid base
circuitry on probe shaft
Fig 5. Probe array schematics. Left: passive probe array. Middle: Active probe array with significant probe height above the cortical surface. Right: proposed modular probe with distributed electronics.
Fig. 4. Chip-in-wire process. Top: Cross-section of the embedded dies. Bottom: Thin active dies encapsulated in platinum and embedded in a silicone matrix (left: side view, right: top view).
Modular Neural Probes Microprobe arrays are frequently used to record and or stimulate neural activity, especially for in-vivo measurements of the brain. Current silicon-based implantable neural probes for electrical recording and stimulation are implemented in mainly two fashions. 2D-probe monolithic arrays have been made with out-of-plane probes containing a single electrode per probe (11). Microprobes with multiple recording sites per probe have been realized as in-plane, comb-like 2D arrays. A drawback of the latter is that any support electronics (amplification, switching, etc) is implemented at the base of the probe since there is no virtually no area available on the silicon probe shaft itself (12); this approach significantly increases the probe height above the cortical surface, which constitutes a problem if the probe is to float with the brain in chronic applications. Fig. 5 shows the comb implementation as a fully passive device (left) and with integrated electronics (center). To combine the merits of both in-plane and out-of-plane approaches, we proposed and implemented a modular out-ofplane 3D-probe integration method where the active probes could be flip-chip mounted in a die-to-wafer fashion to a thin micromachined carrier backplane (see Fig. 5, right). This approach should also enable fluidic and sensoric probe integration. The probe die as well as the carrier backplane could be passive (electrodes, sensors, fluidic) or active CMOS circuitry.
In this method, the probe base consumes limited space beyond the implanted part of the probe array, and functions such as filtering, multiplexing and amplifying can be integrated into the slim base. This is a significant attribute for chronic applications, where a probe array should float with the brain without being pressed against the skull. The presented die-to-wafer approach realizes such slim-base embodiment by connecting the out-of-plane probes to an inplane base platform; in addition, it retains the possibility for electronic or sensoric functions. Fig. 6 shows the result after flip-chip integration of 4 sets of 4 neural probe dies to the slim base platform. Once the probe array is assembled the electrical connection is achieved. The electrical out-of-plane interconnects consist of gold clips that are extending over the edge of a cavity. The gold clips are 20 µm wide, 4 µm thick and are hanging over the cavity by about 20 µm. The cavity is 200 µm deep and acts as a socket or bay for the probes. Each bay features between 5 and 11 interconnects. The base of the probe array fits into the socket and ensures mechanical stability (see bottom of Fig. 6). The inside of the cavity as well as the base of the probe are covered with a passivation layer that ensures electrical isolation. To facilitate the perpendicular die-to-wafer assembly a dedicated tooling chuck has been made for a conventional flip-chip bonder (Karl Suss FC150). Electrical contact is established through mechanical caulking (13) when the overhanging gold clips are squeezed between the cavity wall and the contact pad of the base of the probe. Probe lengths range from 1 mm to 8 mm and a complete 4x4 array with flex connector is shown in Fig. 7. The passive probes feature only 5 electrode sites. To allow a better depth control and to enable fine positioning of the probes with respect to individual neurons, CMOS probes were designed that feature electronic depth control electronics (see Fig. 7, left). The 2 mm and 8 mm probes have 112 and 512 electrodes per shaft, respectively.
Fig. 7. Left: Photograph of a 1×4 active CMOS neural probe. Right: 4x4 probe array with flex connector prior to overmolding with silicone (bottom).
References (1)
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Fig. 6. Top: Detail of slim-base wafer with 16 cavities and overhanging interconnect clips. Bottom: Interconnection result of 4 sets of 4 neural probes to the slim-base platform wafer. The insert shows a detail of the interconnection clip.
By electronically scanning the electrodes, the best electrode locations can be determined. The ease of fabrication using die-to-wafer integration combined with the modularity and the slim-base make this approach a powerful research tool for in vivo research, in which a large number of viable signals are simultaneously obtained. A low-power radio plus DSP System-in-Package are added to allow recording on freely moving subjects. Conclusion This paper summarizes ongoing developments for IC-centric wafer-level integration for smaller, flexible, and potentially more cost-effective wearable and implantable medical devices.
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Acknowledgments The contribution of the Department of Microsystems Engineering (IMTEK) of the University of Freiburg, Germany, for the probe process technology is acknowledged. Part of this work was performed in the frame of the Integrated Projects NeuroProbes and Healthy Aims of the 6th Framework Program (FP6) of the European Commission (Project numbers IST-027017 and IST-001837).
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