GA-Based Analog Synthesis of CMOS Power Amplifiers in the 2.45 GHz Band Aida A. El-sabban VLSI Design Center, AOIE Cairo, Egypt Email:
[email protected]
Ramy Iskander ECE Dept, Faculty of Engineering, Ain Shams University Cairo, Egypt
Hisham Haddara MEMScap Egypt Cairo, Egypt
Hani F. Ragai ECE Dept, Faculty of Engineering, Ain Shams University Cairo, Egypt
Abstract In this paper, an optimized design of a 0.8µm CMOS class AB power amplifier is presented. The optimization is carried out using a simulation-based optimizer whose kernel is based on genetic algorithms (GA). The PA delivers 20.1 dBm of output power to 50 Ω load with an efficiency of 49.3 % and PAE of 44.6 % at 3.3V supply. Keywords: CMOS RF Power amplifier, class AB, genetic optimization, VLSI design.
1
Introduction
A key component of the transceiver is the RF power amplifier (PA), which delivers modulated RF signals to the antenna with appropriate output power level. Its power consumption can potentially dominate that of the entire transceiver. Therefore, there is a need to design the power amplifier as efficient as possible while meeting the linearity limitations of the standard that is being implemented for [1] [2]. The aim of this work is to optimize the design of a class AB PA in the 2.45 GHz band. Section 2 describes the developed optimization tool (AMIGO) [3] interface. Section 3 will focus on the design of the PA using AMIGO. Finally the obtained results are discussed.
2
AMIGO
AMIGO stands for Analog Migration for ICs with Genetic Optimization. It is a simulation-based circuit-sizing tool based on genetic optimization techniques [4]. Given a certain topology, the designer
chooses the device parameters to be changed and the interdependency between the parameters. Then, the tool explores the design space formed by those parameters and selects the design point that best meets all the required specifications. The tuner interface of AMIGO consists of four panes. An Optimization Variables pane shows all the independent variables with their relevant information. A Constraints Specifications pane shows the designer’s supplied constraints and detailed information for each constraint. There is also an Objective Function pane that shows the progression of the cost function and a Waveform pane that allows the designer to view any output results. The tuner interface has two modes of operations: manual and automatic. In the manual mode, the designer specifies the variables values and then asks the tuner to evaluate all the constraints. By proceeding in this way, the designer can study the different tolerances in any given design. In the automatic mode, the designer fires the optimization engine to search for a solution in the design space. The input to AMIGO is an optimization file that describes all the information needed to guide the synthesis process. The input information is categorized in three categories: 1) Independent variables, where the designer specifies all the devices and the parameters that should be changed during optimization. 2) Variables dependency, that can be expressed in the input file (e.g. in matched transistors where variables assume exactly the same values during optimization). 3) Constraints on performance specifications that can be labeled and expressed using a simple syntax. The constraint statement describes the netlist to use during evaluation and the constraint
expression to calculate. The expression can rely on simulator capabilities, or it can be a userdefined function that is programmed by the designer to measure the specification. A framework has been developed to allow the designer to define complex functions using TCL/TK language [5]. This increases the abstraction of the functions and ensures their independence from the simulator. The tool uses an interface developed over EXPECT [5] to encapsulate all the internal aspects of a simulation. Any waveform can be viewed on the tuner interface. Inspecting the outputs can be beneficial especially during the manual mode. Also, the convergence of the outputs to a given behavior can be inspected during automatic mode.
3
Design using AMIGO
A given topology (fig. 1) for a CMOS power amplifier class AB has been tentatively designed in the 2.45GHz band, using 0.8µm CMOS low-cost standard technology at 3.3 V supply. The simulation is carried out using ELDO RFIC [6-8]. The target main specifications are: output power ≥ 20dBm, efficiency ≥ 40% and output voltage THD ≤ 10%. In this tentative design, the coil model is taken as simple as possible. The same architecture is then redesigned using AMIGO. The output of the synthesizer is a set of optimized parameters including the transistor size and the component values that satisfy the main target specifications for the chosen class AB operation. More constraints including the power gain, power added efficiency and tuning frequency are also taken into account. VCC
Specifications
Tentative Design 20.2dBm
AMIGO Design 20.1dBm
Target
Output power ≥ 20dBm (Pout) 33.3% 49.3 % Efficiency (η) ≥ 40% Power added 30.9% 44.6 % ≥ 35% efficiency (PAE) -34dB -19.1dB Reflection ≤ -10dB coefficient (S11) Gain (Gp) 10.3dB 10.14dB ≥ 8dB Power 200mW 130mW Low consumption THD% of the 7.3% 10 % ≤ 10% output voltage Table 1. Specifications before and after synthesis
Pin(dB)
Figure 2. Delivered output power versus input power
Lblock Cblock
Matching Cblockip network
Transformation network
M1
Rbias
Ltune
Ctune
Vout
50 ohm
VIN
0
Vbias
0
0
Fig. 4 shows the power gain as a function of the input power while the last figure (fig. 5) presents the efficiency and PAE curves. It can be seen from this graph that η and PAE have improved and exceeded the target specifications when using AMIGO.
0
Figure 1. Simplified schematic for the power amplifier
4
Simulation results and discussion
The obtained specifications after the synthesis are given as follows (Table 1). Fig. 2 presents the delivered output power while S11 is shown in fig. 3. The figure indicates excellent match between the PA input and the standard 50Ω load. F(Hz)
Figure 3. S11 as a function of frequency
5
Conclusion
A class AB 0.8µm CMOS power amplifier at 2.45GHz is presented. It was optimally designed using a developed simulation-based GA optimization tool (AMIGO). The power amplifier delivers an output power of 20.1dBm to the 50Ω load with an efficiency of 49.3 % and power added efficiency of 44.6 % at 3.3V supply. The consumed power is 130 mW. This amplifier has the potential to work as class1 bluetooth PA if a power control feature is added. Including the on-chip coil into the synthesis flow will be implemented to improve the potential of the developed synthesis tool in such applications. Pin(dB)
Figure 4. Power gain versus input power
Pin(dB)
Figure 5. η and PAE versus input power The values of most of the components has been reduced after synthesis (see Table 2) and found suitable for full integration on a single chip except Lblock (unless multi-level metalization is used). The reduced width of the transistor is likely responsible for the obtained reduction in the power consumption.
Component
Tentative Design 2000µ 13pF 15pF 33nH 2nH 2.1pF 10k 1.24V 200mW
AMIGO Design 1520µ 17.2pF 11.4pF 37nH 1.2nH 1.1pF 8.9k 1.19V 130mW
W(M1) Cblock Cblockip Lblock Ltune Ctune Rbias Vbias DC Power consumption Table 2. Initial and final components values
References [1] Thomas H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, first edition, 1998. [2] S. C. Cripps, RF Power Amplifiers for Wireless Communication, Artech House, first ed., 1999. [3] R. Iskander , M. Dessouky et al, “Synthesis of CMOS analog cells using AMIGO“, Accepted for presentation in DATE’03, Munich, March 2003. [4] D.E.Golberg, Genetic Algoritms in Serasrch Optimizatuin and Machine Learning, Addison-Wesley.1989 [5] J.K.Ousterhout, ed., Tcl and the Tk tool kit, Addison-Wesley , 1994 [6] M. Hella, CMOS Radio Frequency Power Amplifiers for Short-Range Wireless Standard, Ph.D. thesis, Ohio State University, 2001. [7] M. Hella and M. Ismail, “A Digitally controlled RF CMOS power amplifier”, Midwest CAS conf., (Dayton, Ohio), Aug. 2001. [8] S. Yoo, H. Ahn, M. Hella and M. Ismail, “The design of 433 MHz class AB CMOS power amplifier”, in 2000 Southwest Symposium on Mixed Signal Design, pp 26-40, Sept. 2000.
