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Jan 20, 2011 - Design applications of compact MOSFET model for extended temperature range. (60–400K). Z. Zhu, A. Kathuria, S.G. Krishna, M. Mojarradi, ...
Design applications of compact MOSFET model for extended temperature range (60– 400K)

of this type, the PSP model becomes valid for the extended temperature range without any further changes in the model formulation.

Model: As demonstrated elsewhere [6, 7], there is no freezeout in the channel region of the MOSFET operating in strong inversion at cryogenic temperatures. However, freezeout exists in the neutral (‘bulk’) region and affects MOSFET characteristics, especially in the weak inversion regime. This can be included in the MOSFET model by changing the surface potential equation (SPE) to account for the incomplete impurity ionisation [3, 4]. Apart from the details of the gate capacitance Cgg(Vgs) behaviour in a narrow region near the flat-band voltage Vfb [4], the main effect of the neutral region freezeout is to delay the formation of the inversion region by about 20 –30 mV at 60 K in terms of the gate drive relative to the model based on the conventional SPE. Since this shift is readily accounted for by modifying the temperature dependence of the Vfb , the inclusion of the modified SPE in the compact model, while perfectly possible, is not really necessary for most applications. From the practical point of view it is much more important to introduce more detailed temperature scaling equations covering the whole 60 – 400 K temperature range and to ensure that evaluation of the expressions containing ubiquitous Boltzmann factors like exp(−qVds /kB T ) or exp(−qcs /kB T ) (where cs is surface potential) is carefully ordered and is compatible with the model convergence in the extended temperature range. For example, in PSP the mobility model includes the effects of surface phonon scattering, surface roughness and Coulomb scattering via the semi-empirical equation m0 m= (1) b 1 + (mE Eeff )um + C qbq+q i where m0 is the low field mobility, mE and um are the model parameters for vertical field dependence which combines surface roughness scattering and surface phonon scattering mechanisms, C is the model parameter quantifying the effect of Coulomb scattering (critical for the cryogenic operation), and qi and qb are normalised inversion and bulk charge, respectively, at the ‘surface potential midpoint’ [2]. In the original PSP model the temperature variation of m0 is given by

m0 = m0 (T0 ) (T0 /T )s

(2)

where T0 ¼ 298 K is the reference temperature and s is a constant. To ensure the model’s accuracy for the extended temperature range it was found necessary to scale s with temperature using the quadratic form s = s0 + s1 (T /T0 ) + s2 (T /T0 )2

(3)

where the temperature coefficients s0 , s1 and s2 are model parameters extracted from the measured data. With relatively minor modifications

model Vth, V

Introduction: Two industry standard MOSFET models, BSIM [1] and PSP [2], are developed for the traditional temperature range (233– 400 K) and have no real capabilities below 200 K. Hence they are not directly applicable to circuit simulations in the extended temperature range which may include cryogenic temperatures. Recent progress in the formulation of the surface-potential-based approach [3, 4] enables simulations for the 60 – 400 K range that retain all the capabilities of the original PSP model including an extremely accurate and physical description of device characteristics and secondary effects in all regions of operation. This in turn supports the design of mixed signal circuits intended to operate in a wide temperature range [5]. This Letter contains the first description of the new model and its design applications.

measured

8

60 K gm, uA/V

An advanced MOSFET model for the 60 –400 K temperature range is developed starting with the industry standard PSP model. The new model is experimentally verified, implemented in a commonly used circuit simulator and tested for convergence. This provides a robust and accurate description of low temperature MOSFET characteristics, including analogue performance. Simulations on a switched-capacitor integrator design are performed to illustrate the capabilities of the new model and to justify a new design methodology for the extended temperature range.

Model validation: To validate the new version of the PSP model called PSP-E, experimental data were measured at four different temperatures, namely 298, 233, 133, and 60 K. At low temperature, for the same transistor under the same bias conditions, higher mobility and transconductance are expected owing to reduced scattering mechanisms [8]. Threshold voltage Vth , also increases as temperature is reduced. Simulation results for the 180 nm CMOS process are shown in Fig. 1 for the transconductance gm and Vth. The technology used for model verification is TowerJazz’s CA18 (180 nm CMOS) process. The same degree of accuracy has been observed for other device characteristics in the 60 – 400 K temperature range.

6

0.7 0.6 0.5

133

100 200 300 T, K

233

4

298

2

0 0

0.5

1.0

1.5

2.0

Vg, V

Fig. 1 Transconductance against gate bias for extended temperature range 60– 400 K Inset: Threshold voltage temperature dependence

To test the convergence of the model, it was coded in verilog-A and implemented in one of the commonly used circuit simulators. A 49-stage ring oscillator was simulated for multiple temperatures. The results for 60 and 298 K are shown in Fig. 2. As expected, the speed of the circuit increases at 60 K as a result of the increased current driving capability of MOSFETs.

298 K 60 K

2.0

1.5 Vout, V

Z. Zhu, A. Kathuria, S.G. Krishna, M. Mojarradi, B. JalaliFarahani, H. Barnaby, W. Wu and G. Gildenblat

1.0

0.5

0 0

5

10

15

20

25

time, ns

Fig. 2 Illustration of model convergence for 49-stage ring oscillator at 60 and 298 K

Circuit design application: The capabilities of the new model are further demonstrated by simulating a wide-temperature range opamp and switched-capacitor integrator (cf. Fig. 3). This circuit is designed to be used in a 20-bit 1ksps sigma-delta ADC for spectroscopy in space. For this application linearity, DC accuracy and low noise are required for temperature ranging between 60 – 400 K. Several techniques are therefore implemented in the design to achieve this goal. The inset in Fig. 3, shows the wide-temperature range opamp design. The biasing circuit combines the traditional constant-gm biasing and an auxiliary slew rate enhancement circuit [5]. At low temperature, the increase in Vth shown in Fig. 1 results in reduction of the overdrive voltage and a drop in current while constant-gm biasing is used. This degrades the large signal performance of the opamp by reducing the slew rate. The slew rate enhancement circuit used in this design alleviates this problem by maintaining both large and small signal performances of the opamp at low temperatures.

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main opamp with constant-gm biasing vinp

Vin+

Vin–

f1

f2

Cs

f2

f1

f2

f1

f1

f2

f1

C0 f2

C0 f2

Cs

Cf

vinn

–+

vop

+–

von

+





+

PSP model as the special case corresponding to the 233 – 400 K temperature range. It has all the capabilities of the industry standard compact model (e.g. velocity saturation, quantum effects, polysilicon depletion, Coulomb scattering mode, etc.) and for the first time enables accurate circuit simulations which converge down to the liquid nitrogen temperature.

voutn

voutp

Vss Vdd

f1

+ –

Acknowledgments: This work is supported in part by the Jet Propulsion Lab under grant no. 1340201. We are grateful to TowerJazz for providing the test structures used in this study. Special thanks are extended to G. Dessai for reading the manuscript.

– +

Cf

slew rate enhancement auxiliary circuit Vss

Vdd

Fig. 3 Switched-capacitor integrator designed for high resolution sigmadelta ADC Inset: Opamp with uniquely designed slew rate enhancement block

Fig. 4 shows the simulation results for the differential output, Vop – Von , of the integrator when a DC input is applied for different temperatures in the range of 60 – 400 K. The gain of the integrator, formed by the ratio between the sampling capacitor Cs and the integration capacitor Cf , is 0.5. The use of the new model allows one to demonstrate that the performance of the integrator is fairly constant across the wide temperature range and proves the effectiveness of the novel biasing circuit used in the design of the opamp. 60 K/298 K/400 K

Vop−Von, V

Vinp−Vinn, V

0.04 0.02

0.05

DV = 10 mV

0.05 PSP−E, 60 K

0.1 0.05

10 mV

BSIM, 60 K

0 0.1 10 mV

Vop−Von, V

Vop−Von, V

0.1 0.05 0

PSP−E, 400 K 6

8 time, ms

10

BSIM, 400 K 7 mV

0.05 0

6

8 time, ms

Z. Zhu, A. Kathuria, S.G. Krishna, B. Jalali-Farahani, H. Barnaby, W. Wu and G. Gildenblat (Ira A. Fulton School of Engineering, Electrical Engineering, Arizona State University, Tempe, AZ 85281, USA) E-mail: [email protected] M. Mojarradi (Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Drive, Pasadena, CA 91109, USA) References

PSP−E/BSIM, 298 K 0.1

Vop−Von, V

Vop−Von, V

0 0.15

# The Institution of Engineering and Technology 2011 3 December 2010 doi: 10.1049/el.2010.3468

10

Fig. 4 Simulations on switched-capacitor integrator with PSP-E and BSIM models for extended temperature range 60– 400 K (expected DV is 10 mV for all temperatures)

Conclusion: The new PSP-based low temperature model is accurate in the extended temperature range 60 –400 K and includes the standard

1 Chen, Y.H., and Hu, C.M.: ‘MOSFET modeling and BSIM3 user’s guide’ (Kluwer Academic, Boston, MA, 1999) 2 Gildenblat, G., Wu, W., Li, X., Langevelde, R.V., Scholten, A.J., Smith, G.-J., and Klaassen, D.B.M.: ‘Surface-potential-based compact model of bulk MOSFET’ in Gildenblat, G. (Ed.): ‘Compact modeling: principles, techniques and applications’ (Springer, 2010) 3 Gildenblat, G., Zhu, Z., and McAndrew, C.C.: ‘Surface potential equation for bulk MOSFET’, Solid-State Electron., 2009, 53, pp. 11– 13 4 Zhu, Z., and Gildenblat, G.: ‘Symmetrically linearised charge-sheet model for extended temperature range’, Electron. Lett., 2009, 45, pp. 346– 348 5 Gopal Krishna, S., and Jalali-Farahani, B.: ‘A fast settling slew rate enhancement technique for operational amplifiers’. IEEE Int. Midwest Symp. on Circuits and Systems, August 2010, pp. 965–968 6 Gaensslen, F.H., Rideout, V.L., Walker, E.J., and Walker, J.J.: ‘Very small MOSFET’s for low-temperature operation’, IEEE Trans. Electron Devices, 1977, ED-24, (3), pp. 218–229 7 Gildenblat, G., and Nelson, D.E.: ‘Investigation of cryogenic CMOS performance’, IEDM, 1985, pp. 268–271 8 Gildenblat, G.: ‘Low-temperature CMOS’ in Gildenblat, G., Einspruch, N.G. (Eds): ‘Advanced MOS device physics’ (Academic Press, 1989)

ELECTRONICS LETTERS 20th January 2011 Vol. 47 No. 2