Design Considerations for Low-Power, High

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which achieves a power dissipation of 35 mW at full speed operation on a 3.3V ... sipation quadruples for each additional bit of resolution, and is independent of ...
Design Considerations for Low-Power, High-Speed CMOS Analog/Digital Converters Thomas B. Cho, David W. Cline, and Cormac S.G. Conroy*, and Paul R. Gray Department of Electrical Engineering and Computer Sciences, University of California, Berkeley * IBM Corporation, San Jose, CA Abstract This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter[1] implemented in 1.2-µm CMOS technology which achieves a power dissipation of 35 mW at full speed operation on a 3.3V power supply. I. Introduction Reduction of the power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes approaches for the low-power implementation of CMOS A/D converters in the sampling rate range above 5Msample/sec and for resolutions in the 8 to 12 bit range. In this range the applicable approaches are flash, 2-step flash, and pipeline configurations that achieve sample throughputs on the order of one sample per clock cycle. II. Fundamental Limitations to Power Dissipation The two fundamental operations in A/D conversion are sampling and quantization. For the sampling function, the minimum achievable power dissipation is set by the maximum value of the kT/C noise which will allow the achievement of the SNR required. This sets the minimum sampling capacitor value, which in turn sets the minimum power dissipation for a given sample rate assuming the capacitor must be completely discharged on each sample period. At room temperature this limit corresponds to about 0.2 µW per Msample/sec at the 10-bit resolution level, assuming the RMS thermal noise is set such that overall SNR is degraded by 1dB relative to the quantization noise level, and that the signal swing is equal to the supply voltage. The required power dissipation quadruples for each additional bit of resolution, and is independent of power supply voltage. This limit is about four orders of magnitude below the dissipation achieved in recently described high-speed A/D con-

verters[1][2][3][4][5][6]. In practice the S/H power is dominated by dissipation in the (usually class A) operational amplifier or buffer that drives the sampling capacitor in the sample and/or charge transfer modes. As a practical matter, power minimization in the sampling function translates to minimizing the power in the active circuitry driving the sampling capacitors whose kT/C noise limits the SNR of the converter. Thermal noise also sets a fundamental limit on comparator dissipation. In the comparator decision process, internal nodes of a regenerative circuit are initialized with a difference voltage equal to or proportional to the signal, and the circuit is placed in the regenerative mode and the final state is latched as determined by the polarity of the initialization voltage. The uncertainty of the outcome is determined by a number of non-idealities, one of which is the magnitude of the kT/C noise sample that is superimposed on the initialization voltage. Because of this noise and other practical factors such as charge injection, latch uncertainty tends to increase as the physical size of the latch devices is made smaller in order to reduce dynamic power dissipation in the latch. Most practical comparators utilize broadband gain stages before the regenerative latch to reduce the effect of latch uncertainty referred to the input of the comparator. However these gain stages dissipate large power compared to the CV 2 limit. Also, high speed A/D converters using flash or two-step flash architectures tend to use a large number of parallel comparators, and as a result comparator power dissipation is a large part of the overall power dissipation in such converters. Comparator power can be greatly reduced if larger input uncertainty can be tolerated. Fortunately, a number of A/D converter architectures have the property that the overall SNR, accuracy and linearity are relatively independent of comparator error. These include pipeline converters with digital correction and sigma-delta modulators. In these instances comparator power can be potentially made small compared to the power associated with the input S/H function. Because of the potential of error correction to reduce comparator power, the remainder of this paper concentrates on the pipeline architecture for its exploitation for low-power A/D converter implementation.

III. Power Minimization in Pipeline A/D Converters A block diagram of a typical pipeline A/D converter is shown in Fig. 1. It consists of a cascade of stages in which each stage performs a coarse quantization, a D/A function on the quantization result, subtraction, and amplification of the remainder. A sample/hold (S/H) function in each stage allows all stages to operate concurrently, giving a throughput of one output sample per clock cycle. Fig. 1 also illustrates a particular implementation of a pipeline stage in which the D/A, subtraction, amplification, and S/H functions are performed by a switched capacitor circuit with a resolution of 1.5 bits per stage and an interstage gain of 2. This particular configuration has proved particularly advantageous for low-power pipelines because the relatively low gain per stage allows the maximum uncertainty in comparator threshold and also allows the operational amplifiers to operate at low closed-loop gain for best settling at minimum power dissipation. In this example the D/A function is performed by two equal capacitors. When the input signal is applied, each stage samples and quantizes the signal to its per-stage resolution of 1.5 bits (i.e. 2 decision levels), subtracts the quantized analog voltage from the signal by connecting the bottom plate of capacitor CS to ±Vref or 0, and passes the residue to the next stage with amplification for finer conversion. The A/D block consists of two noncritical comparators resolving the input range into 3 segments. The input signal to the first stage is sampled simultaneously by the switched capacitor amplifier and by the comparators. This is made possible by the fact that digital correction allows comparator errors up to 1/4 full scale without degradation of linearity or SNR. The overall pipeline contains 18 comparators and 8 interstage amplifiers. IV. Power Reduction in SC S/H and Gain Blocks The power dissipation of the op amps in the pipeline is determined by the capacitive loading of each. Overall power dissipation can be substantially reduced by using the minimum possible value of capacitance at each point in the pipeline, as dictated by kT/C considerations. In this instance, total Vin

Stage 1

Stage N-1

1.5 bits

SH

+

Vout Vref CS

ADC

CF

Vin

x2

+

1.5 bits

- op amp +

DAC

1.5 bits

One important practical implication of the use of small capacitors in the first three stages is that the 0.1% matching in the D/A capacitors required for 10 bit INL will not be achieved in the as-fabricated state. Calibration circuitry has been incorporated into the first three stages to remove these mismatch errors [3]. This circuitry consists of a small T network of trim capacitors around the input sampling capacitor, and these are adjusted using standard pipeline self-calibration techniques at power-up. For a given resolution, the power dissipation in the interstage gain blocks is strongly dependent on both technology feature size and on power supply voltage. In high speed SC S/H-gain blocks, the speed required dictates the use of class A amplifier configurations. While slew rate is a factor, the principal limitation is the necessity of realizing sufficiently high device transconductance to achieve the required speed of small-signal settling. Scaling of technology results in smaller drain current at a given value of transconductance and input capacitance, giving lower power. Unfortunately, noise considerations require a square-law increase in sampling capacitor value with inverse supply voltage in order to maintain a constant ratio of kT/C noise to lsb value, which in turn tends to require a proportionate square law increase in amplifier device widths and bias current in order to maintain settling time constants at the required values. Thus this component of power tends to increase as power supply voltage decreases, at least in the speed range where class A circuits must be used.

DAC

Interstage Amplifier Vin

1.5 bits

Stage N

kT/C noise from all stages was chosen at 1/9 lsb RMS, corresponding to 0.6 dB decrease in overall SNR over and above that contributed by ADC quantization noise in the ideal case. For the case considered here, with operation on a 3.3 volt supply with ±1 volt internal signal swing, that resulted in the choice of a 390 fF sampling and feedback capacitor value (see Fig. 1) in the first stage, with scaling of that value down to 50fF sampling and feedback capacitors at the far end of the pipeline. This in turn allowed optimization of the power dissipation of each of the operational amplifiers in the pipeline taking into account the source, load, and feedback capacitors seen by each one, resulting in power dissipation ranging from 4.8mW in the first stage amplifier to 0.5mW in the last stage amplifier.

00 01 10

Low Resolution ADC

-Vref 1.5 bit flash ADC

Interstage Amplifier

Fig. 1. A typical pipeline A/D converter architecture.

Vout

V. Low-Power Dynamic Comparators In the example described here, the use of digital correction allows the use of comparators with up to ±250mV of input threshold uncertainty while maintaining full ADC SNR and linearity. It is also very desirable to incorporate the non-critical level generation function into the comparator structure. An all-dynamic circuit that realizes that is shown in Fig. 2. Here the lower set of NMOS devices operate in the triode region as the latch regenerates, steering the drain currents of the active switching NMOS devices to obtain a final

state as determined by the mismatch in the total resistance. Arbitrary noncritical thresholds can be set by properly ratioing the triode region devices. Of the 35mW total dissipation in the experimental A/D converter, at 20MS/sec rate, only 3.5mW was dissipated in comparators. latch/reset

Vref-

Vout+

Vin+ Vinw2 w1

C1

ts (sim. 0.1%) = 17ns CS = 390fF sw2

sw1

CF = 390fF

C2

CL = 1.8pF

latch/reset

Vref+

Vout-

Vout+

R1

R2

Pwr = 4.8mW

Vdd

Vdd

Vdd Vout-

Vdd Gain-boost Amplifier

Vdd = 3.3V

Vdd

C3

C4

Vout+

Av > 60dB Swing = ± 1V P-P

Vout-

Vin+

Vin-

Main Amplifier

w1 w2 Fig. 3. Op amp with gain-boost amplifier.

Fig. 2. Dynamic comparator with triode region level generation.

VI. Some Practical Aspects of Low Voltage Operation. The experimental device described here was intended for incorporation as a cell into complex mixed-signal ICs containing mostly digital blocks for DSP and control. As a result a 3.3 volt supply was chosen to be compatible with digital supplies in low-power systems. Operation at 3.3 V requires the solution of two problems. First, an op amp with an output swing that is a large fraction of the supply voltage, and with large enough voltage gain for the desired resolution, is required. Two- and three-stage amplifiers with various forms of miller compensation are possible solutions. However, the additional stages and associated current paths, as well as the necessity of adding additional capacitance for compensation, tends to result in higher power dissipation at a given settling time for these configurations as compared to a cascode configuration where compensation is performed by the load itself. For the moderate-gain performance required here, good results were obtained by using a cascode with a broadband low-gain preamplifier to add the required increment of gain, as shown in Fig. 3. Series feedback gain-boost amplifiers [7] are included in the PMOS current sources because in the particular technology used the PMOS devices displayed very low output resistance. These amplifiers are capacitively coupled into the signal path using level shift capacitors C1 and C2 which are initialized by closing switches SW1 and SW2. The common-mode feedback is also capacitive through C3 and C4. A second major problem in standard CMOS technologies is the fact that for 3.3 volt supplies transmission gates produce a high (or infinite) resistance region near the mid-supply voltage due to insufficient gate drive. Options for addressing this include modifying device thresholds in the technology or creating a boosted supply voltage for the switches using a charge pump. In this instance the charge pump approach[8] was used with the circuit shown in Fig. 4. By applying a square wave input signal of 3.3 V, C1 and C2 are self-charged to 3.3 V, and

an inverted square wave output of ≈5 V is generated. Because this gate voltage overdrive is much higher than the signal common-mode voltage (≈Vdd/2), sampling switches are implemented with NMOS switches only, and the parasitic capacitance from PMOS is eliminated. In this case individual charge pump circuits were used for each transmission gate or set of transmission gates using the same clock line to avoid the problem of crosstalk through the clock line. Vdd = 3.3 V ~5V! C1

C2

0

NMOS only! 3.3 0 Fig. 4. A charge pump circuit

VII. Experimental Results An experimental prototype[1] of the A/D converter was fabricated in a 1.2-µm, double-poly, double-metal CMOS technology. Chip area not including the pad ring is 3.2 x 3.3 mm2. A die photo is shown in Fig. 5. Fig. 6 shows the probability of getting a code i vs. the DC input voltage near the code transition. The extracted total input-referred RMS noise voltage from this plot was ~220µV while the designed value was 216µV. This confirms the kT/C noise-limited design in the prototype. In Fig. 7, SNDR is plotted for 100 kHz and 10 MHz input frequencies at 20-MS/s conversion rate. The peak SNDR is 59.1 dB for 100 kHz input sine wave. Fig. 8 shows the measured power consumption vs. the sampling frequency on a log-log scale. At reduced op amp bias current and a sampling frequency of 1 MS/s, the power consumption was 2.8 mW with SNDR of 58 dB.

Key performances are summarized in Table 1. VIII. Summary and Discussion Optimization of circuit and architecture configurations in pipeline A/D converters can yield major improvements in power dissipation. It appears likely that further power reductions are possible through a number of approaches, including increasing the signal swing much closer to the supply rail to maximize the signal level over kT/C noise floor. Signal swing was only 1 volt in the prototype due to the limited swing of the op amps. Scaling of technology will also provide power dissipation improvement. Realization of the gain block functions in a class B mode using charge domain switching or some other approach could also yield major improvements. Another issue is the relative benefit of even lower supply voltages. Operation at voltages in the 1 volt range will be desirable for compatibility with low-voltage systems, but is not likely to yield the same benefits in power dissipation as is the case for digital logic and memory, at least at resolutions of 10 bits and above, unless operation of the active amplifiers in class B mode can be achieved.

1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -1mV

Designed:(216µV)2 Measured:(~220µV)2 1mV 0mV 1LSB Vin - Vthreshold, code i

Fig. 6. Input noise measurement SNDR (dB) 60 55 50 45 40 35 30 25 20 -40 -30

ideal 100 kHz 10 MHz

-20 -10 0 Input level (dB) Fig. 7. SNDR vs. input signal level.

Table 1: A/D Performance: 3.3V and 25°C Technology Resolution Conversion Rate Active Area Input Range Input Capacitance Power Dissipation DNL/INL SNDR

1.2-µm CMOS 10 b 20 MS/s 3.2 x 3.3 mm2 ±1V 1 pF (single-ended) 35-mW* 0.5/0.6 LSB 59.1 dB (Fin = 100kHz) 55.0 dB (Fin = 10MHz)

*: Output pad driver power not included

Power(mW) 30 20 15 10 5 Fs (MS/s)

3 1

2 5 10 20 Fig. 8. Power vs. sampling frequency.

[2] S. H. Lewis, et al., “10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp.351-358, March 1992. [3] Y. M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5MHz self-calibrated pipelined A/D converter in 3-µm CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, Apr. 1991. [4] Matsuura, T., et al., “A 95-mW, 10-b 15-MHz low-power CMOS ADC using analog double-sampled pipelining scheme,” Symposium on VLSI Circuits Dig. Tech. Papers, pp. 98-99, Jun. 1992. [5] K. Kusumoto et al., “A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC,” in ISSCC Dig. Tech. Papers, pp.62-63, Feb. 1993. [6] K. Nakamura et al.,“A 85-mW, 10-bit 40-Ms/s ADC with decimated parallel architecture,” in Proc. IEEE Custom Integrated Circuits Conf., May 1994, pp23.1.1-23.1.4. Fig. 5. Die photo.

References [1] T. B. Cho and P. R. Gray, “A 10-bit, 20-MS/s, 35-mW pipeline A/D converter,” in Proc. IEEE Custom Integrated Circuits Conf., May 1994, pp23.2.1-23.2.4

[7] K. Bult and G.J.G.M. Geelen, “A fast-settling CMOS opamp with 90-dB DC gain and 116 MHz unity-gain frequency,” ISSCC Dig. Tech. Papers, pp. 108-109, Feb. 1990. [8] Y. Nakagome et al., “Experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circuits, vol. 26, pp. 465-472, Apr. 1991.