Design Considerations of Digitally Controlled LCL ... - IEEE Xplore

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 2, NO. 4, DECEMBER 2014

Design Considerations of Digitally Controlled LCL-Filtered Inverter With CapacitorCurrent-Feedback Active Damping Xuehua Wang, Member, IEEE, Chenlei Bao, Xinbo Ruan, Senior Member, IEEE, Weiwei Li, Student Member, IEEE, and Donghua Pan, Student Member, IEEE

Abstract— Due to the effect of the computation and modulation delays on the capacitor-current-feedback active damping, the digitally controlled LCL-filtered inverter tends to be unstable as the LCL-filter resonance frequency approaching to one-sixth of the sampling frequency. Therefore, to guarantee sufficient stability margins, the guideline for choosing the LCL-filter resonance frequency is proposed in this paper. After the resonance frequency is selected, a systematic design method is proposed to facilitate the selection of the proper controller parameters. With this design method, a satisfactory region of the controller parameters for meeting the system specifications is obtained, from which the proper controller parameters can be easily determined. Moreover, it is convenient and explicit to optimize the system performance according to the satisfactory region. A 6-kW prototype is built and tested. The simulation and experimental results validate the theoretical analysis. Index Terms— Active damping, digital control, grid-connected inverter, LCL filter.

I. I NTRODUCTION

N

OWADAYS, distributed power generation systems (DPGSs) based on wind energy, solar energy, and so on, gain much attention for their environmental friendly features [1]. As an interface between the DPGSs and the grid, pulsewidth modulation (PWM) grid-connected inverter feeds high-quality power into the grid through an L filter or LCL filter. Compared with the L filter, the LCL filter has higher ability of attenuating the switching harmonics, thereby

Manuscript received February 1, 2014; revised April 28, 2014 and July 3, 2014; accepted July 28, 2014. Date of publication August 21, 2014; date of current version October 29, 2014. This work was supported in part by the National Natural Science Foundation of China under Award 50837003 and Award 51007027, in part by the Jiangsu Province 333 Program for Excellent Talents under Award BRA2012141, and in part by the Fundamental Research Funds for the Central Universities under Award YAH12012. Recommended for publication by Associate Editor Luca Zarri. X. Wang, C. Bao, W. Li, and D. Pan are with the State Key Laboratory of Advanced Electromagnetic Engineering and Technology, Huazhong University of Science and Technology, Wuhan 430074, China (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). X. Ruan is with the State Key Laboratory of Advanced Electromagnetic Engineering and Technology, Huazhong University of Science and Technology, Wuhan 430074, China, and also with the Aero-Power ScienceTechnology Center, College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JESTPE.2014.2350262

Fig. 1.

Control structure of the LCL-filtered grid-connected inverter.

leading to a smaller size and lower cost [2]. However, the inherent resonance of the LCL filter might trigger undesired oscillation or even instability. To suppress the LCL-filter resonance, passive and active damping methods have been proposed [3]–[6]. Passive damping is performed by incorporating a resistor into the filter network [3], [4]. The damping resistor that is placed in parallel with the filter capacitor can effectively suppress the LCL-filter resonance without affecting its attenuating ability, but it results in considerable power loss [4]. To overcome this drawback, virtual resistor that mimics the physical one is proposed through proportional feedback of the filter capacitor current [5]. To differ from the passive damping method, the virtual resistor is called as the active damping method. Based on the concept of the virtual resistor, a step-by-step design method was proposed to determine the capacitor-current-feedback coefficient and the grid-current regulator parameters [7]. Given the specified steady-state error of the injected grid current, phase margin, and gain margin, a satisfactory region of the controller parameters is plotted, from which a group of optimized controller parameters can easily be picked out. This design method is straightforward, but it is performed without considering the delay effect, and thus it is not effective for digital control. In the digitally controlled system, the inherent computation and modulation delays will

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WANG et al.: DESIGN CONSIDERATIONS OF DIGITALLY CONTROLLED LCL-FILTERED INVERTER

Fig. 2.

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Linearized average model of the LCL-filtered inverter with capacitor-current-feedback active damping.

introduce an appreciable phase lag [8]–[11], which imposes severe limit on the control bandwidth. Moreover, these delays also have effect on the damping performance. As reported in [12], the capacitor-current-feedback active damping is equivalent to a virtual frequency-dependent resistor and a virtual frequency-dependent reactor in parallel with the filter capacitor. Due to the virtual reactor, the equivalent resonance frequency of the LCL filter is no longer fixed. When the equivalent resonance frequency is higher than one-sixth of the sampling frequency ( f s /6), the virtual resistor becomes negative at the equivalent resonance frequency, and the loop gain contains two right-half-plane (RHP) poles. Moreover, when the LCL-filter resonance frequency equals to f s /6, the system can be hardly compensated to be stable [13]. Thus, the design of a digitally controlled LCL-filtered inverter is far different from that of an analog-controlled one. This paper proposes a systematic design method, including a forbidden region for choosing the LCL-filter resonance frequency and the design procedure for determining the controller parameters. This paper is organized as follows. Section II briefly reviews the effect of the computation and modulation delays on the capacitor-current-feedback active damping. The stability constraints for different equivalent resonance frequency are given, and a forbidden region is deduced. While designing the LCL filter, it should keep the LCL-filter resonance frequency away from the forbidden region. Based on these stability constraints, some controller design considerations are summarized, and a step-by-step design method is proposed for the digitally controller LCL-filtered inverter in Section III. To verify the effectiveness of the proposed forbidden region and the step-by-step design method, a 6-kW prototype is fabricated and tested, and the simulation and experimental results are presented in Section IV. Finally, Section V gives the conclusion of this paper.

voltage loop [14], [15]. Since the bandwidth of the voltage loop is much slower than that of the grid current loop, it is reasonable to ignore the voltage loop and set I ∗ directly while designing the grid-current regulator. In Fig. 1, feedback of the capacitor current i c is used to damp the resonance of the LCL filter, where Hi1 represents the capacitor-current feedback coefficient. Ts is the sampling period. Note that the equivalent series resistors of the filter inductors and the filter capacitor are commonly very small, so they are ignored. In addition, the stability conditions become adverse if they are ignored. In general, the controller parameters, such as the current regulator G i (z) and the capacitor-current feedback coefficient Hi1 , of the digitally controlled LCL-filtered inverter can be directly designed in z-domain [10], [15]. Pole placement is usually used to achieve a good dynamic response. Meanwhile, the effect of the computation and modulation delays on the digitally controlled inverters can easily be studied in s-domain [12], [16]. For digitally controlled inverters, the PWM reference is commonly calculated in the current sampling period and it is updated until the next sampling time step. As a result, the computation delay happens. In s-domain, it is expressed as e−sTs . Since the PWM reference remains constant during one sampling period, the zero-order hold, i.e., (1 − e−sTs )/s is usually used to represent the modulation delay. In addition, the sampler is usually represented by 1/Ts [17]. Considering these three elements, the digitally controlled LCL-filtered inverter together with its control structure shown in Fig. 1 can be modeled as Fig. 2 [12], where K PWM is the transfer function of the PWM inverter. The expression is K PWM = Vin /Vtri , where Vin is the dc-link voltage and Vtri is the amplitude of the triangular carrier. In Fig. 2, G d (s) represents the transfer function of the sampler, the computation and the modulation delays [17], which is expressed as G d (s) =

II. M ODELING AND S TABILITY A NALYSIS OF THE D IGITALLY C ONTROLLED LCL-F ILTERED I NVERTER

1 1 − e−sTs ≈ e−1.5sTs. · e−sTs · Ts s

(1)

A. System Description

B. Reviewing the Effect of the Computation and Modulation Delays on Capacitor-Current-Feedback Active Damping

Fig. 1 shows a generic structure of the digitally controlled LCL-filtered inverter. The inverter-side inductor L 1 , the filter capacitor C, and the grid-side inductor L 2 compose the LCL filter. The grid current i L2 is regulated by the grid-current ∗ is determined by the regulator G i (z), and its reference i L2 amplitude I ∗ and the phase angle θ of the grid voltage vg . Hi2 is the feedback coefficient of i L2 . In general, θ is obtained by a phase-locked loop, and I ∗ is determined by an outer

As observed from Fig. 2, G d (s) is in the forward path of the capacitor-current-feedback loop, which means that the computation and modulation delays must affect the capacitor-currentfeedback active damping. A comprehensive investigation of the effect has been done in [12]. However, for the sake of the readability, a brief review is given in this paper. By replacing the feedback signal i c (s) with vc (s), and relocating its feedback node from the output of G i (s) to the

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Fig. 3.

Equivalent virtual impedance of the capacitor-current-feedback active damping in block diagram.

Fig. 4.

Bode diagrams of the loop gain T (s). (a) Case I. (b) Case II. (c) Case III.

input of 1/(sC), an equivalent block diagram is obtained, as shown in Fig. 3. The equivalent virtual impedance of the active damping can be expressed as L1 Z eq (s) = = Req //j X eq (2) K PWM C G d (s)Hi1 where Req and X eq are the virtual resistor and virtual reactor being connected in parallel with the filter capacitor. Furthermore, based on Fig. 3, a series of equivalent transformations can be fulfilled, which is shown in the Appendix. Then, the loop gain T (s) can be derived as T (s) =

G i (s)G d (s)Hi2 K PWM 2 s L 1 L 2 C s + C Z 1 (s) s + (2π fr )2 eq

(3)

where√fr is the resonance frequency of the LCL filter, i.e., √ fr = L 1 + L 2 /(2π L 1 L 2 C). It can be observed from (2) that due to X eq , the equivalent LCL-filter resonance frequency fr will no longer be fixed. It will deviate from the inherent resonance frequency fr , and the deviation direction of fr lies on the impedance characteristic of X eq . The following two cases will happen. 1) When fr < fs /3, X eq behaves as a virtual inductor, thus fr > fr . With the increase of Hi1 , the virtual inductance of X eq decreases, and fr keeps on deviating to the right side of fr . However, in this case, even if Hi1 increases to be infinite, fr cannot exceed fs /3. 2) When f s /3 < fr < f s /2, X eq behaves as a virtual capacitor, leading to fr < fr . With the increase of Hi1 , the virtual capacitance of X eq increases, and fr keeps on deviating to the left side of fr . Likewise, even if Hi1 is infinite, fr cannot exceed f s /3. When fr locates in different regions, the characteristic of Req at fr is different, which results in different damping

performance. Accordingly, the pole location of the loop gain is variable, and three cases may happen. 1) If fr < f s /6 and 0 < Hi1 < Hi1 c , then fr < f s /6. Here, Hi1 c = 2π fr L 1 [2cos(2π fr Ts ) − 1]/ [K PWM sin(2π fr Ts )] is the critical value of Hi1 as fr = f s /6 occurs [12]. As a result, Req at fr is positive, and the loop gain does not contain the RHP pole, i.e., P = 0. 2) If fr < f s /6 and Hi1 > Hi1 c , then fr > f s /6. As a result, Req at fr is negative, and the loop gain contains two RHP poles, i.e., P = 2. 3) If fr > f s /6 and Hi1 > 0, then fr > f s /6. As a result, Req at fr is negative, and the loop gain contains two RHP poles, i.e., P = 2. From the above analysis, it can be concluded that when fr > f s /6 happens, the loop gain must contain two RHP poles. Then, the stability constraints for the digitally controlled inverter will be far different from those for an analogcontrolled one. C. Stability Analysis According to the above analysis, the stability constraints can be classified to three cases, which are shown in Fig. 4. Case I: As observed from Fig. 4(a), the phase curve crosses over −180° only at fr . According to the Nyquist stability criterion [18], if the gain at fr is above 0 dB, it will be a negative crossing. Supposing N+ is the number of the positive crossing, N− is the number of the negative crossing, and P is the number of the open-loop RHP poles, it means N− = 1, N+ = 0. Since P = 0 is true for this case, the negative crossing must be disabled to ensure the system stable. In other words, the loop gain at fr needs to be adjusted to


TABLE I S TABILITY C ONSTRAINTS FOR THE T HREE D IFFERENT C ASES

be less than 0 dB so that the gain margin GM1 > 0 dB happens. As observed from Fig. 4(a), the phase curve does not cross over −180° at fr , the stability of the system is not affected even though the resonance peak at fr is not damped below 0 dB. Case II: As seen from Fig. 4(b), the phase curve crosses over −180° at both fr and f s /6. If the gains at both fr and f s /6 are above 0 dB, a negative crossing and a positive crossing happen, i.e., N− = N+ = 1. Since P = 2 is true for this case, the negative crossing must be disabled, and the positive crossing must be enabled to ensure the system stable. This means that the gain margin GM1 at fr must be larger than zero and the gain margin GM2 at f s /6 must be less than zero, i.e., GM1 > 0 dB and GM2 < 0 dB. Case III: As observed from Fig. 4(c), the phase curve also crosses over −180° at both fr and f s /6, and P = 2 is true for this case, so the stability constraints are similar to those of Case II. However, since the locations of fr and f s /6 are exchanged, the stability constraints about the gain margin should be adjusted to GM1 > 0 dB and GM2 < 0 dB. Besides the gain margins GM1 and GM2 , the phase margin PM of the three cases must be higher than 0 to ensure the system stable. Thus, the stability constraints are concluded in Table I.

As observed from Fig. 4(c), if fr = f s /6, the two gain margins will be equal, i.e., GM1 = G M2 . At this time, the requirement of GM1 > 0 and GM2 < 0 for Case II, or vice versa for Case III cannot be satisfied. Since the gain margins are usually recommended to be no less than 2 dB [18], a region can be obtained for the LCL-filter resonance frequency fr , where the selected fr should be kept away. Here, this region is defined as the forbidden region. According to Fig. 4, the gain margins GM1 and GM2 can be expressed as (4) (5)

To reduce the steady-state error, the widely used PR regulator [19]–[21] is employed here, which is expressed as G i (s) = k p +

s2

2kr (2π f i )s + 2(2π f i )s + (2π f o )2

where k p is the proportional coefficient, kr is the integral gain at the grid frequency f o , and f i is the lower breakpoint frequency of the dc gain [19]. To reduce the sensitivity of fo , −3 dB cutoff frequency is commonly reserved for f i . Since the grid frequency f o commonly fluctuates between 49.5 and 50.2 Hz in practice [22], f i is usually set to be 0.5 Hz. In general, for a properly designed system, the crossover frequency is set over a decade above the fundamental frequency f o . Therefore, when evaluating the system frequency response at and above f c , the PR regulator can be approximated to a proportional gain k p [15]. In addition, considering the gain of G d (s) is 1, and substituting s = j 2π f r into (2)–(4) yields Hi1 (L 1 + L 2 ) GM1 = 20 lg . (7) Hi2 k p L 1 Likewise, substituting s = j 2π( f s /6) into (2), (3), and (5) yields GM2

⎡

⎤ (2π f s /6)L 1 L 2 C ⎢ Hi2 K PWM k p ⎥ ⎥. = 20 lg ⎢ ⎣ ⎦ /6)K H (2π f s PWM i1 · (2π fr )2 − (2π f s /6)2 + L1 (8) Considering G i ( j 2π f c ) ≈ k p [15], substituting s = j 2π f c into (3), and setting |T ( j 2π f c )| = 1 yields 2π fc (L 1 + L 2 ) kp = . (9) K PWM Hi2 Substituting (9) into (7) yields GM1 2π f c L 1 Hi1 = 10 20 · = Hi1_GM1 (10) K PWM where Hi _GM1 is the critical value of Hi1 constrained by GM1 . Substituting (9) and (10) into (8) yields ⎧

2 ⎡ 2 ⎤⎫ ⎨ GM1 ⎬ fs 6 fs 6 fs 6 ⎦ . GM2 = 20 lg 10 20 · + · ⎣1− ⎩ ⎭ fr fc fr (11)

III. F ORBIDDEN R EGION OF THE LCL-F ILTER R ESONANCE F REQUENCY

GM1 = −20 lg |T ( j 2π f r )| GM2 = −20 lg |T ( j 2π f s /6)|.

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(6)

As observed from Fig. 4(b) and (c), when the loop gain contains two RHP poles, the amplitude curve crosses 0 dB three times. Meanwhile, the lowest frequency at which the amplitude curve crosses 0 dB is defined as the crossover frequency [18]. To achieve a sufficient phase margin, the crossover frequency is commonly set to be 0.3 times of the LCL-filter resonance frequency [13], [23], i.e., f c = 0.3 f r . Defining fr λ= . (12) fs /6 Substituting (12) into (11) yields 10

GM2 20

· λ3 − 3.33λ2 − 10

GM1 20

· λ + 3.33 = 0.

(13)

As seen, (13) is a third-order equation, which can hardly be directly solved. Nevertheless, if the boundaries of gain margins GM1 and GM2 are given, the boundaries of λ can easily be obtained by means of the mathematics tools, such as MATLAB or Mathcad. Then, a forbidden region can be determined.

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IV. C ONSTRAINTS OF THE C ONTROLLER PARAMETERS AND THE D ESIGN P ROCEDURE According to (13), a satisfying LCL-filter resonance frequency can be selected. Furthermore, based on the steady-state error, phase margin, and gain margins, just like the proposed design procedure for the analog-controlled one in [7], the controller parameters of the digitally controlled LCL-filtered inverter can be determined. However, differing from the analog-controlled one, the digitally controlled one may contain the open-loop RHP poles, which means that the resonance peak cannot be damped below 0 dB. Then, another gain margin is required for Fig. 4(b) and (c). Considering these differences, this section will give the design method for the digitally controlled LCL-filtered inverter. A. Constraint of the Controller Parameters 1) Steady-State Error: As observed from Fig. 4, the slope of the amplitude curve of the loop gain is −20 dB/decade within fc , which means that the filter capacitor can be ignored when calculating the steady-state error. Therefore, (3) can be simplified to [7] G i (s) G d (s) K PWM Hi2 . (14) s (L 1 + L 2 ) Furthermore, while calculating the steady-state error, i L2 can be expressed as T (s) ≈

1 T 1 1 i ∗ (s)− · vg (s) . (15) Hi2 1 + T L2 1 + T s (L 1 + L 2 ) As known, the steady-state error of the grid-connected inverter includes the amplitude error δ and the phase error θ . Since the PR regulator can provide a sufficient gain at f o , the phase error θ is easily attenuated. In other words, the design procedure is the same no matter what PF is. For simplicity, here, PF is set to 1. Based on (14) and (15), and considering |T ( j 2π f o )| 1 and |G d (2π f o )| ≈ 1, δ can be simplified into Hi2 |I L2 ( j 2π f o )|− I ∗ Vg 1 L2 · ≈ δ= ∗ I G ( j 2π f ) K I∗ i L2 (s) =

L2

i

o

PWM L2

As seen in (9), when an expected crossover frequency f c is selected, the proportional coefficient k p can be determined. If the required maximum steady-state error is set, the minimum integral gain of the grid-current regulator can be obtained from (17). 2) Gain Margin: Besides (10), another critical value of Hi1 constrained by gain margin can be obtained from (5), which is expressed as GM2 2π L 1 fr 2 ( fs /6)2 − fr2 Hi1_GM2 = 10 20 fc + . K PWM f s /6 f s /6 (18) As mentioned, if the system contains no open-loop RHP pole, as shown in Fig. 4(a), (18) is not required. 3) Phase Margin: Since f c is higher than both f o and f i , G i ( j 2π f c ) ≈ k p + 2kr f i / f c is reasonable to calculate the phase margin. Substituting s = j 2π f c into (3), and considering G i ( j 2π f c ) ≈ k p + 2kr f i / f c , yields PM = π/2 − 3π f c Ts − atan(2kr f i /( f c k p )) f c K PWM Hi1 cos(3π f c Ts ) . −atan 2π( f r2 − f c2 )L 1 + f c K PWM Hi1 sin(3π f c Ts ) (19) Then, substituting (9) and (17) into (19), the boundaries of Hi1 constrained by PM can be derived as (20), as shown at the bottom of the page. If GM1 , GM2 , PM, and δ are specified, a satisfactory region constrained by Hi1 and f c can be obtained from (10), (18), and (20). Compared with other controller design method, this method can intuitively provide all the proper controller parameters. Moreover, a good dynamic response can be ensured when a large f c is selected from the satisfactory region. After fc is selected, a proper Hi1 can be selected, and another boundary of kr constrained by the phase margin can be deduced as (21), as shown at the bottom of the page. According to (17) and (21), a satisfying kr can be selected.

(16) ∗ , i L2 , I L2

where and Vg are the root mean square (rms) values. Substituting s = j 2π f o into (6) yields G i ( j 2π f o ) = k p + kr . Then, substituting G i ( j 2π f o ) = k p + kr into (16) yields Vg kr_δ = (17) ∗ − kp K PWM δ I L2 where kr_δ is the critical value of kr constrained by δ.

Hi1_P M

kr_ P M

B. Design Procedure From the above analysis, a design procedure can be concluded, as shown in Fig. 5. Based on the satisfactory region constrained by (10), (18), and (20), the crossover frequency f c and the capacitor current feedback coefficient Hi1 can be selected. Then, the proportional coefficient k p can be calculated from (9). According to (17) and (21), the lower and upper boundaries of the integral gain kr can be obtained, respectively,

2π fr2 − f c2 L 1 1 = Hi2 Vg f i 2 fi f c K PWM cos (3π f c Ts ) tan P M + 3π f c Ts + atan −1 − ∗ 2 fc π f c (L 1 +L 2 )δ I L2 2π fr2 − f c2 L 1 + sin (3π f c Ts ) − tan (3π f c Ts + P M ) cos (3π f c Ts ) 2 π f c (L 1 + L 2 ) fc K PWM Hi1 = 2π ( fr2 − f c2 ) L 1 K PWM Hi2 f i tan (3π f c Ts + P M) + cos (3π f c Ts ) + sin f T (3π ) c s f c K PWM Hi1

(20)

(21)


Fig. 5.

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Flow chart of the design procedure.

TABLE II PARAMETERS OF THE P ROTOTYPE

Fig. 6. Satisfactory region of f c and Hi1 constrained by gain margin, phase margin, and steady-state error. (a) Filter I. (b) Filter II. (c) Filter III.

GM1 , GM2 , PM, and δ are too restrictive, the satisfactory region may not exist. At this time, some specification such as PM or δ must be adjusted, and the design procedure should be reiterated. C. Design Example from which a satisfying kr can be selected. To check whether the selected controller parameters are proper or not, the gain margins GM1 , GM2 , the phase margin PM, and the steadystate error δ should be verified. Note that if the specified

To verify the proposed forbidden region and the design method, an example is given. The prototype parameters are shown in Table II. Three different capacitances of the filter capacitor are used to achieve different fr . Here, C = 30 μF,

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C = 20 μF, and C = 10 μF are adopted. The corresponding resonance frequencies are 2.7, 3.2, and 4.6 kHz, respectively. For simplicity, Filters I–III are defined in accordance. Since GM is recommended to be no less than 2 dB [18], the target value GM1 is set to 3 dB and GM2 is to −3 dB for Figs. 4(a) and (b), and GM1 is −3 dB and GM2 is 3 dB for Fig. 4(c). Note that the lower boundary of λ is determined by GM1 = 3 dB and GM2 = −3 dB, and the upper boundary of λ is determined by GM1 = 3 dB and GM2 = −3 dB. Substituting GM1 = 3 dB and GM2 = −3 dB into (13), three values of λ can be produced by means of Mathcad, where λ1 = −1.08, λ2 = 0.88, and λ3 = 4.9. Likewise, substituting GM1 = −3 dB and GM2 = 3 dB into (13), another three values of λ can be produced, where λ4 = −0.92, λ5 = 1.25, and λ6 = 2.04. Obviously, the two negative values are invalid. Considering the forbidden region of λ is around 1, the valid forbidden region of λ is [0.88, 1.25]. As observed in Table II, the sampling frequency is set to be 20 kHz, so the forbidden region of the resonance frequency is [2.94, 4.23] kHz. It means that Filter II falls in the forbidden region, and Filters I and III are out of the forbidden region. To achieve a good dynamics response, Filters I and III should be selected. Besides the gain margins GM1 and GM2 , the PMs are expected between 30° and 60° [18]. Here, the initial target value of PM is set to be 45°. In addition, the magnitude error δ is expected to be less than 1% at the rated power. Based on these target values and the parameters in Table II, the satisfactory regions for Filters I and III can be obtained, as shown in Fig. 6(a) and (c). As shown in Fig. 6(a), the initially specified PM is so strict that the satisfactory region does not exist. Then, PM is adjusted to 36°, and a satisfactory region is found. As shown in Fig. 6(c), the satisfactory region with PM = 45° exists for Filter III. Based on the design method, all the controller parameters that meet the system specifications are obtained. To confirm Filter II can hardly achieve a good dynamics response, its satisfactory region is also given in Fig. 6(b), where PM is set to 45°, and GM1 and GM2 are set to zero. As seen, the satisfactory region is very small. According to Fig. 6(a), f c = 1.1 kHz and Hi1 = 0.05, which correspond to point A, are selected. With the parameters in Table II, the critical value of Hi1 for Filter I can be calculated, which is Hi1 c = 0.04. It is clear that the compensated system contains two open-loop RHP poles. Based on (9), (17), and (21), k p = 0.293, kr_δ = 56.7, and kr_PM = 66.6 are obtained. Then, k p = 0.29 and kr = 63 are selected. Substituting the selected Hi1 , k p , and kr into (7), (8), (16), and (19), GM1 = 3.1 dB, GM2 = −6.1 dB, δ = 0.7%, and PM = 36.5° are obtained. Likewise, from Fig. 6(b), f c = 1 kHz and Hi1 = 0.034, which correspond to point A, are selected. Based on (9), (17), and (21), k p = 0.266, kr_δ = 56.6, and kr_PM = 59.6 are obtained. Then, k p = 0.27 and kr = 58 are selected. Substituting the selected Hi1 , k p , and kr into (7), (8), (16), and (19), GM1 = 0.55 dB, GM2 = −0.62 dB, δ = 0.8%, and PM = 45°. From Fig. 6(c), f c = 1.3 kHz and Hi1 = 0.02, which correspond to point A, are selected. Based on (9), (17), and (21), k p = 0.346,

Fig. 7.

Bode diagrams of the compensated T (s). (a) Filter I. (b) Filter III.

kr_δ = 56.6, and kr_PM = 63.1 are obtained. Then, k p = 0.35 and kr = 63 are selected. Substituting the selected Hi1 , k p , and kr into (7), (8), (16), and (19), GM1 = −6.4 dB, GM2 = 3.2 dB, δ = 0.7%, and PM = 45° are obtained. Here, only the Bode diagrams of the well compensated loop gain for Filters I and III are shown in Fig. 7(a) and (b). As seen, the compensated results satisfy with the design expectation. To prove the accuracy of the satisfactory region, the parameters at point B in Fig. 6(a) and (c) will also be tested in the following. The controller parameters at point B in Fig. 6(a) are k p = 0.29, kr = 63, and Hi1 = 0.062, which results GM2 is about 0 dB, and the controller parameters at point B in Fig. 6(a) are k p = 0.35, kr = 63, and Hi1 = 0.042, which results GM1 is about 0 dB. V. S IMULATION AND E XPERIMENTAL R ESULTS A. Simulation Results A detailed time-domain model of the studied system in Fig. 1 is implemented under the Saber environment to verify


Fig. 8.

∗ . Simulation results for Filter I. (a) Steady-state waveform at rated power. (b) Transient response waveform under step change in i L2

Fig. 9.

∗ . Simulation results for Filter II. (a) Steady-state waveform at rated power. (b) Transient response waveform under step change in i L2

Fig. 10.

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∗ . Simulation results for Filter III. (a) Steady-state waveform at rated power. (b) Transient response waveform under step change in i L2

the theoretical analysis. The parameters of the three prototypes are given in Table I, and the selected controller parameters k p , kr , and Hi1 in Section IV-C will be examined. Figs. 8(a), 9(a), and 10(a) show the steady-state simulation results for Filters I–III at the rated power, respectively. As seen, all the three compensated system are stable. Because of the sufficiently high gain at the fundamental frequency of

the PR regulator, the measured PFs are over 0.997, and the amplitude errors δ are less than 1%. Figs. 8(b), 9(b), and 10(b) ∗ is show the transient response for Filters I–III. Here, i L2 stepped down at its peak from the rated power to the half rated power. As seen, i L2 is well in phase with vg , and the overshoots of the three cases are all about 80%. Oscillation occurs after ∗ is stepped. However, it decays fast for Filters I and III i L2

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Fig. 11.

Fig. 12.


Simulation results with the controller parameters at point B. (a) Filter I. (b) Filter III.

Photograph of the single-phase grid-connected inverterprototype.

and very slow for Filter II, which means that the dynamics responses of Filters I and III are good, and it is bad for Filter II. Fig. 11(a) and (b) shows the simulation results with the controller parameters at point B of Fig. 6(a) and (c), respectively. As seen, the oscillation happens, and the oscillation amplitude increases as time goes on. Through the spectrum of the grid current i L2 , it is found that the oscillation frequencies are around 3.1 and 4.4 kHz for Filters I and III, respectively. It is clear that the controller parameters at point B cannot ensure the compensated system stable. B. Experimental Results The single-phase LCL-filtered inverter was implemented with two Mitsubishi IGBT modules (CM100DY-24NF). The control algorithm was implemented in a high-speed DSP (TMS320F2812), and an extended 14-bit A/D converter (MAXIM-1324ECM) was used. Fig. 12 shows the prototype construction. Note that the LCL-filtered inverter is connected to the real grid through a local isolated transformer, where the leakage inductor of the transformer is used to work

as L 2 . The corresponding prototype parameters are given in Table II. Figs. 13(a), 14(a), and 15(a) show the steady-state experimental waveforms for Filters I–III at the rated power, respectively. The measured PFs are 0.997, 0.998, and 0.998; THDs are 4.4%, 3.7%, and 3.8%; the rms values of i L2 are 27.07, 27.18, and 27.09 A; and the amplitude errors are 0.7%, 0.4%, and 0.5%, respectively. As seen, these measured steady-state experimental results satisfy the simulation results. Figs. 13(b), 14(b), and 15(b) show the transient response ∗ is stepped down at its peak for Filters I–III. Likewise, i L2 from the rated power to the half rated power. As seen, i L2 is well in phase with vg , but the overshoots are only 37%, 78%, and 44%, respectively. The oscillation is far smaller than that of the simulation results. The reason is that the parasitic resistors exist in the real LCL filter, and the local loads that are connected to the real grid can also contribute to reduce the overshoot and attenuate the oscillation. Nevertheless, the experimental results still illustrate that the dynamics responses of Filters I and III are good, whereas it is bad for Filter II. Fig. 16(a) and (b) shows the experimental results with the controller parameters at point B in Fig. 6(a) and (b), respectively. As seen, the oscillation happens. Through the spectrum of the grid current i L2 , it is found that the oscillation frequencies are truly around 3.1 and 4.4 kHz for Filters I and III, respectively. Note that due to the LCL-filter parasitic resistors and the local loads, the oscillation does not become divergent. Here, to identify the oscillation frequencies, the waveforms are obtained with a programmable ac source (Chroma 6590) for emulating a pure sinusoid grid voltage. From the above simulation and experimental results, it can be concluded that when the resonance frequency of the selected LCL filter falls in the forbidden region, the system can be hardly compensated to achieve a good dynamics response, which means that the proposed forbidden region can guide the design of the LCL filter. As well, the proposed controller design method is very convenient, because the satisfactory region can provide all the proper controller parameters meeting the system specifications and guide the selection of the proper controller parameters.


Fig. 13.

∗ . Experimental waveforms for Filter I. (a) Steady-state waveform at rated power. (b) Transient response waveform under step change in i L2

Fig. 14.

∗ . Experimental waveforms for Filter II. (a) Steady-state waveform at rated power. (b) Transient response waveform under step change in i L2

Fig. 15.

∗ . Experimental waveforms for Filter III. (a) Steady-state waveform at rated power. (b) Transient response waveform under step change in i L2

VI. C ONCLUSION Due to the delay effect, the proportional feedback of the capacitor current is equivalent to a frequency-dependent virtual impedance in parallel with the filter capacitor, and the digitally controlled LCL-filtered inverter tends to be unstable as the LCL-filter resonance frequency approaching one-sixth of the sampling frequency.

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A forbidden region of the LCL-filter resonance frequency is proposed to guide the design of the LCL filter. After the LCL filter is determined, a design method is proposed. A satisfactory region of the controller parameters for the system specifications is obtained, from which the proper controller parameters can easily be determined. In addition, based on the satisfactory region, it is convenient to optimize the system performance. The proposed forbidden region and

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Fig. 16.

Experimental waveforms with the controller parameters at point B. (a) Filter I. (b) Filter III.

Fig. 17.

Equivalent transformations of block diagram of Fig. 3.

the design method in this paper can be extended to the digitally controlled LCL-filtered inverters with different active damping solution.

A PPENDIX To get the expression of the loop gain T (s), from Fig. 3, a series of equivalent transformations of the system in terms


of block diagrams is shown in Fig. 17, where the dashed lines represent the original status and the bold solid lines represent the destination status. First, simplifying the transfer functions from G i (s) to G d (s), and simplifying the loop from the forward path 1/(sC) to the feedback path 1/Z eq (s), an equivalent block diagram is obtained, as shown in Fig. 17(a). Second, moving the feedback node of vc (s) from the input of 1/(sL1 ) to its output, and adjusting its feedback function, results in the equivalent block diagram shown in Fig. 17(b). Third, simplifying the loop from the forward path 1/[sC + 1/Z eq (s)] to the feedback path 1/(sL1 ), an equivalent block diagram is obtained, as shown in Fig. 17(c). Fourth, relocating the feedback node of i L2 (s) from the input of sL1 /[s 2 L 1 C + sL1 /Z eq (s) + 1] to its output, and adjusting its feedback function, an equivalent block diagram is obtained, as shown in Fig. 17(d). Finally, simplifying the loop from the forward path 1/(sL2 ) to the feedback path sL1 /[s 2 L 1 C + sL1 /Z eq (s) + 1] results in the equivalent block diagram shown in Fig. 17(d), from which the expression of the loop gain can easily be obtained. R EFERENCES [1] J. M. Carrasco et al., “Power-electronic systems for the grid integration of renewable energy sources: A survey,” IEEE Trans. Ind. Electron., vol. 53, no. 4, pp. 1002–1016, Jun. 2006. [2] A. A. Rockhill, M. Liserre, R. Teodorescu, and P. Rodriguez, “Grid-filter design for a multimegawatt medium-voltage voltage-source inverter,” IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1205–1217, Apr. 2011. [3] T. C. Y. Wang, Z. Ye, G. Sinha, and X. Yuan, “Output filter design for a grid-interconnected three-phase inverter,” in Proc. IEEE 34th Annu. PESC, Jun. 2003, pp. 779–784. [4] R. Peña-Alzola, M. Liserre, F. Blaabjerg, R. Sebastián, J. Dannehl, and F. W. Fuchs, “Analysis of the passive damping losses in LCL-filterbased grid converters,” IEEE Trans. Power Electron., vol. 28, no. 6, pp. 2642–2646, Jun. 2013. [5] C. Wessels, J. Dannehl, and F. W. Fuchs, “Active damping of LCL-filter resonance based on virtual resistor for PWM rectifiers—Stability analysis with different filter parameters,” in Proc. IEEE PESC, Jun. 2008, pp. 3532–3538. [6] Y. Jia, J. Zhao, and X. Fu, “Direct grid current control of LCL-filtered grid-connected inverter mitigating grid voltage disturbance,” IEEE Trans. Power Electron., vol. 29, no. 3, pp. 1532–1541, Mar. 2014. [7] C. Bao, X. Ruan, X. Wang, W. Li, D. Pan, and K. Weng, “Stepby-step controller design for LCL-type grid-connected inverter with capacitor–current-feedback active-damping,” IEEE Trans. Power Electron., vol. 29, no. 3, pp. 1239–1253, Mar. 2014. [8] E. Wu and P. W. Lehn, “Digital current control of a voltage source converter with active damping of LCL resonance,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1364–1373, Sep. 2006. [9] D. G. Holmes, T. A. Lipo, B. P. McGrath, and W. Y. Kong, “Optimized design of stationary frame three phase AC current regulators,” IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2417–2426, Nov. 2009. [10] J. Dannehl, F. W. Fuchs, and P. B. Thøgersen, “PI state space current control of grid-connected PWM converters with LCL filters,” IEEE Trans. Power Electron., vol. 25, no. 9, pp. 2320–2330, Sep. 2010. [11] X. Zhang, J. W. Spencer, and J. M. Guerrero, “Small-signal modeling of digitally controlled grid-connected inverters with LCL filters,” IEEE Trans. Ind. Electron., vol. 60, no. 9, pp. 3752–3765, Sep. 2013. [12] D. Pan, X. Ruan, C. Bao, W. Li, and X. Wang, “Capacitor-currentfeedback active damping with reduced computation delay for improving robustness of LCL-type grid-connected inverter,” IEEE Trans. Power Electron., vol. 29, no. 7, pp. 3414–3427, Jul. 2014. [13] S. G. Parker, B. P. McGrath, and D. G. Holmes, “Regions of active damping control for LCL filters,” IEEE Trans. Ind. Appl., vol. 50, no. 1, pp. 424–432, Jan./Feb. 2014. [14] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, “Overview of control and grid synchronization for distributed power generation systems,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1398–1409, Oct. 2006.

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[15] E. Figueres, G. Garcera, J. Sandia, F. Gonzalez-Espin, and J. C. Rubio, “Sensitivity study of the dynamics of three-phase photovoltaic inverters with an LCL grid filter,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 706–717, Mar. 2009. [16] D. G. Holmes, T. A. Lipo, B. P. McGrath, and W. Y. Kong, “Optimized design of stationary frame three phase AC current regulators,” IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2417–2426, Nov. 2009. [17] J. L. Agorreta, M. Borrega, J. Lápez, and L. Marroyo, “Modeling and control of N -paralleled grid-connected inverters with LCL filter coupled due to grid impedance in PV plants,” IEEE Trans. Power Electron., vol. 26, no. 3, pp. 770–785, Mar. 2011. [18] M. Driels, Linear Control Systems Engineering. New York, NY, USA: McGraw-Hill, 1996. [19] S. Fukuda and T. Yoda, “A novel current-tracking method for active filters based on a sinusoidal internal model [for PWM invertors],” IEEE Trans. Ind. Appl., vol. 37, no. 3, pp. 888–895, May/Jun. 2001. [20] X. Yuan, W. Merk, H. Stemmler, and J. Allmeling, “Stationary-frame generalized integrators for current control of active power filters with zero steady-state error for current harmonics of concern under unbalanced and distorted operating conditions,” IEEE Trans. Ind. Appl., vol. 38, no. 2, pp. 523–532, Mar./Apr. 2002. [21] D. N. Zmood and D. G. Holmes, “Stationary frame current regulation of PWM inverters with zero steady-state error,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 814–822, May 2003. [22] Technical Rule for Photovoltaic Power Station Connected to Power Grid, Chinese Standard Q/GDW 617-2011, May 2011. [23] Y. Tang, P. C. Loh, P. Wang, F. H. Choo, F. Gao, and F. Blaabjerg, “Generalized design of high performance shunt active power filter with output LCL filter,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1443–1452, Mar. 2012.

Xuehua Wang (M’12) was born in Hubei, China, in 1978. He received the B.S. degree in electrical engineering from the Nanjing University of Technology, Nanjing, China, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the Nanjing University of Aeronautics and Astronautics, Nanjing, in 2004 and 2008, respectively. He is currently a Lecturer with the School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, China. His current research interests include multilevel inverter and renewable energy generation system.

Chenlei Bao was born in Zhejiang, China, in 1987. He received the B.S. degree from the School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin, China, in 2010, and the M.S. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2013. His current research interests include digital control technique and renewable energy generation system.

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Xinbo Ruan (M’97–SM’02) was born in Hubei, China, in 1970. He received the B.S. and Ph.D. degrees in electrical engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 1991 and 1996, respectively. He joined the Faculty of the Electrical Engineering and the Teaching and Research Division at NUAA, in 1996, where he became a Professor with the College of Automation Engineering in 2002. In 2007, he was a Research Fellow with the Department of Electronic and Information Engineering, Hong Kong Polytechnic University, Hong Kong, where he has been involved in teaching and research of power electronics. Since 2008, he has been with the School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan, China. He is currently a Guest Professor with Beijing Jiaotong University, Beijing, China, the Hefei University of Technology, Hefei, China, and Wuhan University, Wuhan. He has authored or co-authored four books, and over 100 technical papers published in journals and conferences. His current research interests include soft-switching dc–dc converters, soft-switching inverters, power factor correction converters, modeling the converters, power electronics system integration, and renewable energy generation system. Dr. Ruan is a Senior Member of the IEEE Power Electronics Society and the IEEE Industrial Electronics Society. Since 2005, he has served as the Vice President of the China Power Supply Society, and a Technical Committee Member of Renewable Energy Systems with the IEEE Industrial Electronics Society since 2008. He has been an Associate Editor of the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS and the IEEE J OURNAL OF E MERGING AND S ELECTED T OPICS ON P OWER E LECTRONICS since 2011 and 2013, respectively. He was a recipient of the Delta Scholarship by the Delta Environment and Education Fund, in 2003, and the Special Appointed Professor of the Chang Jiang Scholars Program by the Ministry of Education, China, in 2007.

Weiwei Li (S’12) was born in Henan, China, in 1987. He received the B.S. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2009, where he is currently pursuing the Ph.D. degree. His current research interests include digital control technique and renewable energy generation system.

Donghua Pan (S’12) was born in Hubei, China, in 1987. He received the B.S. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2010, where he is currently pursuing the Ph.D. degree. His current research interests include magnetic integration technique and renewable energy generation system.