Design, Fabrication, and Calibration of a

IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 32, NO. 2, JUNE 2009

513

Design, Fabrication, and Calibration of a Piezoresistive Stress Sensor on SOI Wafers for Electronic Packaging Applications Kuo Tian, Zheyao Wang, Member, IEEE, Min Zhang, and Litian Liu

Abstract—This paper presents the development of a piezoresistive stress sensor fabricated on silicon-on-insulator (SOI) wafers for measurement of electronic packaging stress at high temperature. The sensor consists of a series of sensor elements and calibration elements. The sensor elements comprise a 0 –90 p-type piezoresistor pair and a 45 n-type piezoresistor pair for stress measurement, and the calibration elements comprise two polar three-piezoresistor rosettes with specific angels to calibrate the piezoresistive coefficients. The sensor and the calibration piezoresistors are etched from the SOI layer as separate “silicon islands” on the dielectric buried oxide (BOX) layer. This configuration exploits the excellent electrical insulation of the BOX layer, and enables high-temperature operation of the stress sensor by eliminating the leakage current. Design, fabrication, and the calibration of the piezoresistors at high temperatures show the feasibility of the SOI high-temperature stress sensor. The piezoresistive coefficients are calibrated versus stress and temperature, and the nonlinearity of the resistance versus temperature and the calibration errors are discussed in detail. Index Terms—High temperature, piezoresistors, silicon-on-insulator (SOI), stress sensors.

I. INTRODUCTION

T

HE application of excess mechanical or thermal loadings to a die during packaging can produce die failure due to the stress-induced cracks or breakage. The excess stresses are most likely to occur during die attachment or encapsulation in epoxy resin and molding of plastic-packaged ICs [1]. This problem is even more serious for state-of-the-art multiplayer-stacked packaging and 3-D integration. To measure the die stress, test chips incorporated in chip packages to replace the die of interest have gone a long way since their appearance in the early stage of 1980s [2]. Most test chips use IC-compatible silicon piezoresistors as stress sensors to measure the stress on the chip surface [3]–[14]. The silicon piezoresistors are fabricated on silicon

Manuscript received July 01, 2008. First published December 09, 2008; current version published July 22, 2009. This work was supported in part by the Major State Basic Research Program (973) under Grant 2006CB302703 and 863 Program under Contract 2007AA03Z304. This work was recommended for publication by Associate Editor K. Jonnalagadda upon evaluation of the reviewers comments. The authors are with the Institute of Microelectronics, Tsinghua University, Beijing 100084, China (e-mail: [email protected]; [email protected]; [email protected]; litianliu@ tsinghua.edu.cn). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAPT.2008.2006854

wafers by doping specific patterns with given concentration to obtain desired resistivity and piezoresistive coefficients, and the measured resistance changes induced by stress can be used to solve the stresses. The piezoresistors are isolated from one another and the substrate by reverse bias p-n junctions. Besides piezoresistors, MOSFETs [15]–[17] and piezo-bridge structures [18] also attract research interests as alternative stress sensors. The advantage of these devices is the superior spatial resolution compared with the piezoresistors. For real-time stress monitoring during packaging, the stress sensors should be operated at high-temperature processes, such as die attachment or molding, in which the operation temperature can be as high as 150 C–200 C. The devices on bulk silicon wafers do not fulfill this requirement, because the significant leakage current of the reverse bias p-n junctions at high-temperature environments makes the devices invalid. For high-temperature applications, silicon-on-insulator (SOI) wafers offer some advantages over conventional bulk silicon wafers. By etching the SOI layer except for the piezoresistors completely away, the piezoresistors are formed as separate “silicon islands” on the buried silicon dioxide (BOX) layer. Hence, they can be insulated from one another and the substrate by the dielectric BOX layer. This avoids the use of reverse bias p-n junctions and thus eliminates the substrate contact and the leakage current. Thanks to the excellent insulation capability of the BOX layer, SOI wafers have been widely used to develop high-temperature pressure sensors and accelerometers [19]–[23]. This paper proposes a piezoresistive stress sensor fabricated on (100) SOI wafers for high-temperature applications. The piezoresistors are etched from the SOI layer, and other regions of the SOI layer rather than the piezoresistors are completely etched away. The BOX layer insulates the separate piezoresistors from the silicon substrate, and also acts as a barrier layer for dopants diffusion during thermal annealing, making the doping concentration uniform through the thickness of the piezoresistors. Design, fabrication, and calibration of the stress sensor are given in detail. Piezoresistive coefficients and temperature coefficients are measured and are compared with bulk silicon wafers. II. SENSOR AND CALIBRATION ELEMENTS The test chip consists of a series of piezoresistor measurement rosettes for stress measurement (T1 to T11) and calibration rosettes for piezoresistive coefficient calibration (Cn12 to Cp15), as shown in Fig. 1(a). For a piezoresistor fabricated on

1521-3331/$25.00 © 2008 IEEE Authorized licensed use limited to: Tsinghua University Library. Downloaded on August 12, 2009 at 19:01 from IEEE Xplore. Restrictions apply.

514


Fig. 1. (a) Configuration of the test chip. (b) Piezoresistor rosettes for the measurement element and the calibration element.

(100) wafers and oriented at an angle of with respect to the [110] wafer axis, when subjected to an arbitrary state of stress, the fractional changes in the resistance is a function of stress [3], [4]

normal stress difference and the shear stress [24]. Application of the orientations of the four piezoresistors to (1) gives the following relations between the resistance changes and the stresses at the rosette site

(2) (1) is its changes, and where is the initial resistance and are the normal stresses along the [110] and the direcis the shear stress in the main plane. , tions, respectively, , and are the three unique piezoresistive coefficients. and are, respectively, the first- and second-order temperature coefficients, and is the temperature changes relative to reference. The out-of-plane stresses are neglected due to the thin plate characteristics of the chips. A. Sensor Rosettes A typical stress sensor on (100) wafers employs a four-element dual-polarity sensor rosette [4], as shown in Fig. 1(b). The rosette consists of a 0 –90 p-type piezoresistor pair and a n-type pair. The p-type piezoresistors have the same doping concentration but different angles with respect to the axis, and so does the n-type pair. Such a configuration minimizes the errors due to the misalignment of the resistors to the crystallographic axes, and permits temperature compensated measurement of the

where and . The superscripts n and p denote the n-type and the p-type piezoresistors, respectively. Using (2), the stresses can be obtained by measuring the resistance changes. B. Calibration Rosettes Calibration is necessary to extract the piezoresistive coefficients due to their dependency on fabrication. A calibration method using a three-element n-type rosette and a p-type rosette on a silicon strip has been developed [3]. The three calibration have angles of 0 , 45 , and 90 piezoresistors , , and with respect to the -axis, respectively. The silicon strip is cut from the wafer at an angle of 22.5 and uniaxial stress is created along the strip using a four-point-bending fixture. Individual , , and of both the p-type and the n-type piezoresistors can be determined through the uniaxial stress-induced resistance changes. Based on this method, a set of functions is developed to extract the piezoresistive coefficients from a strip aligned to the axis with an arbitrary angle instead of exact 22.5 .

Authorized licensed use limited to: Tsinghua University Library. Downloaded on August 12, 2009 at 19:01 from IEEE Xplore. Restrictions apply.

TIAN et al.: DESIGN, FABRICATION, AND CALIBRATION OF A PIEZORESISTIVE STRESS SENSOR

515

Fig. 2. Fabrication process. (a) Piezoresistor etching. (b) p-type piezoresistor implantation. (c) n-type piezoresistor implantation. (d) p-type contact implantation. (e) n-type contact implantation. (f) Metallization and passivation.

The changes in the three calibration piezoresistors can be obtained from (1) as follows:

(3) where the temperature associated terms are neglected. , Using tensor transformation, the stress components and in the system can be expressed by the components , and in the system. By applying a uniaxial stress along the -direction, (3) is simplified to

(4) -axis and the where is the rotation angle between the -axis. equals to , and can be obtained easily through four-point bending. Equation (4) can be transformed into

III. FABRICATION AND CALIBRATION The test chips were fabricated on SOI wafers using 1- m manufacturing technology and design rules. Serpentine configuration, which consists of six piezoresistor segments connected with aluminum interconnects, is used for the piezoresistors, such that small occupied area and high spatial resolution can be achieved. The length, width, and thickness of each segment are 12 m, 2 m, and 200 nm, respectively. The fabrication process is rather simple. As shown in Fig. 2, the fabrication started with a p-type (100) SOI wafer with the thickness of the BOX layer 200 nm. After patterning and etching the piezoresistor rosettes, p-type and n-type piezoresistors were implanted with boron and phosphorus, respectively, by alternatively protecting the piezoresistors of opposite polarity. Then the contacts were implanted, followed by deposition of 0.8- m aluminum metallization and 0.6 m silicon dioxide passivation. As the piezoresistors are narrow in width to achieve small size, they should be carefully controlled to avoid over-etch induced width deviation. It should be noted that SOI wafers fabricated using separation by implanted oxygen (SIMOX) is preferred to those fabricated using bonding technology, because the inevitable alignment error between the SOI layer and the substrate silicon of bonded SOI wafers results in the stress difference between the SOI layer and the substrate silicon. Calibration setups are conventional four-point-bending (4PB) apparatus [4], [14]. Fig. 3 shows the photos of the 4PB with a silicon strip installed and the whole calibration system. In a 4PB fixture, a long and thin silicon strip with the calibration rosettes on the center is supported by two parallel blades, and uniaxial stress along the silicon strip is induced by applying external forces to the strip symmetrically to the supporting blades. The uniaxial stress on the top surface of the strip is [14] (6)

(5) 0, 45 , 90 , one can obIt can be seen that in case of tain the piezoresistive coefficients from the given angles and the measured resistance changes. For convenience in cutting the calis chosen for the strip with respect to the ibration strip, -axis.

where is the external force. is the space between the force applying points, is the interval of the two parallel supporting blades, and and are, respectively, the thickness and the width of the silicon strip. This equation is valid on condition that is far smaller than , , and . This requirement is easily are satisfied, as is about 500 m, whereas , , and more than 10 mm. Then the uniaxial stress is substituted into (5) to calculate the piezoresistive coefficients.


516


Fig. 3. Optical photos of (a) 4PB with a silicon strip and (b) the calibration system.

Fig. 4. (a) Optical photo of the test chip. (b) SEM photo of the measurement rosette. (c) SEM photo of the calibration rosette.

Wire bonding instead of hard probes is used to connect the calibration piezoresistors with a PCB, such that the undesired stress caused by the hard probe is avoided. The piezoresistance changes are converted into voltage signal by a Wheatstone bridge and an amplifier, and recorded using a digital multimeter. All the temperature measurements are performed in a computer-controlled oven. Calibration is carried out over a wide range of stress and temperature. IV. EXPERIMENTAL RESULTS Fig. 4 shows the photos of the fabricated test chip, the measurement rosette, and the calibration rosette. The nominal resistance is 50 k , and the sheet resistance of the SOI layer with normal doping concentration, whereas those is 900 fabricated in bulk silicon are on the order of two or three hundreds [3]. Large resistance makes the size of the piezoresistor rosettes as small as 50 m by 50 m for the desired resistance value. Compared with bulk piezoresistor rosettes, e.g., 20 m by 50 m [14], 100 m by 100 m [13] or 400 m by 400 m [10], the piezoresistors fabricated on SOI wafers have a relatively small size and can achieve high spatial resolution for stress measurement. A. Piezoresistive Coefficients Fig. 5 shows the measured changes in the p-type and n-type piezoresistance versus the applied stresses at room temperature. The largest relative change in the piezoresistance for 100-MPa stress is about 3% for the p-type piezoresistors and 0.4% for the n-type piezoresistors. The fitted lines show a satisfactory linear

relationship, and the slopes of the lines represent the piezoresistive coefficients. Both the p-type and the n-type piezoresistors are calculated at all stresses applied, and the mean values are compared with several literature results, as listed in Table I. is the For n-type piezoresistors, the absolute value of largest, followed by and , and holds. The piezoresistive coefficients are two times the heavily doped silicon and half the lightly doped silicon. For p-type piezoreis much larger than and sistors, the absolute value of . is about half that of the lightly doped silicon, and about the same as heavily doped silicon. These relations between the unique piezoresistive coefficients agree well with previous literature [6], [7], [13]. B. Piezoresistive Coefficients Versus Stress and Temperature The piezoresistive coefficients versus stress at room temperature, as illustrated in Fig. 6(a), show that the piezoresistive coefficients remain almost constant with stress. Fig. 6(b) shows the n-type and the p-type piezoresistive coefficients versus temperature variation. Linear and second-order polynomial fittings show that the first- and the second-order temperature coefficients are and , respectively. As a temperature on the order of change of 100 C causes only about 5% relative variation in the piezoresistive coefficients, it is reasonable to neglect the small variation and regard the piezoresistive coefficients as constant with temperature. This agrees well with literature results [3], [14], [25]. The relative variations in large piezoresistive coeffiand for n-type and for p-type, are much cients, like small, whereas the variations are quite large for small piezoresistive coefficients. This is because small absolute piezoresistive coefficients make the measurement errors relatively enlarged.



517

Fig. 5. Relative changes in the piezoresistance versus stress. (a) n-type piezoresistors. (b) p-type piezoresistors.

Fig. 6. Piezoresistive coefficients versus (a) stress and (b) temperature.

TABLE I PIEZORESISTIVE COEFFICIENTS

V. DISCUSSIONS A. Nonlinearity of Resistance Versus Temperature

C. Specifications Several specifications were calculated from the measured piezoresistance changes to evaluate the sensor performance. The nonlinearity is around 4%, whereas hysteresis and repeatability are 0.2% and 0.15%, respectively. Therefore, the measurement errors are dominated by the nonlinearity, and the contributions of hysteresis and repeatability are rather small. This suggests that performance improvement needs significant reduction in the nonlinearity.

The changes in the resistance versus the temperature changes (reference to 20 C) without stress applied were measured, and the results as well as the second-order polynomial fitted curves are shown in Fig. 7. It is shown that the largest relative change in the resistance with temperature is 10%, about 3 times greater than that caused by 100 MPa stress. For p-type resistors, the first-order temperature coefficient is 300 ppm C, smaller than 1000–2000 ppm C of bulk silicon wafers [4]; the second-order temperature coefficient is about 3.3 ppm C . As the temperature changes are on the order of 100 C, the second-order temperature coefficient results in a relatively large nonlinearity. The low first-order temperature coefficient is the result of the relative high doping concentration, since the temperature coefficients decrease with the doping concentration, at a cost of low stress sensitivity. Reasons responsible for the second-order temperature coefficients are still under investigation, and could be attributed to the low thermal dissipation caused by the low thermal conductivity of the BOX layer.


518


Fig. 8. Schematic illustration of the 4PB with unsymmetry.

Fig. 7. Changes in the resistance versus temperature.

The first- and second-order temperature coefficients of n-type resistors are 430 ppm C and 4.6 ppm C , respectively. Although they are on the same order as the p-type resistors, the resistance exhibits non-monotonic characteristics with temperature. Specifically, the resistance decreases with the increase of temperature below 70 C, and increases with temperature higher than 70 C, as shown in Fig. 7. This unexpected behavior could be attributed to the counter implantation during fabrication, i.e., the p-type implantation over the whole wafer to form test p-n junctions counters the n-type dopant that forms the n-type piezoresistors. As the p-type dopant concentration cm is close to the n-type dopant concentration cm , the dominant carriers (n-type dopant) may not ionize completely at room temperature. The measured resistance of the n-type piezoresistors, which is 90 k and about two times the designed 50 k , proves this hypothesis. The resistivity is a function of the mobility and the concentration of the carriers (7) The mobility is determined by scattering mechanisms, which include lattice scattering and impurity scattering , through (8) Therefore, the mobility is dominated by the smaller one, i.e., the stronger scattering mechanisms. For low doping concentration, lattice scattering dominates the mobility. With the increase of temperature, lattice vibration and lattice scattering enhance, and thus the mobility decreases and the resistance increases. For high doping concentration, the impurity scattering dominates the mobility. As the impurity quantity is determined only by the doping concentration and independent of temperature, the mobility almost does not vary with temperature. Hence, high-doping semiconductors exhibit small temperature coefficients. In counter doping, the relation between the mobility and temperature is more complex. For the resistors with the same net doping concentration, the resistivity of counter-doped resistors is larger than the single-doped resistors, because impurity scattering becomes stronger for counter doping and thus the mobility decreases. In addition, the dominant impurity does not

ionize completely at room temperature, and the overall effect is the rather large resistivity of the counter-doped piezoresistors. With the increase of temperature, dominant impurity ionizes largely. This increases the concentration of the carrier and compensates for the decrease of mobility, resulting in lower resistivity. With the further increase of temperature, the dominant impurity completely ionizes, and the concentration of the dominant carrier approaches saturation. Meanwhile, the mobility decreases, and therefore the overall effects are that the resistivity of n-type resistors behaves non-monotonic characteristics. B. Influence of Temperature on Calibration Temperature measurement errors affect the stress measurement significantly. By neglecting the out-of-plane stress, from the first two equations in (2) and solving from the last two equations yields [4]

(9) It can be seen that the difference of the two normal stresses and the shear stress are both temperature compensated (independent of temperature), and thus accurate measurement of these two stresses does not require temperature information. The individual normal stresses and , however, are strongly temperature-dependent, so accurate measurement of these stresses needs temperature information and small temperature measurement errors. For p-type piezoresistors on bulk silicon and doped with low concentration, the typical is Pa and the first-order temperature coefficient is 2000 ppm C [4]. A temperature measurement error of 0.5 C corresponds to a stress measurement error of 20 MPa, on the order of 10% relative [24]. High doping concentration, though has the disadvantage of small piezoresistive coefficients, reduces the first-order temperature coefficient from 2000 ppm C to about 300 ppm C, which reduces the stress measurement error induced by a 0.5 C temperature error from 20 MPa to 3 MPa. For n-type is normally two piezoresistors, the piezoresistive coefficient orders of that of p-type piezoresistors, so the stress measurement errors induced by temperature measurement errors are relatively small. C. 4PB Calibration Errors Besides the literature reported calibration errors induced by the 4PB structure [24], the unsymmetry of the calibration rosette to the loading and the supporting blades may cause errors. Fig. 8 shows the illustration of the 4PB with the calibration rosette located at the center and off-center of the two



supporting blades. The equilibrium of force and moment gives the following relations:

519

The ratio of the shear stress to the normal stress is

(16)

(10) and then the supporting force can be solved

For normal 4PB structures, the numerator in (16) is about three orders smaller than the denominator. Therefore, the shear stress and the errors can be ignored. If the calibration rosette does not locate at the center of the two supporting blades, e.g., at position C, the stress difference between the center and position C is (17)

(11) If the two supporting blades and the two loading blades are symmetrical, i.e., , holds. It can be concluded that there is no shear stress on the strip surface, and the normal stress is constant distribution (independent of the location) and is given by (6). Otherwise, if the silicon strip is not symmetrical to the sup, it can be obtained from (11) that porting blades, and therefore shear stress appears in the silicon strip. At any position in between the two supporting blades, the vertical force does exist and equals to (12) is the vertical force in the cross section of the strip, where . The shear stress of the cross section of the and strip in between the two supporting blades is given by (13) where is the shear stress. The normal stress varies linearly instead of constant. The stresses at A and B can be easily obtained as

(14) ), i.e., The normal stress increases from B to A (if , but the stress of the center of the two supporting blades is still the same as (6). This implies that if the calibration rosette locates at the center of the two supporting blades, the unsymmetry of the blades and the calibration rosette does not induce calibration errors. If the calibration rosettes locate at the center of the two supporting blades, the normal stress is

(15)

where is the interval between the position C and the center, i.e., the offset. Then one has (18) If the offset to the center is 2 mm and unsymmetry is 3 mm, the relative error of the normal stress is about 1% for cm and cm, and is about 4% for cm and cm. As the error is on the same order as the temperature and stress induced errors, the unsymmetry must be avoided. VI. CONCLUSION Piezoresistive stress sensors on SOI wafers have been designed, fabricated, and calibrated for high-temperature stress measurement in electronic packaging applications. Etching the piezoresistors from the SOI layer as separate silicon islands on the BOX layer eliminates the leakage currents between the piezoresistors and the substrate, enabling the high-temperature operation of the sensors. The characteristics of SOI piezoresistors assemble those in bulk silicon wafers. The three-element calibration rosette with any angles to the crystallographic axes has been verified. The measurement results demonstrate the feasibility of implementation of high-temperature stress sensors using dielectric insulation of the BOX layer of SOI wafers. REFERENCES [1] O. Slattery, D. O’Mahoney, E. Sheehan, and F. Waldron, “Sources of variation in piezoresistive stress sensor measurements,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 27, no. 1, pp. 81–85, Mar. 2004. [2] J. N. Sweet, “Integrated test chips improve IC assembly,” IEEE Circuits Dev. Mag., vol. 5, no. 5, pp. 39–45, Sep. 1990. [3] R. C. Jaeger, J. C. Suhling, M. T. Carey, and R. W. Johnson, “Off-axis sensor rosettes for measurement of the piezoresistive coefficients of silicon,” IEEE Trans. Compon. Hybrids Manuf. Technol., vol. 16, no. 8, pp. 925–931, Dec. 1993. [4] J. C. Suhling and R. C. Jaeger, “Silicon piezoresistive stress sensors and their application in electronic packaging,” IEEE Sensors J., vol. 1, pp. 14–30, 2001. [5] R. C. Jaeger, J. C. Suhling, and R. Ramani et al., “CMOS stress sensors on (100) silicon,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 85–95, Jan. 2000. [6] Y. Zou, J. C. Suhling, R. W. Johnson, R. C. Jaeger, and A. K. M. Mian, “In-situ stress state measurements during chip-on-board assembly,” IEEE Trans. Electron. Packag. Manufact., vol. 22, no. 1, pp. 38–52, Dec. 1999. [7] Z. W. Zhong, X. Zhang, and B. H. Sim et al., “Calibration of a piezoresistive stress sensor in (100) silicon test chips,” in Proc. Elect. Packag. Technol. Conf., 2002, pp. 323–326.


520


[8] J. Zhang, H. Ding, D. F. Baldwin, and I. C. Ume, “Characterization of in-process substrate warpage of underfilled flip chip assembly,” in Proc. IEEE Elect. Manuf. Technol. Symp., 2003, pp. 291–297. [9] J. N. Sweet, D. W. Peterson, and J. A. Emerson, “Liquid encapsulant and uniaxial calibration mechanical stress measurement with the ATC04 assembly test chip,” in Proc. 44th IEEE Electron. Compon. Technol. Conf., 1994, pp. 750–757. [10] D. W. Peterson, J. N. Sweet, S. N. Burchett, and A. Hsia, “Stresses from flip-chip assembly and underfill; measurements with the ATC4.1 assembly test chip and analysis by finite element method,” in Proc. 47th IEEE Electron. Compon. Technol. Conf., 1997, pp. 134–143. [11] M. Mayery, O. Paul, and H. Baltes, “Complete set of piezoresistive coefficients of CMOS n+diffusion,” J. Micromech. Microeng., vol. 8, pp. 158–160, 1998. [12] B. J. Lwo, C. H. Kao, T. S. Chen, and Y. S. Chen, “On the study of piezoresistive stress sensors for microelectronic packaging,” Trans. ASME, vol. 124, no. 3, pp. 22–26, 2002. [13] B. J. Lwo, T. S. Chen, C. H. Kao, and Y. L. Lin, “In-plane packaging stress measurements through piezoresistive sensors,” J. Electron. Packag., vol. 124, no. 6, pp. 115–121, 2002. [14] B. J. Lwo and S. Y. Wu, “Calibrate piezoresistive stress sensors through the assembled structure,” J Electron. Packag., vol. 125, no. 6, pp. 289–293, 2003. [15] T. S. Chen and Y. R. Huang, “Evaluation of MOS devices as mechanical stress sensors,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 25, no. 3, pp. 511–517, Sep. 2002. [16] M. Doelle, C. Peters, and P. Ruther et al., “Piezo-FET stress-sensor array for wire-bonding characterization,” J. MEMS, vol. 15, pp. 120–130, 2006. [17] A. T. Bradley, R. C. Jaeger, J. C. Suhling, and K. J. O’Connor, “Piezoresistive characteristics of short-channel MOSFETs on (100) silicon,” IEEE Trans. Electron. Dev., vol. 48, no. 9, pp. 2009–2015, 2001. [18] A. Sutor, R. Lerch, H. P. Hohe, and M. Gavesi, “New CMOS-compatible mechanical shear stress sensor,” IEEE Sensors J., vol. 1, no. 4, pp. 345–351, Dec. 2001. [19] A. D. Kurtz and A. Kane et al., “High accuracy piezoresistive internal combustion engine transducers,” [Online]. Available: www.kulite.com [20] O. Vallin and Y. Backlund, “High-temperature piezoresistive gauge fabricated on commercially available silicon-on-insulator wafers,” J. Micromech. Microeng., vol. 10, pp. 196–199, 2000. [21] B. Diem, P. Rey, and S. Renard et al., “SOI ‘Simox’ from bulk to surface micromachining, a new age for silicon sensors and actuators,” Sens. Actuators A, vol. 46–47, pp. 8–16, 1995. [22] K. Lee, H. Takao, K. Sawada, and M. Ishida, “Low temperature dependence three-axis accelerometer for high temperature environments with temperature control of SOI piezoresistors,” Sens. Actuators A, vol. 104, pp. 53–60, 2003. [23] R. L. Johnson, “High temperature silicon-on-insulator pressure sensor technology,” in Proc. 3rd Eur. Conf. High Temp. Electron., 1999, pp. 45–48.

[24] R. C. Jaeger, J. C. Suhling, and R. Ramani, “Errors Associated with the design, calibration and application of piezoresistive stress sensors in (100) silicon,” IEEE Trans. Compon. Packag., Manufact. Technol. B, vol. 17, no. 1, pp. 97–107, Feb. 1994. [25] O. N. Tufte and E. L. Stelzer, “Piezoresistive properties of heavily doped n-type silicon,” Phys. Rev. A, vol. 133A, pp. A1705–A1716, 1964.

Kuo Tian was born in China in 1982. He received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 2005. He is currently pursuing the M.S. degree in microelectronics in the Institute of Microelectronics, Tsinghua University. His research interests are MEMS, piezoresistive, and MOSFET stress sensors and their application in electronic packaging and chip reliability issues.

Zheyao Wang (M’07) was born in China in 1972. He received the B.S. degree in mechanical engineering and the Ph.D. degree in mechatronics, both from Tsinghua University, Beijing, China, in 1995 and 200, respectively. From 2000 to 2002, he was a Postdoctoral Research Fellow at the Institute of Microelectronics, Tsinghua University, where he worked on silicon micromachining for microsensor applications. In 2002, he joined DIMES, Delft University of Technology, Delft, The Netherlands, as a Postdoctoral Researcher, and worked on silicon micromachined components for 3-D packaging. He is currently an Associate Professor at Tsinghua University. His research interests include microsensors, silicon micromachining, and MEMS.

Min Zhang was born in 1984. He received the B.S. degree in mechanical engineering from Harbin Institute of Technology, Harbin, China, in 2007. He is currently pursuing the M.S. degree in microelectronics in the Institute of Microelectronics, Tsinghua University, Beijing, China. His research interests are microsensors and their biomedical applications.

Litan Liu received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 1970. He is currently a Full Professor at the Institute of Microelectronics, Tsinghua University. His research interests include the development of semiconductor devices and integrated circuits. His current research includes the development of integrated sensors and microelectromechanical systems. He has authored and coauthored more than 150 peer-reviewed journal and conference papers and supervised 20 Ph.D. students.
