Apr 2, 2000 - The two structures are the diode bridge and the switched emitter follower (SEF). The output in the diode bridge (shown in Fig. 2) tracks the input ...
Design issues on high-speed high-resolution track-and-holds in BiCMOS technology C.Fiocchi, U.Gatti and F.Maloberti
Abstract: The authors address some fundamental issues in track-and-hold (T&H) design. A number of explicit expressions characterising the main limitations of this class of circuits are given. A fully differential open-loop T&H is presented satisfying the stringent specifications imposed by present telecom applications. It exhibits high-resolution (12 bit) and high-speed V;.k = 160MHz) as measured on samples integrated in a standard 0 . 8 12-GHz ~ BiCMOS technology. The overall performance is beyond state-of-the-art.The T&H's size is 0.37mm2,and it consumes 45mA from a 5V power supply.
1
Introduction
The evolution in radio communication systems has been towards increasing complexity and, at the same time, wider flexibility [11. Consequently, the most suitable approach has been to digitise the analogue signal as soon as possible and to devolve all the processing to DSP, which can be easily reconfigured via software. However, the new telecom architectures foreseen for this task provide challenging specifications for A D converters, by requiring high-speed cfck > lOOMHz), high resolution (12-14 bit) and linearity (spunous free dynamic range, SFDR < -97dB). Although it is possible to implement complex algorithms to digitally correct the internal blocks of an ADC, the bottleneck in the conversion system is the input T&H, whose non-idealities cannot be compensated by computations. A variety of T&Hs have already been presented, dealing with different targets: very high-sampling-rate low-resolution [24], high-sampling-rate low-voltage medium-resolution [5], [6], high-sampling-rate high-resolution [7-141. This work focuses on the last class, by examining the main limitations both in frequency and precision and deriving explicit analytical expressions. Starting from these, the structure and building blocks of a 12-bit 160MHz track~ technology are and-hold realised in a 0 . 8 BiCMOS described together with extensive experimental results. 2
Track-and-hold principle
The logical block diagram of a track-and-hold is shown in Fig. 1. We distinguish three sections: the input buffer (IB), the sampler (SMP) and the output buffer (OB). The main purpose of the IB is to decouple the signal source and the sampling section, whose input capacitance can be quite 0 IEE, 2000
IEE Proceedings online no. 2oooO200 DOL 10.1049/ipcds:2oooO200 Paper fmt received 1 lth January and in r e d form 22nd September 1999 C. Fiocchi is with Mkron AG, C o m Mazzini, 3,27100 Pavia, Italy U. Gatti is with Italtel S.p.A., R&D Lab., Col, 20019 Settimo Milanese, M h o , Italy F. Maloberti is with the Department of Electronics, University of Pavia, Via Ferrata, 1,27100 Pavia, Italy 100
high. This function must be performed without introducing distortion and with suitable speed. The simplest buffer can be realised using a MOS follower (level-shifter). However, the distortion introduced by PMOS or NMOS devices is very high: the transconductance is lower than the bipolar counterpart and the body effect affects the threshold of MOS devices if their body cannot be shorted to the source. Therefore, it is better to use bipolar transistors instead. To assess the possible accuracy, we calculate the expected distortion when a BJT level-shifter drives a capacitance c,. Here, and in the rest of the paper, we shall refer only to the third harmonic. All the even harmonics can be cancelled with the use of matched differential structures. If the output resistance of the current source is reasonably high, the Vbe modulation mainly due to the current flowing in C, leads to:
where V , is the themdl voltage, Vp is the signal peak amplitude,fi;, is the input frequency, C, the sampling capacitance and Zbl the level-shifter bias current. For example, using Zbl = 2mA, C, = 5pF,J;, = 100MHz, Vp= 0.25V, a distortion of at least 4 6 d B is obtained.
"+--Pc*F
T l'leak
I- -SMP __-A
Fig. 1
Truck-d-hold principle
Eqn. 1 establishes also a relation between the gain-bandwidth product of the level-shifter and the expected distortion. Considering that
we have:
IEE Proc.-Cir.cuit.\ Devices S y s I . . Vol. 147,No. 2. April 2000
Eqn. 2 futes a lower limit for the GBW if very low harmonic distortion is needed. For example, using the above figures, to achieve HD, = -84dB, the GBW must be at least 5GHz. Let us consider now the sampling and hold operations (SMP). The simple implementation shown in Fig. 1 uses a MOS switch and a capacitor. However, the nonlinear behaviour of the r, resistance with V, and the nonlinear clock-feedthrough limit the distortion performance of the sampler. Therefore, once again, BJT-based solutions should be preferred. For any circuit implementation, another important source of imperfection is the so-called ‘aperture error’. The non-zero time over which the T&H disconnects from the input is the so-called ‘aperture time’ tA. Since tA generally depends on the instantaneous slope of the input signal, variations produced in tA, i.e. AtA, cause an aperture error. It, in turns, introduces distortion to the held samples. For conventional T&H topologies [lo], the typical At, modulation does not guarantee an equivalent linearity better than 10 bit. The last block in Fig. I is the output buffer OB. It exhibits distortion and settling limitation, sirmlar to those in the IB. In addition, we have to account for the droop rate. It results from discharging currents in the hold phase. If the discharging currents are a nonlinear function of the signal, a distortion is produced. As shown in Fig. 1, Rp represents the input impedance of the OB. If Rp is linear, the voltage on C, after an hold period of T becomes:
I
ances. The two structures are the diode bridge and the switched emitter follower (SEF). The output in the diode bridge (shown in Fig. 2) tracks the input by forcing the bias current I, into four diodes, thus providing a low impedance path from the input to the sampling capacitor. The hold mode is achieved by switching the bias current through Qsl: the diodes go off and the sampling capacitor is disconnected from the input. Fig. 3 shows an improved version of the basic topology. There, a unity gain buffer and two diodes Q, and Qb equalise the swing of nodes 1 and 2 during the hold period. This, in turn, limits charge injection through parasitic capacitances. Implementing the buffer, however, is a difficult task as it must provide a unity gain, a very fast settling time and a large current driving capability. Fig. 4 presents the circuit principle of the switched emitter follower. During the track phase, the emitter follower is normally biased, thus transferring the buffered signal to the output. During hold phase, transistors Q,, and Qs2 deviate the current Ij, turning Qoutoff. The sampling capacitance is insulated and holds the stored signal. The distortion of a SEF is dominated by the contribution of the output emitter follower. Therefore, we can again use eqn. 1. Observe that we achieve the track-to-hold transition by draining the current generator Ib from the output node of the IB. Thus, even if V, rises the base of Qoutis kept low and maintains the transistor off. In fact, the base voltage of Qoutis VI,- RIh. Therefore, ensuring RIj >
5,
VDD
That would cause an offset error and a gain error. Unfortunately, with bipolar emitter followers, the input impedance is RI, = r/, + prcf, where /3 is a nonlinear function of V,. Therefore, the droop rate error becomes a nonlinear function of the input voltage. In tum, harmonic distortion appears. In addition to the above non-idealities we have also to consider other spur sources. Among them the thermal noise. Since the thermal noise of active devices is inversely proportional to g,,, the use of bipolar devices with large bias current and low intrinsic base resistance is recommended. A second source of possible performance degadation is the clock jitter. It causes a sample-to-sample variation in time between the effective points at whch the samples are actually taken. Clock jitter is often due to phase jitter on input signals or unwanted phase-modulation of the sample clock by random noise, supply line noise or digital noise caused by an inaccurate physical layout. By considering a ‘white noise model‘, the SNR can be expressed by [151:
I I 1
Tl ub.
lb
II
lbI
I I I
IB
lol
’
SMP
Fig.2 Schematic diugrum of dwde-bridge shcture
I
‘DD I
1
1
where tJ,RMSis the root mean square value of the jitter (assuming a Gaussian distribution). To obtain a SNR equivalent to 12 bits with a lOOMHz input signal, a t/,RMs lower than 0.32~sis needed. From the above considerations, it seems that if we deal with a BiCMOS technology it is preferable to use bipolar devices in all signal paths, while the presence of MOS could guarantee good upper current mirrors and a better droop rate. 3
Conventional track-and-hold structures
This paragraph considers two track-and-hold structures published in the literature and compares their performIEE Proc -CircultA Devrcec Syst , Vol 147, No 2 April 2000
“out 4
*i
Qb
I
I I I I I IB I
*
SMP
Fig.3 Schmnatic hgrm of improveddwde-bridgestructure 101
QOutremains off with any possible input signal. With a typical signal of 5 = 0.25V, we achieve the required drop with R = l00Q and Ib = 2.5mA. These figures are acceptable even if the circuit can suffer by some speed limitation. I
VDD
I
t
I
U
I
Fig.4
At high frequency the implementation in Fig. 5 suffers of the following limitation: the inverse current-to-voltage conversion performed by the series Q3-R3 (and Q4-R4) only partially corrects the nonlinearity of the input pair Q,-R, (and QTR2). At very high frequencies possible m i s matches of relative delays critically affect the expected compensations. In addition, the clock rate is limited by the time constant due to R3 and R4 and the parasitic capacitance at nodes A and B. An evolution of this topology proposed by [14] overcomes some h t a t i o n s . However, since it makes use of an IB similar to that in Fig. 5, it suffers from the same problems at high frequencies, which limits its resolution to 10 bit. A final point to keep in mind concerns the voltage of nodes A and B in the hold mode. The extra-currents Ib flow through the input buffer loads and pull down the voltage of A and B as required. However, their value can be so low as to bring transistors Q1 or Q2 into the saturation region.
Sbnplfzd schematic diagrm of witched emitterfollower I
VDD
I Q0"t
Vout2 --P
cs
*
I IB
SMP
Fig.5
1
IB
1
SMP
SMP
Fig.6 Schematic diagrm of SEFproposed by authors
Schematic diagrm of SEFproposed in [8]
Fig. 5 shows a possible implementation [7, 81 of the SEF. It is made up of an open-loop input buffer (Q1 to Q4, RI to R4) and two SEF sampling stages. During the track phase the input signal is transmitted between nodes A and B and through Qoutl,Z to the output. During hold phase, transistors Qsl are on and the current flows through R3 and R4, producing a voltage drop that lowers the base of Qoutl,2. Both structures in Figs. 2 4 show an excellent speed: they do not use feedback in the track mode and achieve a good linearity thanks to the use of bipolar devices. Nevertheless, the diode bridge is less effective than the SEF solution. In the diode bridge architecture the input signal passes through two junctions, and t h s causes a double distortion and a lower bandwidth. It can be shown that the third harmonic of the diode bridge sums up two terms, one due to the input level-shifter and the other caused by the diode bridge itself [16]:
7-
Fig.7 Input &fer with non-ideal current sources
4
In particular, the second term in eqn. 5, with zbl = Ib, leads to a worsening by lOdB with respect to the SEF HD,. To maintain a performance similar to that of the SEF the diode bridge should increase its DC current. Ths, in turn, increases the power consumption and, moreover, it may worsen the switching noise of the supply lines. 102
I
New track-and-holdtopology
We have seen in the previous Section that the SEF architecture is better than the diode bridge, especially when our key goal is high resolution. However, it is possible to improve the SEF performances by using the ameliorating solutions that will be discussed in t h s Section. A first improvement results from the input buffer. Fig. 6 shows the circuit used. The signal at node A is a replica of the input because of the shift down of Qin(at node B) and the shift up of the diode connected element Qd. Since the current in the two transistors is the same, the two levelIEE Proc.-Circuits Devices Sysr., Vol. 147, No. 2, April 2000
shifters match and possible nonlinearities are cancelled. Note that, in the hold mode, the current through QSlpulls down the voltage of node A until the clamping transistor QcIpturns on and fwes the voltage of node A one Vk below the input. The diode connected transistor Qd is reversal biased. Therefore, we avoid the risk to push the input transistor Q,, into saturation. The impedance driving node A 2/gm,,,is very low. Consequently, the time constant is reduced and unwanted ringing effects (whch will be discussed later) are minimised. Moreover, the huge bandwidth of the stage guarantees a satisfactory distortion performance. Typical performance for 16, = 2.5mA is GB W > 5GHz and Rout< 20Q. However, the linearity of the proposed buffer is affected by the nonideality of current generators. If the input voltage increases by AV,,, nodes A and B in Fig. 7 increase by the same amount and the current in Q,, and Qd changes by A V , ( l / R A + l/RB)and -AV,JRA, respectively, where R A and RB are the output resistances of current generators. Therefore, the V,, values of the two bipolar transistors do not match any more and a difference between input and output results:
Because of the nonlinear behaviour of eqn. 6 and of R A and R ,harmonic distortion results. To minimise the effect, it is necessary to use current sources with high output resistance up to the frequency of operation. A general problem of all the T&H circuits concerns the so-called ‘pedestal error’ Ep. This is defmed as the error introduced to the voltage stored in the sampling capacitor during switching phase and is due to a charge injection or a capacitive coupling between the clock and the held signal through the capacitance C,, of switches Qsl and Qs2.An analysis of the third-order harmonic gives [16]:
(7) where V,,, is the single-ended output voltage when the input signal is zero; Vpthe input voltage amplitude; Nd and Q0 technology parameters. V& dr is the driving signal average value, V,, is the clock swing, and C, is the base-collector capacitance of the switches when Vp= V,, = 0. Typical values lead to about -90dB distortion due to this cause only. Because of the nonlinear nature of the parasitic capacitance, the use of a differential structure (obtained by doubling the structure) also helps to reduce, but does not completely solve, pedestal error. From eqn. 7, a first solution to the problem could be a lower value of V,, dr. However, it must be compatible with the required dyna;nic range of the I,. Fig. 6 employs a more straightforward solution: using dummy switches Qdml and Qdd with open emitter. They are driven with opposite phases and inject a charge through their CbC The charge of dummy switches compensates the one given by normal switches, limiting this effect only to nonlinear and m i s match contributions. We have a second cause for pedestal error if the pulling down of node A and the I b switching are not at the same time. If node A falls down before, the current through Qs2 discharges a bit the hold capacitance. If the current in Qs2 drops before, the V,, voltage of QOutdiminishes, pulling up the output voltage. A differential configuration minimises the error so long as everythmg is matched. In particular, the differential version of the circuit in Fig. 6 ensures equal IEE Proc.-Circuits Devices Syst., Vol. 147, No. 2, April 2000
swing of node A and its differential counterpart when switching from the track to the hold mode: both nodes change by v b p By contrast the solution used in [9] leads to asymmetry: the voltage of node A and its differential counterpart are clamped at a fuced voltage. Another general problem in T&H topologies is the socalled hold-mode feed-through (HMF). It is a perturbation of the held signal due to imperfect insulation between the input and the output during the hold phase because of parasitic stray capacitances. In the implementation of Fig. 6 transistor Qclphas its base connected to V,,. During the hold phase a fraction of the signal appears at the output. It and C,. is due to the nonlinear capacitive divider Cb‘e,ouf Therefore, the HMF is given by:
(
H M F = 2010g A,
+ cs
Cb’e,out Cb’elout
)
(8)
where A , is the gain of Q,,, and is the intrinsic baseemitter capacitance of QOut.For typical values Cb’e,out= lpF, C, = lOpF and A , = 1, it follows that the HMF is -20dB. To circumvent this error, the solution in Fig. 8 (shown in a single-ended arrangement), biases the base of QcI, with a replica of the hold signal. Actually, in the hold mode, node A is controlled by two paths, one through Qclp and the other through the parasitic capacitance C b e , d and 1/gm,,,. Therefore, the hold-mode feed-through worsens at angular frequencies higher than gm,clJCb’e,dFor a typical technology we can assume Cb‘e,d = 0.15pF, gm,cb= 0.3Q-’. Therefore, with an input frequency of lOOMHz the HMF is as good as -80dB. The proposed solution is equivalent to that in [14], but is realised in a simpler manner and with reduced current consumption. Hold-mode feed-through can be compensated with crossed feed-forward capacitors as proposed in [SI.That compensation techtuque is not very effective since it must rely on matching of nonlinear capacitors. Instead, the compensation approach used together with the replica of the hold signal further improves the HMF. This is achieved in the circuit of Fig. 9 that includes two feed-forward capacitors CR between node A (A) and B’ (B). CKis the series-parallel connection of four diodes [SI, as shown at the bottom of the same Figure. The simulation results show an HMF as low as -100dB. IB
SEF
OB
VDD
Fig.8
Completeschematicofproposed trackandhold (smgk-endedversion)
The unity gain buffer driving QcIpcan generate kick-back noise that affects the output signal. The duplication of the SEF shown in Fig. 8 avoids this possible drawback. Actually, the hold capacitance of the auxihary SEF is not connected to ground but to the degeneration resistance of the current source Ib. This connection dynamically changes 103
Fig.9 Schematic &gram of proposed SEF with holu-nwdefeed-through compematwn and practical inplementatwn offeedforward capacitances
the value of during track mode, bootstrapping the current delivered to the sampling capacitance C,. The qualitative result is that the modulation of vb, of Qout is reduced benefiting the harmonic distortion [Ill. Using in our design C, = 8pF and Ib = 8mA, an improvement of about lOdB was obtained in THD. Besides the harmonic distortion, the nonidealities in the track phase are related to settling and speed. Settling must be completed within a fraction of the track period (AT,) and this will demand a large bias current: during the hold interval (ATH)an input sine-wave may change by VpmAT,. Therefore, with Vp = 0.25V, U = 2n100Mrad and AT, = 2.511s (supposing a 200MHz clock rate), the SEF bias current should exceed 0.8mA/pF to acheve settling within 1/5 of ATP r-------------------
c @
~ ~ b ~ ~ ; ~ o l + Q o u t Cb'e,out
VI"
I L-----
glll,OUtVbe
e
--------_-_--
; I
The relationship of eqn. 10 leads to a strict limit on R, as g,,,,,/C, (the bandwidth of the SEF) needs to be quite large to ensure minimum harmonic distortion. Let us assume = 2mA, rbb, = 40Q, C, = 10pF, Cye,our= lpF, the driving resistance R,,, must be lower than 25Q to satisfy the relationship. This requirement contrasts with the need for a suitable voltage drop to guarantee Q,,, is turned off in solution [8]. Instead, the proposed solution exhibits a low output impedance (2g,,i, = 20Q), which avoids ringing. The final output buffer (Fig. 11) drives the capacitance of the following circuitry. It has a single stage local-loop structure similar to the input buffer. However, its input impedance is enhanced by bootstrapping the collectoremitter resistance of Q,, rol. The collector of Q, is biased with the output voltage that tracks the input. In our circuit the small signal input impedance increases by a factor approximately equal to 10.
I I "samp
J-
cs Fig. 10 Small s i w l equivalent circuitfor SEF output section
The major limit to speed comes from the network driving the output transistor Q,,. I k s network can be schematised with the equivalent circuit in Fig. IO. Its transfer function has one zero and two poles: Vsamp
Kn
-
S R I
SR.
K+STi
S2Ti
cs(RZn-k T b b ' ) -k S [cs (Rtn+T66/ ) + c s T x + T i ] +K
(9) where zl = r,Cye,,,, and K = 1 + g,,ou,r, Therefore, to avoid ringing, the Q-factor must be less than 0.707 [16]. Assuming that C, > Cye,,,, and that R,,+ rbb' > r, we must satisfy the following condition:
104
Fig.11 Schtmtic dhgram of output &fer
A simple circuit (shown in the same Figure) compensates for the input transistor common-mode base current. Transistors Mbl and Mb2 mirror the base current in Q4 and inject it into the base of Q1. Since the base current of Q4 is the same as in Q1, an ideally perfect compensation of the base current is acheved, reducing the common-mode voltage droop during the hold phase. IEE Proc.-Circuits Devices Sysl , Vol. 147, No. 2,April 2000
5
Experimental results
An experimental T&H (without compensation capacitances 'C was fabricated using a 0 . 8 double-metal ~ double-poly BiCMOS technology and occupied a 0.37mm2 area. The die includes two T&Hs for dynamic testing purposes, bandgap references and clock buffers. Its micrograph is shown in Fig. 12. v
Fiig.12 Die micrograph
to the circuit. The T&H outputs were fed to another balun transformer driving a spectrum analyser. For all measurements the load was 50Q//lOpF. Fig. 13a shows the output spectrum with a 77MHz, 1 Vppinput signal with the circuit in track mode. The second harmonic acheved is -87dB below the fundamental one, while the thrd is not si&icant. In contrast to the simulations, where the third harmonic was dominant. the measurements indicate an hgher second harmonic, due to imbalances between the positive and negative paths induced by T&H layout mismatches and external component nonidealities (transformers, filters, etc.). Fig. 13b reports the output spectrum under the same condition with a clock of 160MHz. The second harmonic was around -72dB below the fundamental one, while the thrd was lower than -76dB. It is important to note that in ths test the entire output waveform was analysed, whereas when a front-end for the ADC is used only the held values of the output are to be considered. Since the waveform exhibited slewing at the beginning of the track phase, this measurement represented a worst-case condition for the harmonic distortion. Moreover, the fundamental had an amplitude of around -5dB because of the attenuation introduced by the output transformer. The graph in Fig. 14 illustrates the degradation of the total harmonic distortion as a function of the sampling frequency. At the maximum frequency (250MHz) we again acheved 10 bit resolution (THD = 61dB). The dependence of the distortion on the signal amplitude indicates that it becomes -74dB when the input signal is 0.5 V,, with the same clock rate. Fig. 15 reports the hold-mode feed-through spectrum when An = 77MHz and the input amplitude is 1 Vpp. We achieve a hold-mode feed-through rejection of 6 8 d B (including the balun attenuation). Finally, the differential droop rate was limited to 122pV/ns, whle the common-mode droop rate was 250pV/ns, which corresponds to an input current of 2pA for the T&H output stage.
-
1
-60
-62 -64
-66 -
m
U
-
&68
I I-
-70 -
a
-72
-
-76I
100
I
130
I
160
190
220
I
250
frequency, MHz
Fig. 14 Degrmhtion of THD usfunction of clockfiequency
ampl. = 1 V p p ; h= 77MHz
b
Fig. 13 Memrcd output spectrum (in dB) of T&H in responye to 77MHz input sine wave (lOdB/div)
a Track mode h With a clockf, of 160MHz
The sine wave at the output of a signal generator was filtered by means of a band-pass high-selectivity filter, split into differential signals by a balun transformer and applied IEE Proc-Circuits Devices Syst., Vol. 147, No. 2, April 2000
Fig. 15 , Meanaed output spectrum of T&H in respome to 77MHz input sw wave M hold mode 105
Table 1 summarises T&H performance parameters. The current consumption for each T&H is 45mA (including output b&ers) operating with a 5V supply. Table 1: Performance summary Feature
Performance
Technology
12GHz BiCMOS
Pedestal error
< 2mV
Total harmonic distortion
-70dB @ 77MHz
Hold-mode feed-through
4 8 d B @ 77MHz
Analogue bandwidth
250MHz
Max differential input signal
1VPP 250MHz
Max sampling rate Droop rate
122wV/ns (@ 1VPp)
Load
5052//10pF
Current consumption
45mA @ 5V
6
Acknowledgments
This work was supported by CEC under the Esprit Project 8795 AMFIS. The authors thank Mr G. Gazzoli at the Italtel Radio Mobile Business Unit, Mrs S. Mazzoleni at the Italtel Quality Department and Mr P. Costa at the Department of Electronics of the University of Pavia for their help and their contribution to this work. 7
References
1 SCHWEBER, B.: ‘Converters restructure communication architecture’, EDN, 1995, pp. 5 1 4
106
2 ROHMER, G.: ‘An 800 MSps track and hold using a 0.3 pm AIGaAs-HEMT-technology’. IEEE GaAs symposium, Dig. tech. papers, 1994, pp. 236 ff. 3 POULTON, K., CORCORAN, J., and HORNAK, T.: ‘A 1-GHz 6bit ADC system’, ZEEE J. Solid-state Circuits, 1987, 22, pp. 962-970 4 PREGARDIER, B., LANFMANN, U,, and HILLERY, W.J.: ‘A 1 Gsampleis 8 b silicon bipolar track and hold IC‘. ISSCC digest of technical papers, 1995, pp. 58-59 5 RAZAVI, B.: ‘Design of a 100-MHz IO-mW 3-V sample-and-hold amplifier in digital bipolar technology’, IEEE J. Solid-State Circuits, 1995,30, pp. 724730 6 RAZAVI, B.: ‘A 200 MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply’, IEEE J. Solid-State Circuits, 1995, 30,pp. 1 3 2 6 1332 7 PETSCHACHER, R., ZOJER, B., ASTEGHER, B., JESSNER, H., and LECHNER, A.: ‘A 10-b 75-MSPS subranging A/D converter with integrated sample and hold‘, ZEEE J. Solid-State Circuits, 1990, 25, pp. 1339-1346 8 VORENKAMP, P., and VERDAASDONK, J.: ‘Fully bipolar, 120Msampleis 10-b track-and-hold circuit’, ZEEE J. Solid-State Circuits, 1992,27, pp. 988-992 9 SONE, K.: ‘ A 10b 100 Mds pipelined subranging BiCMOS ADC‘. ISSCC digest of technical papers, 1993, pp. 66-67 10 COLLERAN, W.T., and ABIDI, A.: ‘A lO-b, 75-MHz two-stage pipelined bipolar A/D converter’, IEEE J. Solid-State Circuits, 1993, 28, pp. 1187~1 I99 11 MURDEN, F., and COSSER, R.: ‘An 12b 50 MSamplds two-stage A/D converter’. ISSCC digest of technical papers, 1995, pp. 27&279 12 FIOCCHI, C., GAlTI, U., and MALOBERTI, F.: ‘A IO-bit 250MHz BiCMOS track-and-hold’. ISSCC digest of technical papers, 1997, pp. 1 6 1 4 5 13 VORENKAMP, P., and ROOVERS, R.: ‘A 12b 50 Msamplek cascaded folding and interpolating ADC‘. ISSCC digest of technical papers, 1997, pp. 134-135 14 BAUMHEINRICH, T., PREGARDIER, B., and LANGMANN, U,: ‘A I-Gsampleis 10-b full Nyquist silicon bipolar track and hold IC‘, IEEE J. Solid-State Circuits, 1997, 32, pp. 1951-1960 15 RAZAVI, B.: ‘Principles of data conversion system design’ (IEEE Press, 1995) 16 FAIULO, G., FIOCCHI, C., GATTI, U., and MALOBERTI, F.: On the design of high-speed high-resolution track and holds’. Proceedings of ISCAS’96, 1996, pp. 73-76
IEE Proc-Circuits Devices Syst., Vol. 147,No. 2, April 2000
