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This conversion requires sev- eral digital filters working at very high sample rates with low power consumption. The input sample rate is 160 MHz and the output ...
Design of a Digital Down Converter Using High Speed Digital Filters Henrik Ohlsson, Håkan Johansson, and Lars Wanhammar Department of Electrical Engineering, Linköping University, SE 581 83 Linköping, Sweden email: {henriko, hakanj, larsw}@isy.liu.se Abstract The digital down converter (DDC) is used in the front-end of a multiple-antenna radar. This conversion requires several digital filters working at very high sample rates with low power consumption. The input sample rate is 160 MHz and the output sample rate is 40 MHz. To find suitable filter structures for the implementation of the DDC, several filter structures were evaluated. Both recursive and non-recursive filter structures have been considered. These filter structures were evaluated with respect to implementation properties and suitable structures were identified.

1. Introduction This paper presents some results from the study of the digital filters used in a DDC. This project is part of a smart sensor project [1]. Our responsibility is to evaluate and implement some different digital filter structures suitable for the DDC implementation and identify the best candidates among these structures. Factors that have been considered in this evaluation are low power consumption and small chip area. Also, the sample rate of the incoming signal to the DDC is very high. This makes it important to find suitable filter structures for high sample rates.

2. Digital Down Conversion The main purposes with the DDC are to transfer the radar signal band into baseband, splitting the signal into its I and Q parts, and to reduce the sampling rate of the signal. The sampling rate reduction is needed to reduce the complexity of the digital signal processing performed later in the system. For this system the input sample rate of the DDC has been decided to be 160 MHz and the incoming signal bandwidth has been decided to be 36 MHz. This gives that the total decimation factor of the DDC should be four, i. e., the signal sampling rate should be reduced to 40 MHz in each channel. The DDC implementation is divided into two parts, one IQ-split stage and one decimation stage, see Fig. 1. The IQsplit is performed using a hilbert transformer, implemented with the digital filter H 1 ( z ) [7]. One result from the IQsplit is a sample rate reduction with a factor of two in each channel. Every even sample is used in the I-channel and every odd sample is used in the Q-channel. This means that the decimation stage only needs to perform a decimation by another factor of two. This is performed using another digital filter H 2 ( z ) , with one such filter each channel. Since the main function of both the IQ-split and the decimation stages is performed with some type of digital filters, a wide range of filter structures may be used. Thus, finding the most suitable filter structures, considering power consumption and chip area, is of great importance. 2

H2(z)

2

I

2

H2(z)

2

Q

H1(z)

Figure 1: The DDC filter configuration.

3. Digital Filters for DDC A class of filters suitable for both interpolation and decimation with a factor of two is so called halfband filters. An efficient method for implementing such filters is the use of polyphase structures. This method may be used for either recursive or non-recursive structures [7].

The first halfband filter structure considered is based on FIR-filters which are non-recursive structures. An example of a halfband FIR filter is shown in Fig. 2. This kind of filter can be made to have a linear phase response, yielding a constant group delay. Another property of FIR filters is that they can be used in systems with very high sample rates. This is possible since the FIR filter structure may easily be pipelined. x(2n)

T

T

T

T

a4 T

a1

a2

T

T

y(n)

a3

Figure 2: A seventh order halfband FIR decimation filter.

A drawback of FIR filters is that they are quite complex, considering the number of hardware recourses needed. This gives that the chip area required may be large. The high complexity also yields a high power consumption. The complexity of the implementation is proportional to the filter order needed for a certain specification and the filter order increases significantly when the filter specification gets more difficult. Thus, FIR filters have some properties that makes them suitable for the DDC implementation, mainly the linear phase response and the possibility of using high sample rates. However, the potential large chip area needed and the possible high power consumption, especially for narrow transition band filters, are a problem. The other class of halfband filters considered are so called bireciprocal lattice wave digital filters, (BLWDFs). As for the halfband FIR filters, the BLWDFs are suitable for interpolation and decimation with a factor two. An example of a BLWDF is shown in Fig. 3. T

a3

T

a7

x(2n)

a0

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a9

T

T

T

T

T

a0

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Figure 3: An eleventh order BLWD decimation filter.

The BLWDFs have some very important properties. For example, they can be made to guarantee stability, which is an important property for recursive filters. Also, the filter orders are often lower than for the corresponding FIR filter, especially when the filter requirements are difficult. Finally, these structures have a very low coefficient sensitivity in the passband, which corresponds to the possibility to have short coefficient word lengths. However, BLWDFs are recursive structures which means that the maximum sample rate possible to achieve with a certain structure is limited by the longest loop latency of the structure [6]. In Fig. 3 the structure of the adaptor used in a BLWDF is shown. From this figure it can be seen that each adaptor results in one recursive loop with two additions, one multiplication and one delay element. This configuration corresponds to a sample rate bound of T min = T mult + 2T add , where T min is the minimal sample period, T mult is the latency of the multiplication and T add is the latency of the additions. If we look at the complexity of the implementation of the two arithmetic operations, addition and multiplication, the later is by far the most complex. Hence, the latency of the multiplication is the main contributor to the sample period bound. A major reduction of T min is possible if T mult can be reduced. This can be done by, for example, using an efficient multiplier structure. Another possibility is to have filter structures with as low coefficient word lengths as possible, which gives a simplified multiplier. It is important to achieve a structure

with as low T min as possible since any excessive speed may be traded for low power consumption by reduction of the supply voltage [2].

4. Presentation and Evaluation of the Different Filter Structures First we considered a filter structure where both H 1 ( z ) and H 2 ( z ) are FIR filters. The second filter structure considered was an FIR-WDF solution where H 1 ( z ) is an FIR filter and H 2 ( z ) is a WDF. For the third, and final filter structure both H 1 ( z ) and H 2 ( z ) are WDFs. The magnitude responses for the filter stages are shown in Fig. 4 H2(z)

Htot(z)

0

0

−20

−20

−20

−40 −60 −80 −100

Magnitude [dB]

0 Magnitude [dB]

Magnitude [dB]

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−80

−100

0 Angle [deg]

−100

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−80

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0 Angle [deg]

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0 Angle [deg]

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Figure 4: Magnitude responses for the filter stages

These different structures have been evaluated with respect to their implementation properties and some different measures have been considered. One measure, which gives a rough estimation of the complexity of an implementation, is the filter orders needed for each filter stage. Another measure is the number of different hardware resources needed, such as multiplications and additions. The latter yields a more relevant result since that also depends on the filter structure selected. As can be seen in table 1, the different filter structure solutions yields some differences in hardware resources needed. The FIR-FIR solution would require a significantly larger amount of chip area compared to the other two structures. The FIR-WDF and WDF-WDF solutions seem to require about the same amount of hardware. However, there are some problems which may arise when going for the WDF-WDF solution. Then we have a recursive structure, working at the higher sample rate. This could give problems for the implementation due to the critical path limitation of recursive structures mentioned above. Filter Structures

Filter Order - H 1 ( z )

Filter Order - H 2 ( z )

Multiplications

Additions

FIR - FIR

14

78

45

86

FIR - WDF

14

11

15

40

WDF - WDF

7

11

13

42

Table 1: Comparison of the different filter structures

5. New Filter Structures for Decimation As mentioned above, reducing the coefficient word lengths reduces T min . This can be achieved by cascading several filter stages. This means that the requirements on each of these filters are relaxed and the coefficients of each filter stage can be quantized to a shorter word length. However, this is not an efficient method for implementing decimation filters. By cascading several such filters, only one of the stages may operate with the lower sample rate. This is not a suitable solution, if a high sample rate and a low power consumption are needed. A solution to the problems described above, using cascaded filters, has been proposed in [3]. The idea is to take the transfer function of the cascaded structure and rewrite it to a form where all the filter operations can be performed at the lower sample rate. An example of a structure corresponding to two cascaded filters is shown in Fig. 5. Also, this kind of structure has been shown to reduce the amount of hardware resources needed for implementing it compared to

the standard WDF structure [5]. Thus, the gain achieved when using a cascaded structure is that the maximum sample rate is increased with a reduction of the hardware resources required. T

T

a0

a0

y(n)

x(2n) T

T

a1

a1

T T

2

a1

Figure 5: A simplified structure, corresponding to the example filter in Fig. 3, derived from two cascaded halfband filters

6. Conclusions Some different filter structures for DDC have been considered. Among these, two solutions, an FIR-WDF structure and a WDF-WDF structure, were identified as the most suitable. However, the latter structure may be difficult to implement due to the high input sample rate. One solution to that problem may be to use the cascaded filter structure introduced above. Another important consideration when implementing digital filters is the logic style used for the actual silicon implementation. Such evaluation requires a design path that reduces implementation times significantly. Currently, work is going on to find the critical design steps and make these steps more efficient. For this evaluation we will consider both well known logic styles and new logic styles. Especially we will evaluate a newly, at our department, developed logic style, namely differential NMOS logic [4].

7. References [1] [2] [3] [4] [5]

[6] [7]

Brodén S., Danestig M., Folkesson K., Ohlsson H., Svensson B., and Åström A.: “Smart Sensors”, Proc. RVK-99, Karlskrona, Sweden, 14-17 June, 1999. Chandrakasan A.P. and Brodersen R.W.: “Minimizing Power Consumption in Digital CMOS Circuits”, Proc of the IEEE, Vol. 83, No. 4, pp. 498-523, April 1995. Johansson H.: Synthesis and Realization of High-Speed Recursive Digital Filters, Diss. No. 534, Linköping University, Sweden, 1998. Karlsson M.: Distributed Arithmetics: Design and Applications, Thesis No. 696, Linköping University, Sweden, 1998. Ohlsson H., Johansson H., and Wanhammar L.:“Implementation of a Combined High-speed Interpolation and Decimation Wave Digital Filter” in Proc. IEEE Int. Conf. Electronics Circuits Syst. ISECS’99, Pafos, Cyprus, pp. 721-724, Sept. 5-8, 1999. Renfors M. and Neuvo Y.: “The Maximum Sampling Rate of Digital Filters Under Hardware Speed Constraints”, IEEE Trans. on Circuits and Systems, CAS-28, no. 3, pp. 196-202, March 1981. Wanhammar L. and Johansson H.: Digital Filters, Linköping University, Sweden, 1999.