Design of an integrated CMOS operational amplifier with low probability EMI induced failures A. RICHELLI, L. COLALONGO, Zs. M. KOVÁCS-VAJNA Dept. of Electronics -DEA, Univ. of Brescia (ITALY) {richelli, colalong, zkovacs}@ing.unibs.it Abstract In this paper the design of an operational amplifier with enhanced immunity to electromagnetic interference (EMI) conveyed to the input terminals is presented. It has a symmetric topology, based on two main blocks; the first is a fully differential folded cascode and the second is a source cross-coupled AB class buffer. The integrated circuit has been fabricated in a 0.8µm n-well CMOS technology (AMS CYE process). Its main features are: a gain of 93 dB, the GBW of 10.4 MHz and a symmetric slew rate. The supply voltage can range from 3.3 to 5V.
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wanted or not, even at frequencies outside the working bandwidth of the circuit [1-3]. In recent years, due to the increasing adoption of electronic and microelectronic equipments, EMI has been more and more carefully studied [3] and experimentally evaluated in order to find possible prevention methodologies, especially in highperformance digital/analog ICs which may include several operational amplifiers (OpAmps) [4].
1. Introduction EMI effects may involve virtually any electrical or electronic equipment along with interconnects. As an example, aircrafts are especially susceptible to electronic interferences because of their increasing reliance on radio communication and navigation systems whose electromagnetic spectrum ranges from 10kHz (navigation systems) up to 9GHz and above (weather radar). Furthermore, the massive introduction of electronics in automotive can cause a number of problems: engines may stall because of the interference induced by traffic lights while cellular telephone transmitters can induce disturbs in braking systems (ABS ). Sources of EMI arise inside the automobile as well. The internal sources, in fact, include alternator, ignition system, switching solenoids, electric starter, lamps, etc … In addition, EMI are relevant on long signal lines and in power supply rails where battery can be far from the powered circuitry, as shown in Figure 1. Nowadays, the high density of components packed on printed circuit boards as well as the high speed of mixed analog digital circuits force the designers to consider EMI during the design phase. Neglecting these aspects may lead to failures on integrated circuits induced by spurious signals arising from a large class of signals,
Figure 1: EMI conveyed to power supply rails It‘s worth mentioning that the most sensitive circuits to EMI are those who perform analog operations and, among them, the OpAmps [3]. In order to investigate the EMI effects on a generic amplifier the interfering signal can be modelled as a sinusoidal waveform generated by a zero DC value voltage source superimposed to all the pins connected to long wires. This assumption represents a worst case condition, for the interfering signal because it often decays in time [3]. Among all the possible interfering signals, the ones superimposed to the input signal, often very weak, is the most difficult to control and cut-off with external filters.
a strong symmetry in the signal paths. Frequency compensation is obtained by means of two RC lines across the output buffer as shown in the figure.
Vdc t Vdc
OpAmp Vout A
Vin + Vin -
Folded Cascode
Vout B
Vout B
CL
Vout A
Buffer
t
CL
Vdc
Figure 3. Amplifier architecture
t
Figure 2. Amplifier architecture The most undesirable effect of interferences on the input pins is a shift of the output DC mean value (offset) that can asymptotically force the amplifier to either positive or negative saturation. Recently, a lot of work has been devoted to investigate the most important cause of such an anomalous behaviour. The EMI susceptibility characteristics has been correlated to some special features of the OpAmp transient responses. In particular, it has been shown that both the asymmetric slew rate and the parasitic capacitances [5] play a significant role. Hence, in order to reduce EMI effects it is important to choose strongly symmetrical circuital schemes. In what follows, an highly symmetrical CMOS amplifier will be designed: its architecture allows to reduce EMI effects by more than one order of magnitude compared to commercial amplifiers. In section 2 the circuit topology will be described, in section 3 results of measurements will be discussed and compared to the well known commercial OpAmp uA741, in section 4 some conclusions will be drawn.
2.
The circuital scheme of the folded cascode input stage is reported in Fig. 4. Its main features are: large gain due to the folded cascode structure, good rejection of common mode signals even in the presence of stray elements and nonidealities (because of the high symmetry of the circuit), and large output voltage swing. Furthermore, common mode feedback is accomplished by applying a return signal from the output terminals to the gates of the transistors M7a and M7b. This is important, since in the fully differential OpAmp the common mode output voltage should be internally forced to a reference potential. The common mode feedback operates the following way. Since the gate voltages of M6a and M6b are fixed at the biasing voltage Vp4 and their currents are Vdd
M7a
M6a
M6b Vp4
Amplifier architecture
As shown in the upper half of Fig. 2, since the effect of EMI conveyed to the input pin results in an output DC offset due to the input differential stage and the signal propagation in the feedback line a possible improvement in the susceptibility problem is the generation of a second output which is not directly connected to the input pins (see bottom of Fig. 2). Being the two outputs correlated in the “in band operation”, but indipendent in the high frequency interfering signal path, the output in the feedback line may still suffer from the increasing DC offset, but the secondary output will be much less susceptible and its DC value may be used as the prime output of the OpAmp. The overall amplifier architecture is reported in Fig. 3. It is composed of two main blocks: the first stage consists of a folded cascode to achieve large gain, the second stage is a source cross-coupled AB class buffer to ensure
M7b
M5a Vout A
M1a M1b
Vin+
Vin-
M5b Vp3
M4a
Vout B
M4b Vp2
Vp1
M2
M3a
Vp1
M3b
Figure 4: Folded cascode amplifier
set, their source voltages are also stabilized. This fixes the drain to source voltages of M7a and M7b. The value of Vp4 is chosen such that M7a and M7b operate in their linear regions. Their aspect ratios are
chosen such that, in equilibrium, the common mode output voltage has some desired value. If now the common mode voltage would rise, the resistance of M7a and M7b increases. This reduces the gate to source voltages of M6a and M6b and, since the current in M6a and M6b remains unchanged, it forces drain to source voltages of M6a and M6b to increase. Thus the drain voltages of M6a and M6b drop. This reduces the gate to source voltages of M5a and M5b and thus drops their drain voltages which are VoutA and VoutB . The common mode voltage is thus reduced. This feedback loop also stabilizes the common mode voltage against transistor parameter variations arising from fabrication imperfections. The second stage of the OpAmp is reported in Fig. 5. It is a source cross coupled class AB buffer with active loads; this configuration is very useful when the output slew rate of the OpAmp is an important task. Such a scheme leads to a strong symmetry of the output voltage thanks to the mirrored path of the signals. The first stage
With regard to this, it is important to point out that the slew rate of VoutA − VoutB is symmetrical because the first stage of the OpAmp is fully differential, while the slew rate of both output voltage VoutA and VoutB are singularly symmetrical thanks to the cross architecture of the second stage (buffer).
3.
Measurements results
In order to investigate the EMI immunity level the OpAmp has been measured in the voltage follower configuration shown in Fig.3 It is quite easy to understand why the voltage follower topology represents the worst case: in this configuration, due to direct connection between the output and the inverting input node, the gates of the differential pairs experience the largest voltage difference [3]. Furthermore to predict effects of EMI, the interfering signals have been modelled by a sinusoidal waveform generated by a voltage source: the amplitude of the
Vdd
M14a
M12a
M12b
M14b
Vp5
Vp5 M16a
Vout A
M16b
M11a
Vout B
M11b
M9a
M9b Vout A
Vout B M8b
M8a M10a
M10b
M18a M17a
M15a
M17b M18b
M13a
M13b
M15b
Figure 5: Class AB buffer output voltage VoutA and VoutB are now applied to both the gates of M9a and M9b, in order to bias the NMOS differential pair, and to the gate of M8a and M8b to bias the PMOS differential pair. Hence, the output voltages of the first stage VoutA and VoutB are symmetrically applied to the gates of the two differential pairs M10 and M11 and any voltage mismatch originated in the first stage is vanished by this cross connection. This leads to a very symmetrical path for both signals across the amplifier.
interfering signal has been assumed to be 1Vpp, with 0 DC mean value, and a frequency ranging from 10MHz up to 4GHz. The choice of the frequency range has been taken to include the whole spectrum of the possible interfering signals up to the cellular phone band. As reported above, one quantity that easily and accurately quantify the EMI effect is the mean output voltage of VoutA and VoutB (offset). The experimental results are reported in Fig. 6, where, the offset voltage of VoutA and VoutB of the designed
OpAmp is compared with the ouput of a commercial single ended amplifier uA741. This OpAmp, used as a reference, is the only one reported here as an example, however, many others may be found in [3]. The offset of our OpAmp is more than one order of magnitude smaller than the one of the uA741 which, in turn, appears to be quite susceptible to EMI. In particular, the output voltage VoutB that represent the most symmetrical signal path between input and output, is quite immune to the EMI interference according to the idea introduced in Fig. 2. As shown in the figure, at frequencies slightly higher than the operating bandwidth of the amplifier (i.e., ~10MHz) the offset of the OpAmp is very low on both output pins. On the contrary, at the same frequency, the uA741 exhibits a larger offset, of about 700mV, that could easily drive the circuit connected to its output to saturation with catastrophic behaviour of the whole system the OpAmp is used in. Furthermore, at higher frequencies, around 600 MHz, the offset on the output voltage VoutA of our OpAmp peaks at around 150 mV while the offset of VoutB is pinned at around 27 mV; on the other hand the uA741 still exhibit an offset of about 600mV. At even larger frequencies the parasitic effects of the measurements set-up (board, cable …) acts like a low pass filter and the offset of both amplifier rapidly decay to a offset voltage of few tens of millivolts.
4.
Bibliography 1. 2.
3.
4.
5.
C.R. Paul, Introduction to Electromagnetic Compatibility, John Wiley & Sons, 1992. A.S. Poulton, “Effect of conducted EMI on the DC performances of operational amplifiers”, Electronics Letters, Vol. 30, pp. 282-284, 1994. G. Masetti, S. Graffi, D. Golzio, Zs.M. Kovács-V., Failures Induced on Analog Integrated Circuits from Conveyed Electromagnetic Interferences: a Review, Microelectronics and Reliability, Vol. 36, No. 7/8, pp. 955-972, 1996 G. Setti N. Speciale, “Design of a Low EMI Susceptibility CMOS Operational Amplifier”, Microelectronics Reliability, Vol. 38, pp. 1143, 1998. G. Masetti G. Setti N. Speciale, “On the key Role of parasitic Capacitances in the Determination of Susceptibility to EMI of Integrated Operational Amplifiers”, Proc. EMC99 Zürich, 1999.
Conclusions
In this paper, an highly symmetrical integrated CMOS operational amplifier with enhanced immunity to electromagnetic interference (EMI) was presented. It is based on a two stage topology that allows to obtain a strong symmetry of each signal path, this is particularly attractive in order to minimize electromagnetic interferences. As stated before our amplifier is based on two main stages: the first is a fully differential folded cascode and the second is a source cross-coupled AB class buffer. The circuit was fabricated in a 0.8 µm n-well AMS CMOS CYE technology thanks to the Europractice prototyping service. Its main features are: a gain of 93 dB, the GBW of 10.4 MHz and a symmetric positive – negative slew rate. The supply voltage can range from 3.3 to 5V. Our measurements on the chip show a low susceptibility to electromagnetic interferences conveyed especially at the non buffered output pin. It suggests that it could be used as a preferential output for EMI critical applications. The overall performance of the OpAmp in terms EMI immunity were compared to a commercial amplifier uA741 showing a EMI susceptibility reduced by more than one order of magnitude.
Figure 6. Measurements results
