Design of Inductor

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FPGA Programming File in NI c-RIO 9082: For Duty Ratio: D=0.4 and 100 KHz frequency. Module Used: Digital Input Output : NI 9401.
A Design of Inductor 

Design of Input Inductance( L ): i Switching frequency f s is 100kHZ.,

Vi =28V,P=250W., Ii,rms =8.85A Assume B=2500G For PQ type core i.e PQ-3230 A c =1.61 cm2 , W A =1.6 cm4 (From Datasheet of the PQ type ferrite core.) a c k=Core Factor=2440 lm =7.47m, lg =0.5mm Crossectional area of the conductor including insulation= 1.589mm2 Nearest SWG wire is SWG-17 μμA Permeance value= Λ= 0 r c lm +μ r lg

μ 0 =4π×10-7 , μ r =2000±25%

Li =17Turns Λ Actual Number of turns of the conductor=aN  18 Turns Number turns of Conductor= N=



Design of Input Inductance( L ): s Switching frequency f s is 100 KHz.

Vi =28V,P=250W., Ii,rms =1.5A Assume B=2500G For EE-type core i.e EE-16A a= A c =18.4 mm 2 , (From Datasheet of the EE-16 type ferrite core.) k=Core Factor=2440 l e =35.5mm, lg =0.5mm Current Density=J= 3 106 Cross-sectional area of the conductor including insulation= 1.589mm2 Nearest SWG wire is SWG-17 μμA Permeance value= Λ= 0 r c lm +μ r lg

μ 0 =4π×10-7 , μ r =2000±25%

Ls =5Turns Λ Actual Number of turns of the conductor=aN  6 Turns Number turns of Conductor= N=

B Design of Transformer Design of High Frequency Transformer: Given Input Voltage, Vi =28V,R=577  ,Output Voltage, V0 =380V Switching Frequency= f s =100KHZ Let's consider Magnetizing ripple current is 20% of the Dc magnetizing current. Duty Ratio=D=0.62 n Turn Ratio= 2 =5, Bmax =0.25T n1 k u =Utilization Factor=0.3 V n2 × 0 =10.42A , Im = n1 (1-D) R ΔIm =20%ofIm =0.2×10.42=2.084A so Im,max =Im  Im =12.504A

Lm =

Vi DTs =41.65µH 2ΔI m

I1 =I m D (1+(

ΔI m 2 1 ) × =8.259A Im 3

n1 ×I1 =1.2931A n2 n I tot =I1 + 2 I 2 =14.725A n1 I2 =

n1 =

Lm I m,max ×104 Bmax ×A c

For PQ type i.e PQ-3230 Ferrite core A c =1.61 mm2 , WA =0.99379 so, n1 =12.93≅13 turns similarly n 2 =13×5=65 turns Wire Gauge Factor for primary side and secondary side of the Transformer is I α1= 1 =0.562 I tot n I α2= 2 × 2 =0.439 n1 I tot α1k u w A Window Area of primary side= A w1  =1.2865 mm2 n1 so, size of SWG wire for primary side become SWG-18(According to datasheet) α2k u w A Window Area of secondary side = A w2 = n2 so, size of SWG wire for secondary side become SWG-25(According to datasheet).

C FPGA Programming File in NI c-RIO 9082: For Duty Ratio: D=0.4 and 100 KHz frequency.

Module Used: Digital Input Output : NI 9401