Design of Inverting Buck-Boost DC-DC Converter with ...

Design of Inverting Buck-Boost DC-DC Converter with Input-to-Output By-Pass Capacitor N. Femia, G. Di Capua, A. De Nardo Dipartimento di Ingegneria Elettronica ed Ingegneria Informatica (DIEII) Università degli Studi di Salerno Fisciano (SA), Italy e-mail: {femia,gdicapua,adenardo}@unisa.it Abstract- This paper discusses the design of Inverting Buck Boost (IBB) DC-DC converter including a by-pass Input-toOutput Capacitor (IOC). Based on the analysis of circulating currents, the guidelines for the selection of the IOC are provided. It is shown that an adequate selection of the IOC can help in reducing the size of input and output capacitors and the ground current, thus improving PCB layout noise management. Some examples regarding low voltage IBB applications are presented to illustrate the design approach proposed in the paper.

and the magnitude of the ground rms ac current by means of a proper choice of an additional by-pass Input-to-Output Capacitor (IOC), connected as shown in Fig.2.

INTRODUCTION The Inverting Buck-Boost (IBB) is one of the basic DC-DC converter topologies used to realize power supplies providing negative polarity voltages. These are required to feed OPAMPs and other electronic devices and equipments needing dual voltages. IBB is much attractive also for applications where having an inverted output voltage is not influent, like in LED drivers providing constant current regulation. The IBB topology can be implemented in several configurations [1]. Fig.1 shows one of them.

Fig.1 Basic IBB circuit schematic

Several issues arise in IBB design: i) the voltage stress on solid state devices is higher than for other basic topologies (like buck and boost); ii) both input and output capacitors have to filter high frequency ripple currents; iii) high-amplitude high-frequency current circulates through the ground (the total FET current); iv) a right-half plane zero appears in the control-to-output ac transfer function; v) different switcher ICs are required to control the FET depending on the selected ground configuration [2]. In this paper we focus the attention on issues ii) and iii). In particular, the goal of this paper is to provide design guidelines to reduce the size of input and output capacitors

Fig. 2. IBB-IOC circuit schematic.

The IOC offers additional by-pass path for FET and diode pulsating currents. This can help in achieving the design of the IBB by using only ceramic capacitors. Indeed, due to the pulsating nature of currents, the input and output filtering is often realized by using an electrolytic and a ceramic capacitor in parallel: the former provides the capacitance to limit the voltage rise/fall during switching intervals while the latter ensures high rms current capability and low ESR needed to limit the stepwise rise of voltage across switching instants. The selection of these two capacitors is mostly based on heuristics: put a small ceramic cap in parallel to a big electrolytic one. How much small, how much big? There are models and design techniques allowing to solve in rational way this problem, as shown in [3]. However, it is sometimes preferable to avoid paralleling the electrolytic and ceramic caps, as for cost as for PCB layout as for dynamics and control issues. Indeed, a single additional by-pass ceramic IOC may allow using either single electrolytic or single ceramic capacitors for input and output. As the IOC loops with input and output capacitors through the ground, the whole map of circulating currents through the three capacitors is required to correctly design each capacitor, exploiting at the best the opportunity of minimizing all capacitances. The following sections of this paper will show how to simplify the analysis of the circulating currents and how to figure out a design method to identify the most convenient set of commercial capacitors allowing to achieve the desired limitation of input and output ripple voltages. A design example is discussed regarding a low voltage IBB application.

I

CIRCULATING CURRENTS IN IBB-IOC

The analysis of circulating currents in IBB-IOC for the design of the three capacitors can be done by separating the dc components from the ac components. Simplified equivalent circuit for the analysis of switching currents of IBB-IOC is shown in Fig.3(a). The source is assumed to have high impedance compared to input capacitor impedance; it is also assumed to feed a dc current (small ripple). The ESR of capacitors is assumed to be small compared to the capacitive impedance at switching frequency. This hypothesis is well met by high-current ceramic capacitors. Ground path is assumed to have negligible impedance. The load current Io is assumed to have a negligible ripple. The FET and the diode are replaced by two current sources. The sum of these currents provides the inductor current: the inductor is not represented as it is not necessary in mere current analysis.

To simplify the analysis, let us assume that:

Ci = a ⋅ C ,

Cio = b ⋅ C ,

Co = C

The coefficients a and b are not totally independent. In fact, they are related each other by the constraints imposed to the maximum input and output ripple voltage magnitude. In the IBB the relationship between the input and output is given by:

Vo = −

D Vi D'

(2)

where D is FET duty-cycle and D’=(1-D) in Continuous Conduction Mode (CCM) operating conditions. The maximum ripple voltage limits are usually fixed as a percentage of the corresponding DC voltage, as for the input as for the output. For the IBB topology, the following assumptions can be made:

Δvipp = θiVi = θ i Vo Δ vopp = θ o Vo

D' D

⎛ D' ⎞ Δviopp = Δvipp + Δvopp = ⎜ θi + θo ⎟ ⋅ Vo ⎝ D ⎠

(a)

(1)

(3) (4) (5)

where θi and θo are pure numbers smaller than unity (normally θi ≈ 0.05÷0.10 and θo ≈ 0.01÷0.02). From (3) and (4), we get:

Δvipp Δvopp

(b)  iQ

2

 iQ1

 iQ

 iD  iD2

 i D1

Fig.3. IBB equivalent circuit for circulating currents analysis: (a) total currents, (b) DC current components, (c) ripple current components: dotted lines= map of FET current distribution, dashed lines=map of diode current distribution.

Figs.3(b)(c) show the path of dc and ripple components (symbols with hats) of circulating currents. Fig.3(c) also shows how the FET and the diode currents are partitioned by the three capacitors: - the component iQ1 flows through the Co-Cio series; - the component iQ2 flows through Ci; - the component iD1 flows through Co; - the component iD2 flows through the Ci-Cio series.

θi D ' θo D

(6)

As the ratio between the input and output maximum voltage ripple is inversely proportional to the ratio between the capacitances of input and output capacitors, from (1) and (6) we get:

a= (c)

=

θo D θi D '

(7)

Consequently, from (4) and (5), we get:

Δviopp Δvopp

= 1+

θi D ' 1 = 1+ θo D a

(8)

Finally, as the ratio between the input-output and output maximum voltage ripple is inversely proportional to the ratio between the capacitances of the input-output and output capacitors, from (1) and (8) we get: b=

θo D a = 1 + a θi D '+ θo D

(9)

Choosing the input, output and input-output capacitors based on the coefficients a and b is coherent with the correlation existing among voltage ripples determined by voltage balance in the loop of the three capacitors. However, there are some additional facts to take into account: - there are in theory infinite triplets of theoretical capacitances Ci, Co and Cio complying with (1)(7) and (9); - commercial values of capacitances are quantized, so that it is not possible to guarantee exactly the theoretical ratios a and b for all the combinations of input and output voltage and related ripple limits; - the goal of using Cio is to reduce the size of Ci, Co and then a certain amount of oversize of Cio is plausible. As a consequence of the previous considerations, a correction factor cf is introduced, such that:

 ix = k ⋅ i S + μ ⋅ iL

(18)

where:

ix = ⎡⎣iCi

iCio

k = ⎡⎣ k Q

T

(19)

T

i S = ⎡i Q ⎣⎢ μ = [0

ignd ⎤⎦

iCo

i D ⎤ = ⎡ i − Di L ⎣Q ⎦⎥ 0

0

iD − D ' iL ⎤⎦

D]

T

k D ⎤⎦

(22) T

k Q = ⎡⎣ kiQ

kioQ k oQ

k gndQ ⎤⎦

k D = ⎡⎣ kiD

kioD k oD

k gndD ⎤⎦

T

kiD = −ξ ⋅ a ⋅ b '

kioQ = −ξ ⋅ b ',

kioD = ξ ⋅ a ⋅ b '

koQ = ξ ⋅ b ', Accordingly to the previous assumptions, the analysis of ripple circulating currents yields the following results:

koD = ξ ⋅ ( a + b ')

k gndQ = − kiQ ,

k gndD = − kiD

⎧ i Q 1 = ξ ⋅ b ' i Q  ⎪ iQ : ⎨   ⎪⎩ i Q 2 = ξ ⋅ a ⋅ ( b ' + 1 ) i Q

According to (18)-(25) we get:

⎧ i D 1 = ξ ⋅ ( a + b ' ) i D  ⎪ iD : ⎨ ⎪⎩ i D 2 = ξ ⋅ a ⋅ b '⋅ i D

(10)

(11)

(12)

where:

ξ = ( a + b '+ ab ')

−1

(13)

The ripple circulating currents flowing through the capacitors and the ground can be easily obtained from Fig.3(c):

   i Ci = −i Q 2 − i D 2 i Cio = −i Q1 + i D 2    i Co = i Q1 + i D1

(14) (15) (16)

ignd

D    = iQ 2 + i D 2 + D ⋅ iL = i gnd − I o D'

 i Ci = M iQ iQ + M iD iD  i Cio = M ioQiQ + M ioD iD i Co = M i + M i oQ Q oD D  i gnd = M gndQ iQ + M gndDiD

(17)

The circulating currents (14)-(17) can be determined by using the compact matrix model (18):

(23) (24)

(25)

(26) (27) (28) (29)

where:

M iQ = ξ ⋅ a ⋅ ( D -1) , M ioQ = ξ ⋅ b '⋅ (1 + a ) ⋅ ( D − 1), M oQ = ξ ⋅ a ⋅ ( D -1) ,

(30)

M gndQ = D − ξ ⋅ a ⋅ ( D -1) M iD = ξ ⋅ a ⋅ D M ioD = ξ ⋅ b '⋅ (1 + a ) ⋅ D M oD = ξ ⋅ a ⋅ D

Equation (17) provides the total ground current:

(20)

(21)

kiQ = −ξ ⋅ a ⋅ ( b '+ 1) ,

Cio = b ⋅ c f ⋅ C = b '⋅ C

T

(31)

M gndD = D − ξ ⋅ a ⋅ D In compact form:

⎡iQ ⎤ ⎡iQ ⎤ ix = M ⎢ ⎥ = ⎡⎣ μ + k QD D ' ; μ − k QD D ⎤⎦ ⎢ ⎥ ⎣iD ⎦ ⎣iD ⎦

(32)

where:

k QD = k Q − k D

(33)

The coefficients Mxy are functions of D and cf. By substitution, the following functions for ripple currents into IBB-IOC capacitors and ground can be obtained:

 i Ci = −γ D ' iQ + γ DiD  i Cio = −γ D '⋅ c f iQ + γ D ⋅ c f iD i Co = −γ D ' i + γ Di Q D  i gnd = γ (1 + D ⋅ c f ) iQ + γ D ⋅ c f iD

(34) (35) (36) (37)

both in the input and in the output capacitor as well as in the ground, while the IOC takes only one half of the total initial current of each capacitor. In this situation, a great benefit is obtained especially for output capacitor which is subjected, in general, to the most restrictive ripple voltage limit. Rising cf above 1 boosts such benefit. In particular, values of cf around 5 reduce input, output and ground rms currents to 20% of their initial values. Swapping the ripple currents of input and output capacitors into the IOC is highly beneficial as the current is reduced and injected into a capacitor subjected to a bigger ripple voltage. Going far beyond cf=5 just causes increasing the size of IOC without getting valuable benefits. The plots of Fig.4 show that the worst case for ripple currents is at minimum input voltage. In next section this condition will be considered for verifications. DESIGN OF IBB-IOC CAPACITORS

II

where γ = (1 + c f )

−1

(38)

It is important to notice that (34)-(37) have been obtained assuming that ground impedance is negligible, source impedance is big compared to input capacitor impedance and that ESR of capacitors is negligible compared to reactance. Accordingly, simplified rms values of ripple currents are:

iCi,rms = iϕ ,rms iCio ,rms = c f ⋅ iϕ ,rms iCo,rms = iϕ ,rms ignd ,rms = iϕ ,rms

(39)

iϕ ,rms = γ I o D D '

(43)

The analysis of circulating currents and of their dependence on the correcting factor cf illustrated in the previous section allows to formulate the design equations for the three capacitors of IBB-IOC. Fig.4 shows typical waveforms of currents into the three capacitors of the IBB-IOC.

ΔiCio

ΔiCo

ΔiCi

(40) (41) (42)

The plots of rms currents (39)-(42) vs cf are shown in Fig.4 for a design subjected to the following specifications: Vi =[10,14]V, Vo=-12V, Io=1A, θi=0.1, θo=0.02.

Fig.5. Currents of IBB-IOC capacitors

According to the model developed in previous section, the magnitude of the current steps across the switching instant DTs are given by:

ΔiCi = ( M iD − M iQ ) I pk = M iDQ I pk = γ I pk

ΔiCio = ( M ioD − M ioQ ) I pk = M ioDQ I pk = γ c f I pk ΔiCo = ( M oD − M oQ ) I pk = M oDQ I pk = γ I pk where:

I pk = I L + Fig.4. Normalized rms currents of capacitors vs cf factor.

For cf=0 the plots provide the rms currents without IOC. For cf=1 the rms currents corresponding to the basic voltage ripple compliance are given. The rms current is almost halved

ΔiLpp 2

=

Io Vi D + D ' 2 fs L

(44) (45) (46)

(47)

Ripple voltage constraint across each capacitors is given by:

Δ v xpp < Δv xpp ,max

(48)

where x=i,o,io. Assuming that the currents of capacitors are shaped as shown in Fig.4, the following expressions for peakto-peak voltage ripple are obtained:

Δvxpp = M xDQ ESRo I pk + M xD

Io < Δvxpp ,max Co f s

(49)

So that, constraint on ESRx given the capacitance Cx for ripple limit of capacitor x is met is given by (50):

ESRx