Design Techniques and Considerations for mmWave ...

Design Techniques and Considerations for mmWave SiGe Power Amplifiers Nejdat Demirel, Eric Kerhervé

Denis Pache

Robert Plana

IMS Laboratory, COFI Department Microwave Team 33405 Talence Cedex, France [email protected]

STMicroelectronics R&D Crolles, France [email protected]

LAAS-CNRS, University of Toulouse, France [email protected]

Abstract— This paper describes the techniques to design a SiGe power amplifier (PA) for millimeter wave (mmW) applications. The design methodology of a balanced four-stage common emitter circuit topology was reported. The power amplifier was fully integrated including matching elements and bias circuit. The matching networks use coplanar waveguide (CPW) lines and MIM capacitors. Design considerations including parasitic elements, interconnections, pad model and matching structures are detailed. All these elements are taken into account to optimize the maximum output power. A comparison of the simulated and measured small-signal results is presented up to 110GHz. The simulated and measured large-signal parameters are shown at 60, 65 and 77GHz. Power Amplifier; millimeter wave applications; HBT SiGe; design considerations

I.

INTRODUCTION

The new mmW applications for wireless systems need compact and low-cost transmitters with high performances. Three important applications are observed for upcoming markets: point-to-point broadband radio links at 60 GHz [1], intelligent adaptive cruise control (ACC) systems for automotive applications at 77 GHz [2] and others applications above 100 GHz for short range communication or imaging [3]. In order to maintain a very low cost solution and a strong demand of miniaturization, it is foreseen to develop systems fully integrated on a silicon substrate through a System On Chip (SOC) approach integrating a receiver part and a transmitter part. In order to accurately characterize the performance of the developed mmwave power amplifier, reliable techniques have been taken into account. For successful implementation of this circuit, an extensive study of various factors determining the performance of integrated interconnect structures, parasitic elements, matching structures, lumped and distributed passives at frequencies up to 100 GHz was required. An important consideration in designing power amplifiers is to accurately determine the parasitic elements, which affect all simulations, because these elements are a part of both the complete input and output matching circuits. These elements become an important part of the overall circuit. Considerations were already done in CMOS [4] and SiGe [5] where the difficulties to obtain good correlation between simulations and measurements for high output power were shown.

978-1-4244-5357-3/09/$26.00©2009IEEE

Figure 1.

Photography of the differential wideband power amplifier (total chip size: 1.06*1.06 mm²).

This paper describes a four-stage SiGe power amplifier (PA) which features 8% Power Added Efficiency (PAE), with 19dB gain and 17.5dBm of maximum output power at 65GHz, making it suitable for mmW WLAN (Wireless Local Area Network) applications. The methodology used for designing the PA is described in Section II. Amplifier characterization and high frequency design techniques are also discussed. Simulation and experimental results of the PA are described in Section III. II.

DESIGN METHODOLOGY AND CONSIDERATIONS

The balanced PA was designed to operate from a 1.8V supply in a 0.13um SiGe BiCMOS technology with cutoff frequencies fT/fmax= 230/280 GHz [6]. Figure 1 shows the mmW PA photography. The chip, including pads, consumes an area of 1.12mm². On-chip DC decoupling capacitors (15pF) are included for supply voltage in each stage of the differential amplifier. The process has six metal layers with four copper bottom layers, two thick layers, and an aluminum layer as top metal. The SiGe HBT breakdown voltages are BVCEO=1.6V and BVCBO=5.5V. The half-schematic of the amplifier is shown in Figure 2. In order to obtain a high gain, the PA consists of four common-emitter stages. The first three stages are optimized to achieve maximum gain. The output stage is

37

Figure 2. Half-schematic of the wideband balanced PA including real element values.

optimized to achieve the maximum output power. The output transistors have been also driven near to their practical limits, related to high-current effects and avalanche breakdown. The use of class-AB operation for the output stage provides a good trade-off between linearity and efficiency. A current mirror biasing circuit has been used on each stage of the balanced PA to provide an optimum condition for the power device as function of temperature and output power.

under the RF signal pad there isn’t metal. The loss in the substrate is about 0.35dB on the RF input and output pads.

A. Stability analysis The common-emitter topology was preferred for his simplicity and for stability problem reasons with respect to other topologies. The risk of oscillations is high when using several stages. A stability study is made separately on each stage. For the millimeter-wave applications, the transistor has a very high gain at low frequency which may cause low frequency oscillations. The solution adopted to make the amplifier unconditionally stable is to add a resistor in parallel with a capacitor to introduce losses at the low frequencies. B. Parasitic elements As preparation for optimizing the output circuit for maximum RF power generation, it is necessary to determine the device’s parasitic elements. These elements must be determined because they are a part of the total output matching network. The equivalent circuit of the bipolar transistor device is composed of a set of parasitic elements. The equivalent circuit is shown in this Figure 3. Parasitic capacitance and resistance have been extracted and added to the design. This is a critical consideration in the output matching circuit because this circuit matches to the device’s load resistance which contains the parasitic elements. The load line resistance which is the impedance that the output matching network must present to the device is transformed by these parasitic elements. The values of the parasitic elements are summarized in Table I. C. RF Pads The impedances measurements of the RF pad are shown in Figure 4. The input and output pads have been optimized to reduce its capacitance value. The RF pads represent a capacity of approximately 13fF. However, the quality factor (Q=7.6 at 80GHz) of this pad is low in the millimeter wave frequencies. The ground pads are connected from alucap to the substrate but

Figure 3. Parasitic extraction of the transistor accesses.

TABLE II.

TRANSISTOR PARASITIC CAPACITANCE AND RESISTANCE

Rc ( )

T1 CBEBC 8µm 0.275

T2 CBEBC 15µm 0.245

T3,T4 and T5 CBEBCBEBC 15µm 0.18

Re ( )

0.47

0.25

0.14

TR

Rb ( )

0.82

0.845

0.5

Ces (fF)

0.55

0.8

0.6

Ccs (fF)

2

2.5

3.2

Cce (fF)

4.5

6.4

10.8

Cbs (fF)

0.7

0.8

0.95

Cbc (fF)

3.6

5.7

11.35

Cbe (fF)

4.5

6.5

12.25

D. Transmissions lines The design kit includes a model of CPW line up to 110GHz. The CPW transmission line has 70 to 50 characteristic impedance range from 6µm to 12µm widths. These impedances are used in the design to reduce the coupling

2009 SBMO/IEEE MTT-S International Microwave & Optoelectronics Conference (IMOC 2009)

38

to nearby lines and to minimize the coupling to the lossy 15 cm substrate. The attenuation and the propagation phase of a 50 transmission line ( eff=4.2, loss=0.5dB/mm) is plotted on Figure 5. The measurement results with a TRL (Through Reflect Line) de-embedding are compared with EM simulations (Momentum and HFSS) and with a model based on lumped elements.

of these structures are compared with the simulation to evaluate and verify the accuracy modeling between the connections of lumped and distributed elements. The input matching was realized by using series transmission lines, MIM capacitors, and shorted parallel stub. For the output matching, a high capacitor was added to the end of one of the parallel stub which corresponds to a decoupling capacitor used in the power amplifier. Measurements results of the input and output matching networks obtained by a de-embedding open-short reveal a good match with the simulation results from 1GHz to 110GHz.

Figure 4. Imaginary admittance (im(Y)/ ) and real impedance (re(Z)) measurements of the RF pad.

Figure 6. Input matching network: match 50 to the input impedance of the power amplifier.

Figure 5.

Attenuation (alpha) and propagation phase (beta) of the CPW transmission line (w=12µm and l=1mm).

E. Matching circuits Matching circuits transform the source and load impedances to the proper impedance to match the base and collector of the bipolar transistor for high gain and maximum RF power output. Matching circuits contain reactive elements, and therefore are frequency selective. Matching circuits also determine an amplifier’s central frequency and bandwidth. Distributed matching circuits are the most useful at higher frequencies because their element lengths are scaled with frequency, which means that similar circuits become progressively smaller at higher frequencies. The matching networks use MIM capacitors and coplanar transmission lines (~100-200µm). The use of transmission lines is preferred to obtain better accuracy of the passive elements. However, between transmission lines and the other components, interconnections (ico) lines (~5-15µm) have been added for a better description of the circuit. Input and output matching test structures are shown in Figure 6 and Figure 7 respectively. The measurements results

Figure 7. Output matching network: match 50 to the output impedance of the power amplifier

III.

SIMULATION AND MEASUREMENT COMPARISON

All the measurements presented in this paper have been done on 50 single-ended impedance. The measurements were performed on wafer using ground-signal-ground probes (GSG) with 100µm of pitch. The measurements of the balanced PA need baluns which weren’t available. The differential results was found adding 3dB (Pin and Pout) to single-ended measurements.


39

Figure 8. Measured and simulated small-signal S-parameter of the four-stage power amplifier.

A. Small Signal Results A comparison of the measured and simulated S-parameters is plotted in Figure 8. The small-signal results correspond well due to the careful design considerations. The single-ended PA consumes a total quiescent current of 145 mA for a DC supply of 1.8V. The measured small-signal gain is 19dB at 65GHz, and the 3dB bandwidth is 59 to 71GHz. The S11 and S22 are below -10 dB from 58 to 81 GHz and from 60 to 70 GHz, respectively. The output-to-input isolation is better than 40dB over the bandwidth.

S21 parameter with ideal and accurate model is compared in Figure 10. These simulations show accurate model is needed same for the small connections.

Figure 10. Comparison of the simulated S21 parameter of the power amplifier with ideal and accurate model of the decoupling capacitor. Figure 9. Physical structure and schematic of the decoupling MIM capacitor.

The low gain (S21) between 40GHz to 60GHz is principally due to the connection on the decoupling capacitors. The current goes from the top metal to the bottom metal of the MIM capacitor, and ideally the bottom metal is connected to the ground. But with an accurate model (Figure 9), under the CMIM capacitor (15pF) there is another high capacitor Cp (2.56pF) between the BOTMIM metal and the metal6. The connection from the BOTMIM to the metal6 represents an inductive and resistive element (Lp=4pH and Rp=0.3m ). Lp and Cp give a resonance frequency at 49GHz. The simulated

B. Large Signal Results Measured output power, gain and PAE as function of input power at 60GHz are plotted in Figure 11. The measurements were made and presented in a single ended configuration. The single-ended large-signal measurements show that the circuit achieves a maximum output power of 15 dBm at 60GHz. A maximum of PAE of 8.6% is obtained at 60GHz. This value is better than the simulation where the DC current is lower for the high input power in measurements. The output 1dB gain compression point (OCP1) is 10 dBm at 60GHz with 17.3dB


40

TABLE II.

SUMMARY OF SIMULATED AND MEASURED PA PERFORMANCES

Frequency

60GHz

65GHz

77GHz

Units

measured

simulated

measured

simulated

measured

simulated

DC POWER REQUIREMENTS Voltage Supply, Vcc Single-ended Quiescent current, Idc

1.8 146.7

1.8 146.8

1.8 144.8

1.8 146.8

1.8 150

1.8 146.8

V mA

DIFFERENTIAL LARGE SIGNAL Power gain, GP Output compression point, OCP1

17.3 13

18.2 14

19 13.5

18.2 14

13.5 6.2

12.8 10.5

dB dBm

Saturated output power, Psat

18

18

17.5

18.1

13

16

dBm

Maximum Power Added Efficiency, PAEmax

8.6

5.3

7.5

5.1

2.2

2.8

%

Power Added Efficiency at CP1, PAE(@CP1)

4

3.8

4

3.8

0.7

1.6

%

SINGLE-ENDED LARGE SIGNAL Power gain, GP Output compression point, OCP1

17.3 10

18.2 11

19 10.5

18.2 11

13.5 3.2

12.8 7.5

dB dBm

Saturated output power, Psat

15

15

14.5

15.1

10

13

dBm

Maximum Power Added Efficiency, PAEmax

8.6

5.3

7.5

5.1

2.2

2.8

%

Power Added Efficiency at CP1, PAE(@CP1)

4

3.8

4

3.8

0.7

1.6

%

of power gain. Summary of the PA single-ended large-signal results are compared at 60, 65 and 77GHz in Table II. The differential large-signal is also presented for the balanced configuration including 3dB for OCP1 and Psat.

ACKNOWLEDGMENT The authors acknowledge technical support for testing provided by Magali De Matos and Victor Dupuy. Fabrication and technology support was provided by Sébastien Pruvost from STMicroelectronics. The authors extend special thanks to Valerie Danelon and Laurence Moquillon for helpful discussions. The authors thank Conseil Régional d'Aquitaine for the support on the NANOCOM millimeter-wave test bench. REFERENCES [1]

[2]

Figure 11. Measured (solid) and simulated (dashed) gain, output power and power added efficiency versus input power (Vcc=1.8V) at 60GHz in singleended configuration.

[3]

[4]

IV.

CONCLUSION

A wideband Si-based MMIC PA has been realized using accurate model. Design techniques are carefully considered to accurately optimize the circuit. Measurement results at 60GHz indicate that SiGe transistors in balanced common-emitter configurations are able to generate 13dBm at their 1dB compression point and 18dBm at saturation with 8.6% of peak PAE. The chip demonstrates that high output powers are achievable in today’s production silicon technology with reliable techniques.

[5]

[6]

B. A. Floyd, S. K. Reynolds, U. R. Pfeiffer, T. Zwick, T. Beukema, and B. Gaucher, “SiGe bipolar transceiver circuits operating at 60 GHz,” IEEE JSSC, vol.40, no.1, p.156-167, Jan. 2005. S. T. Nicolson, K.H.K. Yau, S. Pruvost, V. Danelon, P. Chevalier, P. Garcia, A. Chantre, B. Sautreuil, S.P. Voinigescu, “A Low-Voltage SiGe BiCMOS 77-GHz Automotive Radar Chipset,” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 5, MAY 2008. E. Laskin, P. Chevalier, A. Chantre, B. Sautreuil, S.P. Voinigescu, “80/160-GHz Transceiver and 140-GHz Amplifier in SiGe Technology,” Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE, Volume, Issue, Page(s):153 – 156. C.H. Doan, S. Emami, D.A. Sobel, A.M. Niknejad, R.W. Brodersen, “Design considerations for 60 GHz CMOS radios,” Communications Magazine, IEEE, Volume 42, Issue 12, Dec. 2004 Page(s): 132 - 140. Ullrich R. Pfeiffer, and Alberto Valdes-Garcia, “Millimeter-Wave Design Considerations for Power Amplifiers in an SiGe Process Technology,” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL.54, NO.1, JANUARY 2006. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, R. Beerkens, N. Zerounian, F. Aniel, A. Chantre, “230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications,” IEEE JSSC, vol.40, no.10, p.2025-2034, Oct. 2005.


41