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Abstract—We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 11, NOVEMBER 2013

Die-Level 3-D Integration Technology for Rapid Prototyping of High-Performance Multifunctionality Hetero-Integrated Systems Kang-Wook Lee, Senior Member, IEEE, Yuki Ohara, Kouji Kiyoyama, Ji-Cheol Bea, Mariappan Murugesan, Takafumi Fukushima, Member, IEEE, Tetsu Tanaka, Member, IEEE, and Mitsumasa Koyanagi, Fellow, IEEE

Abstract— We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, finesized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5-µm diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a knowngood-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system. Index Terms— Backside through silicon via (TSV), die-level 3-D integration, hetero-integrated system.

I. I NTRODUCTION

D

EMAND for a high-performance multifunctionality hetero-integrated system has significantly increased in correspondence to anticipated future needs. To meet these demands, hetero-integrated system integrations involving memory, processor, power integrated circuits (ICs), sensor, and photonic circuits have attracted much attention owing to its high performance, high-speed communication, multifunctionality, and low power consumption [1]–[7]. However,

Manuscript received May 8, 2013; revised July 22, 2013; accepted August 27, 2013. Date of publication September 16, 2013; date of current version October 18, 2013. This work was supported by the New Energy and Industrial Organization “Development of Functionally Innovative 3DIntegrated Circuit (Dream Chip)” project based on the Japanese government METI IT Innovation Program. The review of this paper was arranged by Editor F. Ayazi. K.-W. Lee, J.-C. Bea, M. Murugesan, T. Fukushima, and M. Koyanagi are with the New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan (e-mail: [email protected]; beatrix@ bmi.niche.tohoku.ac.jp; [email protected]; fukushima@ bmi.niche.tohoku.ac.jp; [email protected]). Y. Ohara and T. Tanaka are with the Department of Bioengineering and Robotics, Tohoku University, Sendai 980-8579, Japan (e-mail: [email protected]; [email protected]). K. Kiyoyama is with the Department of Electrical and Electronic Engineering, Nagasaki Institute of Applied Science, Nagasaki 851-0193, Japan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2013.2280273

hetero-integrations of different functional circuit devices have many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. On-chip CMOS integrations [8], [9] and wafer-level encapsulation of sensors on CMOS circuits [10], [11] have limitations of complicated and extra processes, insufficient scalability with CMOS, poor temperature stability, and severe temperature constraints for volume production processing. Recently, 3-D integration technology has attracted attention, because it vertically stacks multiple large scale integration chips such as processor, memory, logic, analogue, and power ICs into one stacked chip. The 3-D integration technology can provide many benefits such as increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, and increased yield [1]–[5]. Semiconductor industries worldwide are currently focused on technology innovation, simulation and design, and product prototypes [12]–[14]. Recently, its stage has changed from the research or prototype production level to the investigation level for mass production. Dynamic RAM vendors and foundries already started small volume production of a couple of anticipated applications such as high-density memory modules, wide I/O handheld devices, and high-performance computers mainly for electrical systems and mobile products. However, the 3-D integration involving different functional circuit chips for achieving new architecture hetero-integrated systems has challenges such as high manufacturing cost and long prototyping time. Currently, to realize new architecture 3-D hetero-integrated systems, we have two options. One option is to ask semiconductor vendors and foundries to make different functional high-end device wafers with through silicon vias (TSVs) (via first/middle approaches). However, high-end customized wafers with TSVs are very expensive and need long test turnaround time to fully obtain different functional customized wafers. Another option is to get different functional commercial device wafers from semiconductor vendors and foundries, and make TSVs through TSV foundries and/or outsourced semiconductor assembly and test (via last approach). However, it requires many numbers of device wafers because of yield drop issue during 3-D IC process. Therefore, these approaches induce high manufacturing cost and long prototyping time. To realize new architecture 3-D hetero-integrated systems with low cost, high flexibility, and rapid prototyping time,

0018-9383 © 2013 IEEE

LEE et al.: DIE-LEVEL 3-D INTEGRATION TECHNOLOGY

Fig. 1. Schematic diagram of die-level 3-D integration technology for heterointegrated systems using different functional commercial chips.

Fig. 2. Process flow of die-level 3-D integration with fine-sized backside TSV and novel detachable bonding technologies. (a) Bump formation glue bonding. (b) Chip thinning and passivation. (c) Via formation, dielectric liner, and contact etch. (d) TSV and micro-bump formation. (e) 1st chip bonding. (f) De-bonding of support wafer. (g) 2nd chip bonding. (h) De-bonding.

we have proposed a die-level 3-D integration technology. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside TSV and novel detachable technologies have been developed. In this paper, we have demonstrated a 3-D stacked image sensor system comprising three different functional chips by the die-level 3-D hetero-integration technology. II. D IE -L EVEL 3-D H ETEROGENEOUS I NTEGRATION T ECHNOLOGY W ITH F INE -S IZED BACKSIDE TSV Our proposed novel die-level 3-D integration technology for high performance multifunctionality hetero-integrated systems is shown in Fig. 1. The commercially available 2-D chips such as those of sensor, logic, and memories with different functions and sizes, which were fabricated by different technologies, are processed to form TSVs and metal microbumps and integrated to form a 3-D stacked chip in die level. As commercially available chips are used, the die-level 3-D integration provides low cost, high flexibility, and rapid prototyping solution for hetero-integrated systems. Fig. 2 shows the die-level 3-D hetero-integration process flow using fine-sized backside TSV and novel detachable technologies [15], [16]. At first, a glue adhesive layer is spin coated on a supporting wafer with the alignment mark, which

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Fig. 3. chips.

New test concept for KGD 3-D stacked system using commercial

was formed by a metal patterning. Each functional chip with Cu/Sn bumps is glue bonded temporally by the high-accuracy bonder and cured in the vacuum chamber. The alignment accuracy within 2 μm is required to avoid the impact of misalignment on the subsequent backside lithography process for via formation. Then, the chips are thinned to ∼30-μm thickness by mechanical grinding and chemical mechanical polishing methods. After cleaning on the thinned surface by deionized water, a dielectric layer is deposited on the backside surface as a hard mask. Via holes are etched from the backside of Si substrate using SF6 and C4 F8 gases. A dielectric liner is deposited into via holes and the bottom dielectric liner in via hole is etched by dry etching using the dielectric hard mask. Barrier and seed layers are carefully deposited into via holes by sputtering. Cu electroplating is used to fill via holes. Cu and Sn electroplating are used to form Cu/Sn bump. All different functional chips are processed in die level simultaneously. After that, the bottom layer chip is bonded to a Si interposer with Cu TSVs and double-side metal microbumps. The stacked sample is dipped into a stripper and the supporting wafer is easily debonded from the chip surface by removing the glue layer using a stripper. After cleaning the chip surface by a cleaner, it is ensured that the second layer chip is bonded to the bottom layer chip and the supporting wafer is debonded again. By repeating these processes, different functional chips are sequentially stacked for achieving a 3-D hetero-integrated system. We propose a new test concept for realizing a known-good-die (KGD) 3-D stacked system using commercial 2-D chips, as shown in Fig. 3. To characterize the performance of commercial chips, the sampling chips of each different function with TSVs and microbumps are bonded to Si interposers, respectively. The full functions of each chip are characterized (Step I). As the function of each chip is fully passed, the 3-D integration process is carried out using these commercial chips. Another second layer chip (chip S-B), which is still not known as KGD prior to stacking, is bonded to a KGD bottom layer chip (chip C). After open/short test using a daisy chain and simple function test using a test block in the chip to confirm the joining quality between the bottom layer chip (chip C) and the second layer chip (chip S-B), the supporting wafer is debonded from the second layer chip. After confirming the chip S-B as a KGD, the stacking of another layer chip (chip S-A) is

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 11, NOVEMBER 2013

Fig. 5. SEM cross-sectional images after (a) backside Si etching and (b) Cu TSV formation. Fig. 4. (a) Design rule of backside TSV. (b) IR images after the backside TSV patterning to M1 layer.

carried out. By repeating these processes, a KGD 3-D stacked system can be fabricated. Subsequently, the full function of the 3-D stacked system is evaluated (Step II). Finally, as the full function is passed, the KGD 3-D stacked system with Si interposer is bonded to a print circuit board (PCB) (Step III). Backside Cu TSV technology is developed for realizing low-cost die-level 3-D integration. Via-last backside Cu TSV approach has high flexibility to commercial device chip/wafer. It also has better reliability from Cu TSV-induced stress and Cu contamination issues, when compared with via-middle Cu TSV approach. However, backside Cu TSV has some technological challenges such as alignment accuracy to metal 1 layer, notch-free Si via etching, and good electrical contact between backside Cu TSV and metal 1 layer [17]. To achieve compact-sized 3-D stacked system, the fine-sized backside TSV is designed, in which the Cu TSV of 5-μm diameter is connected to metal 1 layer of 14-μm width in back end of line (BEOL) passed through n+ well area of 9-μm width, as shown in Fig. 4(a). The TSV patterning on the backside surface of the thinned chip is performed using the alignment mark on the supporting wafer by a conventional mask aligner. Fig. 4(b) shows the infrared (IR) images after the backside TSV patterning, which shows that TSV patterns on the backside are well located within metal 1 layer in the front side with the average alignment accuracy of within 2 μm. Following Si via etching from the backside of Si substrate, a dielectric layer underneath the metal 1 layer in BEOL emerges when Si via etching is completed. However, the dielectric layer is not etched by Si etching gases, and as a result, significant sidewall etching (notch) of Si occurs at the surface of the dielectric layer during Si overetching because of accumulated positive ions. Time-modulation bias technology that periodically turns radio frequency bias ON and OFF to control plasma ion energy is applied to minimize notch phenomenon during Si etching. Fig. 5 shows the scanning electron microscopy (SEM) crosssectional images after backside Si etching [Fig. 5(a)] and Cu TSV formation [Fig. 5(b)]. The notch roughness is 10 000 frames/s [18], [19]. However, if the DPS circuit is simply added to an existing commercial chip, it induces low pixel resolution, because of the limitation of the

LEE et al.: DIE-LEVEL 3-D INTEGRATION TECHNOLOGY

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Fig. 9. Photographs of the fabricated Cu/Sn bumps and Cu RDL on the backside surface in die level. (a) Cross-sectional image. (b) Backside view. Fig. 7. (a) Conceptual diagram of prototype 3-D stacked image sensor system. (b) Circuit diagram of one block with block-parallel architecture.

using 0.18-μm front-side illumination CMOS image sensor technology. The CDS chip was fabricated using 0.18-μm CMOS technology. The ADC chip was fabricated using 90nm CMOS technology. The size of each chip was same at 5 × 5 mm2 , but the number of metal layer and the thickness of dielectric layer were different. B. Fabrication of 3-D Stacked Image Sensor System

Fig. 8.

Photographs and detail specifications of different fabricated chips.

chip size. If the DPS circuit is added to a customized chip using conventional 2-D process, it induces a large chip size, and hence low frame rate to realize such a high-speed image sensor with highly parallel image processing function. To realize high-speed and highly parallel image processing system with high pixel resolution and small size, we have proposed the 3-D stacked image sensor system, which can implement the frame rate of 10 000 frames/s with 2 Mpixel [20]. The dielevel 3-D hetero-integration technology is a promising way to fabricate the 3-D stacked image sensor with low cost, high flexibility, and rapid prototyping time [21]. In this paper, we implemented a prototype 3-D stacked image sensor system comprising three different functional chips of CMOS image sensor (CIS) circuit, hierarchical correlated double sampling (CDS) circuit, and analog-to-digital converter (ADC) array circuit, which were fabricated by different technologies. Fig. 7 shows the conceptual configuration of the prototype 3-D stacked image sensor system [Fig. 7(a)] and circuit diagram of one block with block-parallel architecture [Fig. 7(b)]. One image frame with 320 × 240 pixels is divided into 20 × 15 image processing blocks. Extra 180 blocks are placed at the periphery of image frame. Each block is composed of 256 CIS pixel circuits, one CDS circuit, and one ADC circuit, which are electrically connected in the vertical direction by TSVs. Totally, 480 (24 × 20) image processing blocks simultaneously operate in parallel in this 3-D stacked image sensor system. Within one image processing block, the image data are sequentially processed and transferred vertically through TSVs and metal, as shown in Fig. 7(b). To verify the block-parallel image processing by the 3-D stacked image sensor system, we designed customized CIS, CDS, and ADC chips with TSV areas. Each functional chip was fabricated by different technologies. Fig. 8 shows photographs and detail specifications of CIS, CDS, and ADC chips. The CIS chip was fabricated

Each functional chip of CIS, CDS, and ADC is processed and integrated to form the prototype 3-D stacked image sensor system using the die-level 3-D hetero-integration process flow (Fig. 2). The CIS, CDS, and ADC chips with Cu/Sn bumps on the chip surface are glue bonded temporally to supporting wafers and thinned to ∼30-μm thickness. After the deposition of plasma-tetraethyl orthosilicate tetraethoxysilane (TEOS) dielectric layer with 1-μm thickness as a hard mask, via holes with 5-μm diameter are etched from the backside until exposure metal 1 layer using BOSCH process. An ozone–TEOS liner with 300-nm thickness is deposited into via holes and the bottom dielectric liner in the hole is contact etched by dry etching. After the sputtering of barrier and seed layers, the via holes are filled by Cu electroplating. Cu/Sn bumps are formed by electroplating. All different chips are processed to form TSVs and Cu/Sn bumps in die level simultaneously. Initially, the ADC chip is bonded to a Si interposer. After open/short and simple functional tests to confirm the joining quality between the ADC chip and Si interposer, the supporting wafer is debonded from the surface of the ADC chip by removing the glue layer. By repeating these processes for the CDS and CIS chips, a known-good stacked chip of 3-D stacked image sensor system is fabricated. As the function of the 3-D stacked image sensor system is fully passed, the supporting wafer is debonded from the surface of the CIS chip. Color filters and microlens are formed on the surface of the CIS chip by spin coating and patterning processes in die level. Finally, a glass chip is capped on the top surface of the KGD 3-D stacked image sensor system using a patterned glue sealing layer to protect color filters and microlens. Different functional chips have different layouts depending on the fabrication technologies. To flexibly connect different functional chips, TSVs in each chip layer are connected by using redistribution metal lines (RDLs), which were formed on the back surface of each chip, as shown in Fig. 9. To focus color optical signals, color filters and microlens are formed on the CIS chip surface of the top layer in the 3-D stacked image sensor system and it is a key to form uniform thickness microlens in the die level. By optimizing spin coating and patterning processes, microlens of 3.0-μm height with