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Dec 22, 2015 - Abstract— Multilevel Inverters are nowadays becoming the state-of-the-art power electronic devices for high-power and power-quality seeking ...
Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015

Different Multilevel Inverter Topologies with Reduced Number of Devices Vanya Goel

Jagdish Kumar

Jaimala Gambhir

Department of Electrical Engg. PEC University of Technology Chandigarh, India

Department of Electrical Engg. PEC University of Technology Chandigarh, India

Department of Electrical Engg. PEC University of Technology Chandigarh, India

Abstract— Multilevel Inverters are nowadays becoming the state-of-the-art power electronic devices for high-power and power-quality seeking applications. While the classical topologies have proved to be a viable alternative, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the conventional topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switches are reviewed. Level Shifted triangular multicarrier waves are compared with the sinusoidal reference to generate sine PWM switching sequence. Based on a detailed comparison of the different topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application. Keywords— Multilevel inverters; reduced device count; new topologies; level shifted triangular multicarrier waves.

I. INTRODUCTION DC to AC power conversion is a key technology in the modern set-of generation, transmission, distribution and utilization of electric power. Multilevel inverters are nowadays becoming one of the industrial solutions for DC power source utilization (such as electricity obtained from batteries, solar panels or fuel cells) [1-2], high dynamic performance and power-quality demanding applications covering a power range from 1 to 30 MW [3–8]. They play a crucial role in variable frequency drives, air conditioning, uninterruptible power supplies, induction heating, high voltage DC power transmission, active filters and flexible AC transmission systems. Multilevel inverters can withstand for several important applications like hybrid electric vehicles, uninterruptible power supplies, reactive power compensation and regenerative applications. With the advent of recent power electronics devices, digital controllers and sensors, the role of power inverters also envisaged and acknowledged in frontiers such as futuristic smart grids and greater penetration and integration of renewable energy sources based power generation [9]. A multilevel inverter is basically a power electronic interface that produces a desired output voltage by connecting various DC sources and switches in the appropriate manner [10]. The basic concept of an MLI to achieve higher power is to use power semiconductor switches like IGBTs, MOSFETs, etc. along with appropriate DC voltage sources to perform the power conversion by synthesizing a staircase voltage waveform. Capacitors, batteries, and renewable energy voltage

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sources can be used as the multiple input DC sources. This paper reviews new topologies of multilevel inverters that have fewer semiconductor switches and gate driver circuits with higher number of steps in the output including the generation of 7 level multilevel inverter output waveform using 9 switches, 7 switches with Symmetric and Asymmetric topology, 6 switches with 4 and 3 DC sources and Reduced Device Count Multilevel Inverters (RDC-MLI) topologies. II. TOPOLOGIES A. Conventional Topology. A stepped output voltage and current can be obtained in a cascaded MLI by cascading several H-bridge inverters [1116]. Much of the literature published in past few decades have shown intense focus in studying the diode clamped, flying capacitors and cascaded H-bridge topologies with regard to their respective pros and cons [17-27]. The cascaded H-bridge topology for 7 level is designed by cascading 3 H Bridges, each H Bridge contains 1 dc voltage sources and 4 switches together forming 3 dc voltage sources and 12 switches in total. The output voltage for m level multilevel inverter is given by eq. (1), where, n is the number of switches used in the configuration. Each H Bridge produces 3 levels, i.e., +Vdc, 0,Vdc. By cascading these 3 bridges in such a way, it will produce 7 level stepped staircase waveforms. The switches of the same leg should not conduct at the same time so as to prevent short circuit across the voltage source. Fig. 1 represents the conventional cascaded 7 level H bridge inverter. 2 ⁄2

Fig. 1. Conventional Cascaded 7 level MLI

(1)

Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015 B. Seven level 9 Switch Topology.

C. Seven level 7 Switch Topology.

This topology consists of 9 switches that are connected in series and are capable of producing a stepped output [28]. Each voltage source is Vdc and thus we can get a maximum voltage 3Vdc. A 7-level output voltage is obtained having magnitudes Vdc, 2Vdc, 3Vdc in positive half cycle, zero level, Vdc, -2Vdc, -3Vdc in negative half cycle. H-bridge is responsible for the positive and negative level voltages. Switches S1 and S2 are used for positive level. S3 and S4 are used for negative level. Fig. 2 represents the 7 level 9 switch topology.

In order to reduce the total harmonic distortion further, two more switches are eliminated and thus 7-switch topology is developed as shown in Fig. 4. Except the H-bridge, only one switch is conducting for every instant and thus the operation becomes very simple and with lesser switching losses. For instance, we get output Vdc only when S3 is conducting. Since, each voltage source magnitude is Vdc, hence, this is called Symmetrical configuration.

Fig. 4. Seven level 7-switch topology with Symmetrical Configuration.

Fig. 2. Seven level using 9-switches topology

The following Table. I shows the switching sequence in which the devices should be switched in order to achieve the desired 7 level output waveform as shown in Fig. 3.

With the help of 7 switches, by using different values of the DC source i.e., Asymmetrical or hybrid configuration we can synthesize the 7 level output voltage waveform. Cascaded hybridized structure of [29] with phase disposition pulse width modulation as the switching scheme is introduced in [30]. Fig. 5 consists of two voltage sources of magnitude E and 2E. By proper switching it is possible to generate voltage levels of 0, E, 2E, 3E,-E,-2E and-3E.

TABLE I. SWITCHING STATES OF 9-SWITCH TOPOLOGY S.NO

S1

S2

S3

Output Voltage

1

0

0

0

0

2

0

0

1

Vdc

3

0

1

0

2Vdc

4

1

0

0

3Vdc

Where, 0 means OFF; 1 means ON.

Fig. 5. Seven level 7-switches topology with Asymmetrical Configuration

D. Seven level 6 Switch Topology with 3 DC Sources.

Fig. 3. Seven level waveform

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This topology comprises of three voltage sources and six switches thus, the circuit is simple to design and implement. The switches S2 and S4 are used for polarity reversal hence they are bidirectional in nature while switches S1, S5, S6, and S3 are used for waveform generation hence, unidirectional in nature as shown in Fig. 6. The circuit is used to produce seven

Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015 level output voltage waveform by designing appropriate pulse generation circuitry. It also have additional features like only two switches conduct at a given interval of time as only two switches are used for polarity reversal and rest of the four switches are used for waveform generation.

Fig. 9. Alternate Phase Opposition Disposition PWM technique.

Fig. 6. Seven level 6-switch 3 DC Source Topology

The generalized equations for the number of devices and the number of input dc sources for the above discussed topology is given by eq. (2) and eq. (3) respectively:

2 5 (2) Where, M= number of levels and S= number of switches. 2 1 (3) Where, V=number of dc voltage sources. By using these two equations we can find the number of voltage levels, number of dc sources and switches for any levels. The following Fig. 7, 8, 9, 10 show the level shifted PWM modulation techniques [31-34].

Fig. 10. Alternate Phase Opposition Disposition + Variable Frequency PWM technique.

E. Reduced Device Count Multilevel Inverter (RDC-MLI) Topologies. These topologies are proposed with an exclusive claim of reducing the number of controlled switching power semiconductor devices for a given number of phase voltage levels are referred to as RDC-MLI topologies. In this paper nine such topologies [35-40] are reviewed. Following are the various reduced device count multilevel inverter topologies: 1) Cascaded Half-Bridge based Multilevel DC Link (MLDCL) Inverter. Gui Jia Su [35] has presented a new multilevel inverter named as “Cascaded Half-Bridge based Multilevel DC Link (MLDCL) Inverter”. An MLDCL inverter with four DC levels is shown in

Fig.11. It comprises of cascaded half-bridge cells, with each cell having its own DC source. Various valid switching combinations that can be used to obtain the multilevel DC link voltage vbus (t). Fig. 7. Phase Disposition PWM technique.

Fig. 8. Phase Opposition Disposition PWM technique.

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Fig. 11. Cascaded Half-Bridge based Multilevel DC Link (MLDCL) Inverter.

Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015 2) Switched Series/Parallel Sources (SSPS) based MLI. Hinago and Koizumi [36] proposed a single-phase multilevel inverter consisting of an H-bridge and DC sources which can be switched in series and in parallel. This topology with four input DC sources is shown in Fig.12, consisting of two parts: level-generation part which consists of the switched sources and synthesizes a bus voltage vbus (t) and the polaritygeneration part which synthesizes positive and negative cycles of voltage vbus (t) to feed an AC load.

generation” parts. The level-generation part consists of input DC sources and bidirectional-blocking-bidirectionalconducting switches. The switches in the polarity-generation part are unidirectional-blocking-bidirectional-conducting and have to withstand the maximum voltage generated by the level generation part as shown in Fig. 14.

Fig.14. Multilevel Module (MLM) based MLI Fig. 12. Switched Series/Parallel Sources (SSPS) based MLI

3). Series Connected Switched Sources (SCSS) based MLI. This topology with sources connected in series through power switches is described in literature [37]. It consists of four input DC sources Vdc,j { j = 1 to 4}. The low potential terminals of the sources are all connected through power switches while being also connected to the higher potential terminal of the preceding source through power switches, as illustrated in Fig.13 with Sj { j = 1 to 8}. This interconnection is capable of synthesizing a multilevel rectified waveform vbus (t).

Fig. 13. Series Connected Switched Sources (SCSS) based MLI

4). Multilevel Module (MLM) based MLI. Babaei [38] presented MLM based MLI. This topology consists of separate “level-generation” and “polarity-

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5). Reversing Voltage (RV) Topology. In [39] Najafi et al. have proposed Reversing Voltage MLI (RV-MLI) topology. A single-phase RV-MLI with four input

DC sources, Vdc,j {j = 1 to 4}, is shown in Fig.15. The levelgeneration part comprising of the input DC sources and switches Sj {j = 1 to 8}. The polarity-generation part consists of switches Qj {j = 1 to 8}, operating at the line frequency. To overcome the issue of voltage balancing separate DC sources are used.

Fig.15. Reversing Voltage (RV) Topology

6). Two-Switch Enabled Level Generation (2SELG) based MLI. This topology is presented by Babaei in [40]. It has separate level-generation and polarity-generation parts and requires a

Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015 mix of unidirectional and bidirectional switches. The specialty of this topology is that the level-generation part requires only two conducting switches to synthesize any valid voltage level, irrespective of the number of input sources. Therefore, this topology is referred to as “two-switch enabled level generation (2SELG) based MLI” as shown in Fig.16.

TABLE.IV. ADVANTAGES AND LIMITATIONS OF REDUCED DEVICE COUNT MULTILEVEL INVERTER (RDCMLI) TOPOLOGIES. Topology

Advantages

Disadvantages

MLDCL- MLI

i) Highly modular and simple ii) Requires only unidirectional switches

i) Requires isolated input DC levels. ii) Trinary source configuration can’t be employed.

SSPS-MLI

i) Input DC sources can be combined in both series and parallel ii) Equal load sharing is possible amongst input DC sources

i) Highest voltage rated switches cannot be operated at fundamental switching freq.

SCSS-MLI

i) Simple structure ii) Highest voltage rated switches can be operated at fundamental switching freq.

i)Symmetric configuration mandatory

MLM-MLI

i) Requires non-isolated DC sources ii) Simple structure

i) Equal load sharing is not possible ii) Asymmetric source configuration not possible

RV-MLI

i) Requires non-isolated DC sources ii) Single DC link feeds all the three phases

i) Equal load sharing is not possible ii) Asymmetric source configuration is not possible

2SELG-MLI

i) Requires non-isolated input DC levels ii) Low conduction losses

i) Equal load sharing is not possible ii)Asymmetric sources cannot be employed

Fig. 16. Two-Switch Enabled Level-Generation (2SELG) based MLI TABLE.II COMPONENT COMPARISON OF DIFFERENT TOPOLOGIES. Topology

No. of capacitors

No. of diodes

No. of switches

No. of sources

Flying Capacitor Diode Clamped

14

-

10

-

6

>=8

10

-

Cascaded 7 level 7 level 9 switch

-

-

12

3

-

-

9

3

7 level 7 switch

-

-

7

3, 2

7 level 6 switch

-

-

6

4, 3

TABLE.III PERCENTAGE THD COMPARISON OF TOPOLOGIES.

III. CONCLUSION

DIFFERENT

PWM Technique

PD

POD

APOD

Cascaded 7level

24.26

23.13

22.46

7 level 9 switch

-

21.6

-

7 level 7 switch symmetrical 7 level 7 switch asymmetrical

-

18.5

-

-

16.7

-

7 level 6 switch 4 dc source

18.06

16.15

18.52

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DC

source is

Multilevel inverters have matured from being an emerging technology to a well-established and attractive solution for medium voltage high power applications. New multilevel topologies have been reviewed, offering high output resolution with a reduced number of power switches. With fewer switches, controlling the overall circuit becomes less complex, the size and installation area reduces. It can be seen that minimum THD content is obtained from the 6-switch topology with POD PWM technique. In case of Asymmetrical configuration only 2 dc sources are required which can also be realized through renewable energy resources like photovoltaic system and its integration with electric drives. A review of nine Reduced Device Count multilevel inverter topologies is also presented and a comparison has been made so as to facilitate a well-informed selection of topology for a given application.

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