Differential CMOS edge-triggered flip-flop based on clock racing. Y. Moisiadis and 1. Bouras. A diftccrcntial CMOS cdgc-lriggcrcd flip-flop is psoposcd tililt.
Conchisiuiir: A bandpass dclta-sigma class-S amplificr has hccn cxperimentiilly demoiistralcd a t IOMHz. At a lhird-order intermodulatioii lcvcl of 400.XdBc, a drain clficiency or 33%)and pcak power of 23dBni per tone (26dAm lolal power) wcrc ncasured. This comhination of distortion and eniciency dciiioiislrates (he possibility of attilining hoth high linearity and efficiency in narrowband RI' powcr ampliiier applications.
Acl~iiui~~ledfimenrr: Tlie authors would like Lo thank J. Bcllora lor his generous help. This projccl is funded in part by DUSD (S&T) and the US ARO iindcr the M U R l program, 'Low I'owerILow
M8 cnablc llie flip-llop to bc iictivc only during llie rising cdgc of thc clock (edge-triggered opcralion). Transislor M I is drivcn by thc clock signal (CLK), while lransistor MX is controlled by a dclayed version of tlic invcrlcd clock (CLKI). Conscqucnlly, there cxists a conductive path to ground only during the timc period where hoth signals CLK and CLKI are high (from fl to f2 as illustratcd in Fig. Ih). During this short liine period, innncdialcly after ihc rising edge of thc clock, lhc flip-flop can changc ils slate accordiiig to the daia signal. Wlicn either M I or M8 is off, no conductive path to ground cxists and Llie flip-flop is in its ioniransparcnt statc, kceping the last samplcd d a h
Noise Elcctronics for Wireless Coiniiiunications'. .. IFF. . - moo . .... ,Ylwiro,iic,r I.er!er,s Online No: 200007'14
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IIANIUOTON.ti., LI\KSON, I.,, Uld ASnECK, P.:
'Linear higb-dficicncy tniciowve powcr iiinpliricrs using bimdpass dclta-sigma modulalors', IEEE Microw Cuid IWuw Lei!., 1998, 8,
Differential CMOS edge-triggered flip-flop based on clock racing Y . Moisiadis and 1. Bouras
a
A diftccrcntial CMOS cdgc-lriggcrcd flip-flop is psoposcd tililt crnploys R pair of cross-cuuplcd invcvtcrs, providing Sdly slnlic opcralion. The edgetriggering opcration is ;chicvcd by a niwrow polsc, produccd by the clock signal ;md its invcncd dchycd
GND
CLK-
vcrsioii. 'Ihc proposed flip-flopcxhibirs sigiiificiml powci- swings O I 25W, when compimd wilh other stattic differcnlial flipflop circuits, miiintaining ils spccd advuntiip Soor dirrcrcnl {iowci supply voltages end data activity r;iles. 11 also lrquircs only 12 tsansistoss resulting in a rcduccd tlansislor COLIII~.Moleovcr. onlikc llic cxisling diffcreotiiil cimuils, it lhas thc ahility l o openilc under a rcdoccd silring clock signal, willmit sttitic power dissipation. or tip
Infr.oducl;on: Thc flip-flop is one of tlic most criicial dements in
inodcrn synchronous VLSl dcsign, as it is tlic basic slorage elemen1 in every pipcline stage, seriously affccling the overall systcm performancc. Flip-flops can bc catcgorised into two lypcs: ditl'erentia1 and non-din'erential. Although ion-diCferentii1 flip-flops cxliibit low-power and high-speed charactcristics, dill'erential slrudures can play thc rolc or amplificrs whcn the logic in lhc pipelinc opcfillcs wilh reduced voltdgc swing signals. Tlicrcforc. cvcn iS diSrerentia1 flip-flops iire no1 low powcr circuils, lhey may he used to rcducc the overall powcr dissipalion in pipelinc struc-
Lures. ipfion: o/ie,wcion: Fig. 10 illustratcs thc proposed cdgc-triggered flip-flop circuit. It consists of a pair of cl-oss-couplal inverters (transislors MI-M4), providing fully static opcrition. The numbcr of transistors can bc liirllicr reduced by climinaling transistors M3 and M4, resiiliing in a scmi-slalic dcsign. The data signal atid ils complementary (D and Dh) control transistors M5 and Mh, respectively. l o increase the driviiig capability o f llie flip-flop circuit, an inverting slage is iiiscrtcd in each oulpul of llie cross-couplcd pair. Tlie cascadcd transistors M I and
1012
The CLKI signal ciui bc gcncnitcd locally by using a chain of invcrters as shown in rig. Ih. The Cxll'd area and power introduced by lhe inverting chain c m he considered negligiblc if CLKI is shared hy otticr acljljaccnl ilip-flop cells. Clock signal racing has also been employed for tlic gcneralion of a narrow pnlsc in the design of a CMOS cdgc-triggcred Ilip-flop [I].Howcvcr in [I] three additional clock signals are nccdcd apart from lhe main clock, whilc in tlic proposed Ilip-flop only onc cxtra clock signal is necessary, rcducing in lhis way the powcr dissipatcd by llie clock. A vcry altraclive featnrc of tlic proposed Ilip-tlop is that it cmploys only a11 NMOS transistor a s lhe clock load. As a rcsnlt,
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apart from amplifying daia signals wiili reduced voltiige
swing,il
reduced-swing clocking schcmc without exhibiting static power dissipation. In contrast, convciitional diffcrcnlial flip-flop cells are clockcd with NMOS and PMOS transislors. This rcsults in static power dissipation if rcduced-swing clock signals arc applied to PMOS devices.
Tablc 2 analytically presents the powcr dissipated liom eacli flip-flop, for V = 3.3V u i d V,,,> = 2.5V. I n the casc oCllie proposed flip-flop, the CLK power dissipation also includes 25% of the power dissipatcd by the invertcr chitin, wlieii CLKI is slxircd by four cquivalent flip-flops. The last coluiim illuslrales lhc power dissipation gain of tlic proposed flip-flol, ovcr the two other circuits, which can bc up to 22 tind 15% wlicti comparcd lo ihc SSTC and thc StrongAriiil 10 flip-flops, respeclivcly.
SCnul&~n results: The proposed edge-lriggcrcd flip-flop l i a s heen coinpared with two well-known differential flip-flops, llie SSTC flip-flop [2] and tlic scnse-mplifying flip-llop used i n StrongArm110 [3], illustrxled in Figs. 20 and b, rcspcctively. All the simulations were carried out using a SPECTRE simulalor, with a slandard 0.35pIii AMS CMOS technology. The clock frcquency was IOOMHz. Tlie lransislor lengths arc niiiiiinuin for tlie abovc lcchnology, whilc llie transistor widths arc given in thc parailheses in Fig. l o and Figs. 20 and 11.
Coiidu,sioi,n:A new slatic difkrenliiil CMOS cdge-triggcrcd flipflop has bccn presenled. Tlic cdgc-triggering opcrxlion was achieved hy incam of clock racing. The proposed circiiil results in significanl power savings (up lo 2S%) and spccd gain, whilc rcducing thc Iransistor count when comparcd with cxisling diffcrenlial flip-flop slructures. It is also cwpahlc of i~pcratingundcr reduced swing clock signals without static dissipation.
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Tablc I: CLIC-Q delay times Ins] and riseifill times [lis]
14 April 2000
Tlie proposed Ilip-flop rcquircs fewer traisistors: it cmploys four and six tl-ansislors fewer than llie SSTC and StrongArmlIO {lip-llops, rcspcctively. Tablc I prcsenls tlie CLK-Q delay during lhe low-to-high (LH) and high-blow (Ill.) lransiiion, along wilh lhc rise lime (RT) and fall limc (FT) for Vn,, = 3.3V and V,, 2.5V, respcctivcly. Compared to the SSTC flip-llop, lhe proposcd flipflop prcsents an improved CLK-Q delay tiinc during the I A I transition, while outpcrforming lhe StrongaArml 10 flip-flop for holh the LIT and HL transitions. Moreovcr, il ofrers stccpcr oulpill pulses, reducing lhe short-circuit currcnt i n llie succccding logic stages. To fairly compare the differciil flip-flop circuils i n tcriiis of power dissipation, wc rollowed a melhodology similar to that bund in [4]. In ~ a c hflip-flop the daca iind clock signals wcrc provided through buffering inverters and not as ideal vollage sonrccs. Consequciiily, the local clock end data power dissipalion was dcrived as lhe diffcrcncc in the power dissipation OF each bnffcring inverter, when loaded wilh a flipflop and whcn unloaded. Morcover, to cstimale their driving capabilities, eacli outpul was loaded with CL = 1OOfF. The powcr dissipation was cvalualed Cor a time pcriod ni' loons, considering two different data aclivily ralcs (I = 0.5 and n = 1. 'Table 2: Power dissipation sonrccs
Characteristics of regenerative erbiumdoped fibre ring amplifier B.P. Singh A s ~ i i d y is ~pmcnted into h c dyn;unic chiil.iictesistics of
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LiiiidirccLioiial rcgcncnitivc cl-binin-dopcd fibre ring amplifier ill bclow l i i w threshold. A coiisidcl.ihle improwmcnl i n gain and tioisc ligurc Ipl-rm1ancc was observed duc to 11ic suplxession of ;unplified sponlimcous eiiiissioii in llic mgcncnitive smplitication ~ p ~ o c e iIit. was found tliiit IOWCI. fccdback liowci Iprwitbs liigliei opticid gain. Ao opticid signal of -33.5dR wiis formd to enpcricncc ii g;iin o f t 35dU ill iiad ticar tlie tcsoiiiinm wavelength wing l'% fccdhact by t i i i optical fibm couplcr for a n optical pump (1480nin) liowcr iih IOW as loinW.
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gciierally regarded tis a regenerativc oplical amplificr (ROA) where a sintill porlion of tlic output light is Ted hack to Ihc resoiiiitor [ I 41. 'I'hc ROA syslcm can amplify or evcn alteniiatc tlic inpui signal dcpcnding on the gain tncdintn pcrfon-manccand cavity paramctcrs. 'I'hcorelical analysis shows that ihc signal gain G of an ROA clcpends on frcqucncy detoning 'Aw'and cavily losscs ;ind can he given by G(A'(aw) = yl(Aw2 -1. y, ( I where y is the intensily damping rate of the optic;il couplcr and y,. is the total damping riilc 01' the cavity field. Parameter C is less than iinily wlicii operaling hclow llic laser oscillation threshold [3]. I1 l i a s heen reccntly sliowti experiincoially thal [lie use of a rcgenerativc erbium-dogcd lihre ring ;implilier leiids to an improvemenl in the noisc performancc of iiii optical amplificr ;ind [lie optical gain dcpciids on tlic input signal level, and a gain as high as 23.9dB lias hccn dcmonslraied for 30% fccdback [I]. Ilowcvcr; 110 invcstigalions havc bccn carricd out into the e k l of ihc coupling ratio on lhc gain iind noisc pcrfommnce, which is a i important
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