Diffusion and Gate Replacement - IEEE Xplore

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Abstract—In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow ...
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 1, JANUARY 2016

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Diffusion and Gate Replacement: A New Gate-First High-k/Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry Romain Ritzenthaler, Member, IEEE, Tom Schram, Alessio Spessot, Christian Caillat, Moonju Cho, Eddy Simoen, Marc Aoulaiche, Johan Albert, Soon-Aik Chew, Kyoung Bong Noh, Yunik Son, Jerome Mitard, Anda Mocuta, Naoto Horiguchi, Pierre Fazan, Senior Member, IEEE, and Aaron Voon-Yew Thean, Senior Member, IEEE Abstract— In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high-k, and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material downselection is done (TiN/Mg/TiN gate-stack for nMOS and Al2 O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2 O3 ) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. Index Terms— Al2 O3 capping layers, CMOS process integration, diffusion and gate replacement (D&GR), dynamic random access memory (DRAM) periphery transistors, high-k metal gate (HKMG), La capping layers, Mg capping layers, MOSFET fabrication.

I. I NTRODUCTION YNAMIC random access memory (DRAM) technologies use a lot of transistors in their peripheral circuitry (address decoders, high-voltage applications, and

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Manuscript received September 9, 2015; revised November 2, 2015; accepted November 12, 2015. Date of publication December 7, 2015; date of current version December 24, 2015. This work was performed as part of imec’s Core Partner Program. The imec Core CMOS program members, the imec pilot line and amsimec are greatly acknowledged for their support. The review of this paper was arranged by Editor W. Tsai. R. Ritzenthaler, T. Schram, M. Cho, E. Simoen, J. Albert, S. A. Chew, J. Mitard, A. Mocuta, N. Horiguchi, and A. V.-Y. Thean are with imec, Leuven 3001, Belgium (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). A. Spessot, C. Caillat, M. Aoulaiche, and P. Fazan are with Micron, Boise, ID 83707-0006 USA (e-mail: [email protected]; ccaillat@ micron.com; [email protected]; [email protected]). K. B. Noh and Y. Son are with SK Hynix Inc., Icheon 467-701, Korea (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2015.2501721

sense amplifiers [1]). Currently, the DRAM periphery transistors in high-volume manufacturing are still based on polysilicon/SiO2, and are behind the logic in terms of scaling due to stringent cost requirements. In order to guarantee the performance required by the next generations of memories, the industry roadmap expects that such devices will adopt characteristics already used in high-performance logic devices [1]. Therefore, the introduction of high-k metal gate (HKMG) [2] is expected to be a key enabler for future DRAM periphery transistors (2× node, corresponding to L G ∼45 nm [3] and beyond). In order to target low-power mobile applications, low leakages are also a necessity; the transistors used in the periphery of the memory cell are typically more aggressive in terms of gate leakage [hence, a thicker electrical oxide thickness (EOT) compared with logic applications] and junction leakages (OFF-state current) control. In [4], we reported an HKMG CMOS integration compatible with a 2× node DRAM process flow. In this paper (see also [5]), we extend that work and present a new scheme [diffusion and gate replacement (D&GR)] that allows to control the gate height asymmetry and simplify the gate patterning that permit the mitigation of potential yield issues. Although some patents have been proposed on a similar approach [6]–[8], to the best of our knowledge, this is the first time that such a process flow is implemented in a complete solution, which is in addition compatible with a DRAM periphery application. The D&GR integration concept is presented and validated with physical analysis in Section II. The material downselection is presented in Section III-A. The process window definition is presented in Section III-B. The CMOS integration solutions and drive current performance are presented in Section III-C. II. D IFFUSION AND G ATE R EPLACEMENT C ONCEPT A. Proof of Concept The gate-stack effective work function (eWF) for low-power applications should be low (respectively, high) enough for nMOS (respectively, pMOS) to deliver an acceptable ON-state current while maintaining a strict control of the OFF-state currents, leading to relaxed VTH targets compared with logic applications.

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Fig. 1.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 1, JANUARY 2016

Main steps of the D&GR process.

Fig. 3. SIMS profile of a HfO2 -based stack after Al2 O3 cap-based D&GR processing (diffusion anneal and dummy metal removal) with different annealing temperatures. The diffusion of Al into the high-k during D&GR process is evidenced.

Fig. 2. ERD concentration in HfO2 -based stack after TiN/Mg/TiN cap-based D&GR processing with different annealing temperatures. The diffusion of Mg into the high-k during D&GR process is evidenced.

This is typically obtained with the use of capping metal layers (La based [9]–[13] or Mg based [4], [14], [15] for nMOS devices, and Al based for pMOS [16]–[18] devices) or by implantations in the metal gate (Ar or As ion implantation [19], [20]). The former is expected to create dipole diffusion toward the high-k/SiO2 interface [21], while the latter is filling the preexisting traps in the HKMG [22]. For pMOS gate-stacks, the threshold voltage lowering is obtained by the incorporation of Al and the subsequent creation of dipoles originated from the Al2 O3 diffusion [21]. The DRAM periphery compatible HKMG gate-stack demonstrated in [4] uses HfO2 coupled with Al2 O3 capping (between interfacial layer and high-k) for pMOS devices. For nMOS, a TiN/Mg/TiN stack together with As ion implantation for nMOS is used. The key idea in the D&GR gate-stack module is to diffuse n-type and p-type shifting elements from doped dummy metal gates or cap layers in a dedicated diffusion step, and then to remove the dopant source (Fig. 1). By design, in a D&GR flow, nMOS and pMOS eWF shifters should be deposited on the top of high-k. With a standard capping layer approach, Al2 O3 above HfO2 exhibits marginal differences in terms of threshold voltage and reliability compared with Al2 O3 deposited below HfO2 [23]. Gate leakage is even slightly improved at fixed EOT, showing no hurdles for D&GR with Al2 O3 capping layers. In order to assess the feasibility of the integration flow, it should be proved first that the eWF shifter can be driven into the higk-k. For nMOS and Mg [grown with atomic layer deposition (ALD)], this is done using elastic recoil detection (ERD) (see Fig. 2). Mg is detected into the high-k layers even after the dummy doped metal gate removal. The detected dose is higher when the dose in the dummy doped metal gate and the thermal budget are higher, as expected. It should also be noted that the dose after the dummy

Fig. 4. Schematic of the process flow. The position of the new D&GR gate-stack module is highlighted.

doped metal gate removal is lower than the dose before removal. The thermal budget necessary to shift the work function might, therefore, be relatively high and may degrade other electrical parameters (see process window evaluation in Section III-B). For pMOS, secondary ion mass spectroscopy (SIMS) is used to detect the presence of the ALD Al inside HfO2 . By increasing the drive-in anneal thermal budget (from 600 °C, 4 h to 850 °C, 3 min), more Al is detected into the high-k and near the SiO2 interfacial layer (Fig. 3). Physical analysis, thus, confirms that it is possible to drive the eWF shifter species into high-k, and to keep part of it even after dummy doped metal gate removal. B. Integration Flow The gate-first D&GR CMOS integration flow is illustrated in Fig. 4. After shallow trench isolation formation and well doping, an interfacial layer is grown (thickness of 1.3 nm, using in-situ steam generation). A 2-nm HfO2 high-k layer is subsequently deposited. For the D&GR gate-stack module itself, a shifter-doped metal gate is then deposited and selectively removed from the unwanted side (the example is given with an nMOS-first approach in Step 1 of Fig. 5). The shifter-doped metal gate corresponding to the other polarity is then also deposited

RITZENTHALER et al.: D&GR: NEW GATE-FIRST HKMG CMOS INTEGRATION SCHEME

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Fig. 5. Proposed D&GR gate-stack module. The preferred nMOS-first implementation is illustrated here. A Mg-based TiN sandwich, followed by an Al2 O3 cap layer is used for nMOS and pMOS VTH shifting.

(Step 2 of Fig. 5), and a dedicated diffusion annealing step is applied (Step 3 of Fig. 5). Using an standard clean 1 (SC1)-based wet etching, the TiN [physical vapor deposition (PVD)]-based dummy electrodes can be removed selectively to HfO2 (Step 4 of Fig. 5), and subsequently replaced by an undoped PVD TiN electrode (Step 5 of Fig. 5). Additional dopant diffusion and, hence, unwanted further VTH shift during subsequent thermal processing is avoided. Thanks to the redeposition of an undoped metal gate, it is also expected to have identical gate height. This greatly simplifies the gate patterning tuning in order to obtain vertical gate profiles. After gate patterning, junctions are formed with lightly doped drain, halo, spacer deposition, heavily doped drain implantations, and activation. After the source/drain silicidation, the memory DRAM emulation anneal is added (thermal budget in the 600 °C–750 °C, ≥1-h range). The process flow is completed with the conventional back end of line up to metal 1 level. III. CMOS I NTEGRATION A. Material Choice Additional complication for D&GR CMOS integration are potentially a too high difference of diffusivity between the two chosen species, yielding a situation where one eWF shifter is overdiffused (most notably in the channel) while the other barely diffused into the high-k. On the other hand, in a CMOS integration, one of the work function shifters is deposited on the top of the first gate-stack (Step 3 of Fig. 5); if the diffusivity of this eWF shifter is too high, it might diffuse through the first metal gate-stack and contaminate the high-k. It is also possible that some layers crystallize if the diffusion annealing thermal budget is too high, increasing the difficulty to remove them during the dummy gate-stack removal step (Step 4 of Fig. 5). Even after proving that D&GR was a possible integration concept, the feasibility of CMOS integration is, therefore, far from obvious, and a screening of the potential materials is needed. The results of the first material screening are summed up in Fig. 6. Regarding nMOS side, La is providing a solid eWF shift but is more difficult to remove. La leaves some residues when used as a cap directly on high-k, and is forming an insoluble component when used in a TiN/La/TiN sandwich. Mg (grown with ALD), on the other hand, pro-

Fig. 6. Selection criteria and results for the choice of the nMOS and pMOS dopant species, as well as the dopant location and the integration order.

vides less eWF shift but is usable both in the form of capping layers and TiN/Mg/TiN sandwich. Regarding pMOS eWF shifters, Al is hard to use, since it is diffusing very fast and tends to form an insoluble AlN compound. Al2 O3 (grown with ALD) is functional, but like La capping tends to leave residues when used directly on high-k. A thin TiN/Al2 O3 /TiN sandwich is usable if the Al2 O3 layer is below 1 nm [necessary in case of removal on nMOS side (see Step 3 of Fig. 5)]. Overall, the best combination of materials is, therefore, Mg (TiN/Mg/TiN sandwich or direct capping, with Mg grown with ALD and TiN with PVD) on n-side with Al2 O3 capping (grown with ALD) on the p-side (with a thickness of