Direct Multichip-to-Wafer 3D Integration Technology Using Flip-Chip Self-Assembly of NCF-Covered Known Good Dies Yuka Ito1, 2, *, Mariappan Murugesan3, Takafumi Fukushima3, *, Kang-Wook Lee3, Koji Choki2, Tetsu Tanaka1, 4, and Mitsumasa Koyanagi3 1 Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan E-mail:
[email protected], Phone: +81-22-795-6909, 2 Circuitry with Optical Interconnection Business Development Dept., Sumitomo Bakelite Co., Ltd. 3 New Industry Creation Hatchery Center, Tohoku University 4 Deptartment of Biomedical Engineering, Graduate School of Biomedical Engineering Tohoku University
Abstract We demonstrated surface tension-driven self-assembly and microbump bonding using NCF (non-conductive film)covered chips with Cu/Sn-Ag microbumps for highthroughput and high-yield direct multichip-to-wafer 3D integration. The NCF is a promising candidate to completely fill gaps between fine-pitch microbumps, and is essential for realizing highly-reliable microbump-to-microbump interconnections. Here, by applying the self-assembly method with strong water surface tension, the NCF-covered chips were precisely aligned to hydrophilic assembly sites defined on host Si substrates in a face-down manner with alignment accuracies of approximately 1 µm. The self-assembled chips having Cu/Sn-Ag microbumps covered with NCF were thermally compressed to obtain electrical joints between the chips and substrate after the self-assembly process. The resulting daisy chains showed good electrical characteristics with contact resistance of 53 mΩ/joint.
assembly methods. In addition, no support wafers are required for 3D integration processes. (a)
(b)
Introduction Chip-to-wafer stacking is a promising candidate to realize high-production yield for 3D and hetero system integration owing to the use of known good dies (KGDs) [1]-[7]. In the 3D and hetero system integration, different-sized chips and various materials/devices are highly integrated. Therefore, high-precision, high-throughput, and high-yield 3D chip stacking technologies are essential for creating advanced 3D and heterogeneous systems with TSVs. Conventional robotic pick-and-place machineries such as a flip chip bonder are still mainstream method for chip assembly. However, the one-byone sequential methods have serious trade-off between assembly throughput and alignment accuracy. Thus, to realize the advanced 3D and hetero system integration, we have developed multichip self-assembly techniques using liquid surface tension that drives KGDs to precisely predetermined positions with higher alignment accuracies [8]-[16]. In the series of our previous works, we proposed and developed “Direct multichip-to-wafer 3D integration technology” based on the self-assembly techniques that are essential to improve throughput of the whole integration processes, as shown in Figure 1. The 3D integration is completed by repeating the stacking process of chips. This technology is free from abovementioned trade-off between throughput and alignment accuracy lying in conventional mechanical pick-and-place
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Figure 1. Conceptual drawings of “Direct multichip-towafer 3D integration using flip-chip self-assembly” : (a) stacking process of 1st layer and 3D integration, and (b) schematic drawing for self-assembly technique.
We have previously reported precise flip-chip selfassembly and microbump interconnections using KGDs with fine-pitch In/Au bumps [12-14] and with Cu/Sn bumps [15, 16], respectively. This paper proposes a new flip-chip selfassembly method using KGDs covered with NCFs to realize high-throughput and highly-reliable microbump interconnections for advanced direct multichip-to-wafer 3D integration. Compared to conventional die-level capillary underfills with a one-by-one injection process, in recent years, waferlevel underfill using pre-underfill materials called “nonconductive film (NCF)” will become further necessary for the chip-to-wafer 3D integration to fully fill narrow gaps between KGDs and a substrate wafer with fine-pitch (< 10 µm)
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microbumps. In this paper, to realize high-throughput and highly-reliable multichip-to-wafer 3D integration, we demonstrate a new multichip self-assembly with KGDs having fine-pitch Cu/Sn-Ag microbumps covered with a NCF. Figure 2 show a conceptual drawings of self-assembly and bonding process with the NCF-covered KGDs. The KGDs with the NCF are directly self-assembled on a substrate wafer in a flip-chip bonding manner. And then, the subsequent wafer-level thermal compression provides rigid microbump interconnections. We also describe the evaluation of alignment accuracies using the KGDs covered with the NCF and electrical characteristics of microbump interconnections after the KGD assembly and the NCF bonding. Furthermore, we discuss throughput of the direct multichip-to-wafer 3D integration technology.
was formed outside the assembly sites in order to define precise assembly sites with the same size of 3-mm square to the designed chip outer size. In contrast, the NCF was laminated on the wafers for the chips with vacuum laminator. Finally, the wafers were diced with a standard blade dicer. Figures 3(a) and 3(b) show photographs of the resulting chips and substrates with Cu/Sn-Ag microbumps and Cu wirings. An SEM image of the representative microbumps formed on the substrates and the chips is shown in Figure 3(c). (a)
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Figure 2. Self-assembly and bonding processes with NCF-covered KGDs in batch processing.
Figure 3. (a) Photographs of the wafer covered with the NCF after chip dicing, (b) photographs of the wafer for the substrate, (c) an SEM image of Cu/Sn-Ag microbumps.
Fabrication of chips and substrates with microbumps 8-inch wafers were utilized for the fabrication of interposer substrates without the NCF and 3-mm-square chips covered with 17-µm-thick NCF. Cu/Sn-Ag microbumps with the size of 10-µm-square, 30-µm-pitch, and 6.5-µm-height were formed on both wafers. Firstly, Ti barrier and Cu seed layers were sputtered onto a thermal silicon dioxide layer on the wafers. 2.5-µm-thick Cu wirings were fabricated by photolithography and electroplating. After Cu seed and Ti barrier etching, a silicon dioxide layer as an insulation layer and assembly sites was deposited by plasma-enhanced chemical vapor deposition on the Cu wirings, and contact holes were formed by reactive ion etching (RIE). Cu/Sn-Ag microbumps were fabricated by photolithography, electroplating, and vapor deposition. 1.5-µm-thick Cu microbumps and the following 2.5-µm-thick Sn-Ag microbumps were deposited on the thin Ti and Cu layers. The exposed thin Cu and Ti were etched out from the wafers. On the wafer for the substrates, a hydrophobic fluorocarbon layer
Capability of precise chip self-assembly with water surface tension Liquid wetting properties on the assembly site and the surrounding area on substrates are essential to precisely align chips on the assembly sites. Static contact angles of water droplets were evaluated on the both surfaces. Contact angles on the hydrophilic assembly sites were less than 30° as shown in Figure 4(a). In contrast, the surrounding areas of the assembly sites rendered hydrophobic by fluorocarbon had contact angle of more than 110° as shown in Figure 4(b). These results indicate that the wetting properties of the resulting substrate are appropriate to precise self-assembly [11]. Differences of size and size variation between the chip and the assembly site also have an impact on alignment accuracies. Correlation with chip outer size and alignment
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accuracies in self-assembly were compared between chips dicing with plasma etching and with standard blade dicer. High alignment accuracies are expected with the chips and substrates fabricated with a high-precision process. As shown in Figure 5(a)-(b), both the resulting chips had similar chip outer size, and were precisely aligned toward the assembly sites within 2.0 µm. The alignment accuracies of 2.0 µm are eventually consistent with chip-size accuracies. In addition, Figure 5 indicates that wafer dicing with a standard saw dicer have little effect on alignment accuracy in these self-assembly experiments. Therefore, the chips with NCF/microbumps were also singulated from wafers with the standard dicer. In the blade dicing of the chips with the NCF/microbumps, the chip outer size was 2.999 mm ±2.5 µm, and the standard deviation of chip size was 1.1 µm respectively, shown as in Figure 6 (a). (a)
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Figure 4. Contact angles of water droplets (a) on the hydrophilic assembly site, and (b) on the surrounding hydrophobic area. (a)
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Figure 5. Alignment accuracies of Si chips without NCF: (a) chips singulated by plasma etching, and (b) chips singulated by standard blade dicing.
Figure 6. (a) A photograph of the chip laminated with the NCF after dicing, and (b) the magnified images of the chip surface.
Self-assembly evaluation using the chip with NCF and Cu/Sn-Ag microbumps Shortly before chip self-assembly, the bonding surfaces of the substrates were treated with 172-nm-wavelength excimer lamp irradiation for 4.5 sec to remove contamination and enhance water wettability on the assembly sites. A selfassembly scholar robot developed for the multichip-to-wafer 3D integration was utilized to supply liquid droplets and to sort and supply chips onto the assembly sites. The positioning reproducibility of the robotic was approximately 100 µm, which was high enough to precisely align the chips on assembly sites formed on the corresponding substrates by water surface tension. Figure 7 shows self-assembly flow and photographs for chips in each step. A 0.4 μl droplet of ultrapure water was supplied onto hydrophilic assembly sites on the substrates. The chips were pre-aligned to the assembly sites in a facedown manner using an image-recognition function of the robot, and then the chips were kept in contact with the droplet. After that, the chips were released out from the vacuum tweezer, and finally, the chips were immediately self-aligned to the assembly sites by water surface tension. In Figure 7, the chip was released from 500 µm initial offset position along xaxis, and was self-aligned within 0.3 sec. The alignment accuracies were evaluated with vernier scales on the selfassembled chip and the substrate with an IR microscope, as shown in Figure 8.
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(a)
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Figure 9. Side views of self-assembling chips to substrates with initial offsets of (a) 100 µm, (b) 500 µm, and (c) 1500 µm.
There were some differences between alignment accuracies of chips with NCF in Figure 10(a) and without the NCF in Figure 5(b). The difference was derived mainly from chip-size variations, NCF delamination, and small deformation of the NCF due to its viscoelastic property and stress derived from mechanical dicing. Figure 6(b) shows magnified images of the chip edges after blade dicing. The deformations of 3.0 µm width were observed on the edges of the NCF. Therefore, the alignment accuracy of the worst 3.0 µm would just result from NCF deformation and delamination. However, NCF deformation and delamination protruding inward from the chip edge would have little influence on the chip alignment, because the chip outer sizes were not changed.
Figure 7. Self-assembly behavior of a NCF-covered chip released with an initial offset of 500 µm.
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Figure 8. IR microscopic overlap images of the 3-mm square chip and the substrate after self-assembly.
The impact of initial offset along x-axis prior to chip release on alignment accuracies was investigated in this work. Figure 9 shows self-alignment behaviors of the chips released from initial offsets in 100 µm, 500 µm, and 1500 µm. The NCF-covered chips with the initial offsets were also spontaneously self-aligned by water surface tension. Figure 10 shows alignment accuracies of chips released from initial offset in 0 µm to 1500 µm. The chips with the NCFs can be precisely assembled toward the corresponding assembly sites. In all conditions, most chips can be precisely self-aligned with alignment accuracies within 3.0 µm. With even 1.5-mm initial offset, the alignment accuracies were equivalent to that of chips released from other smaller initial offsets, as shown in Figure 9(c), 10(a) and (e). In Figure 10, the assembly accuracies were 1.5 µm on average and 2.9 µm at worst, and the total accuracy variation were below 0.7 µm.
Figure 10. (a) Alignment accuracies of NCF-covered chips with microbumps, and the resulting IR images of alignment marks on the self-assembled chip with initial offsets of (b) 0 µm, (c) 100 µm, (d) 500 µm, and (e) 1500 µm. Scale bars in (b)-(e): 10 µm.
Thermal compression bonding of Cu/Sn-Ag microbumps and underfilling after self-assembly After the chips are self-aligned to assembly sites on the substrates by water surface tension and the subsequent evaporation of water, Cu/Sn-Ag microbump interconnections between the chips with the NCFs and the substrates were obtained by thermal compression. The chips with alignment accuracies below 2.0 µm were evaluated in this section. Here,
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the self-assembled chips were thermally compressed in the chip-level processing using flip-chip bonder (FC3000, Toray). It is noted that chip alignment function of the flip-chip bonder was not employed. After optimization of bonding conditions such as temperature and load, the chips self-assembled on the substrate were bonded under the temperature and load profiles, as described in Figure 11.
characteristics with contact resistances of 57 mΩ/joints or below without bridge short and open failures. Good electrical connection of Cu/Sn-Ag microbumps through the NCF was obtained.
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Figure 11. Bonding temperature and load profiles during thermal compression for chips after self-assembly the flipchip bonder (chips are self-assembled on the substrates).
Figure 12 (a) and (b) show the plots of alignment accuracies and IR images of alignment marks before and after NCF bonding, respectively. After NCF bonding, chip alignment accuracy were 1.5 µm on average and 3.4 µm at worst. And, such a small decrease in alignment accuracies after thermal compression would be attribute to chip sliding on the substrate owing some tiny tilts, which would be derived from variations of the NCF thickness, the microbump height, and the bonder head planarity. (a)
Figure 13. Cross-sectional images of (a) microbumps before self-assembly, and (b) microbump joints between the upper chip and lower substrate.
(b)
Figure 14. I-V characteristics of daisy chain with Cu/Sn-Ag microbump through NCF.
Figure 12. (a) Alignment accuracies of chips, and (b) IR images of alignment marks before and after NCF bonding. Scale bar in (b): 10 µm.
Conclusions
Figure 13 shows cross-sectional images of microbumps before bonding and bonding interfaces after bonding. The gaps retained by Cu microbumps between the chip and the substrate were above 10 µm without electrically shorted solder bridges and bonding failures. The gaps were filled with the NCF material. I-V characteristics were measured using the daisy chain patterns interconnected through Cu/Sn-Ag microbump joints. The electrical characteristics were measured using a 4-terminal probe on substrates. Figure 14 shows the obtained I-V curves. The daisy chains including 5,000 joints of microbumps showed good electrical
Chips with Cu/Sn-Ag microbumps covered by the NCF were successfully self-assembled onto substrates with the corresponding Cu/Sn-Ag microbumps. The alignment accuracies were found to be 1.4 m on average. Although the chips were fabricated with a standard blade dicing, the chip outer size and the size variation had less influence on the alignment accuracy in self-assembly using chips having Cu/Sn-Ag microbumps with a size/pitch of 10/30 µm. In the subsequent thermal compression process, Cu/Sn-Ag microbumps on the chips and the substrates were electrically connected through the NCF, and good electrical properties
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with contact resistances of 57 mΩ/joints were obtained. By applying a series of direct multichip-on-wafer 3D stacking including pre-underfilling, self-assembly of NCF-covered chips, and thermal compression in wafer-level batch processing, highly-integrated 3D and hetero systems would be realized. Acknowledgments This work was performed at Micro/Nano-Machining Research and Education Center (MNC) and Jun-ichi Nishizawa Research Center at Tohoku University. This work was also performed at Global INTegration Initiative (GINTI) in Tohoku University, Japan. We would like to acknowledge DISCO CORPORATION for supporting implementation of wafer dicing. This research was supported by Japan Society for the Promotion of Science (JSPS), Grant-in-Aid for Scientific Research "Grant-in-Aid for Scientific Research (S)", No. 21226009. We would like to acknowledge Sumitomo Bakelite Co.,Ltd., for their material support in this work.
13. T. Fukushima, Y. Ohara, M. Murugesan, J.-C. Bea, K.W. Lee, T. Tanaka, and M. Koyanagi: Proc. 61st Electron Components Technology Conf. (ECTC), 2011, p. 205 14. T. Fukushima, E. Iwata, Y. Ohara, M. Murugesan, J.-C. Bea, K.-W. Lee, T. Tanaka, and M. Koyanagi: IEEE Trans. Electron Devices 59 (2012) 2956 15. Y. Ito, T. Fukushima, K.-W. Lee, K. Choki, T. Tanaka, and M. Koyanagi, Jpn. J. Appl. Phys. 52 (2013) 04CB09. 16. Y. Ito, T. Fukushima, K.-W. Lee, K. Choki, T. Tanaka, and M. Koyanagi, Proc. 63rd Electron Components Technology Conf. (ECTC), 2013, p. 891
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