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IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 11, NOVEMBER 2000
Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric Yee Chia Yeo, Student Member, IEEE, Qiang Lu, Wen Chin Lee, Member, IEEE, Tsu-Jae King, Member, IEEE, Chenming Hu, Fellow, IEEE, Xiewen Wang, Member, IEEE, Xin Guo, and T. P. Ma, Fellow, IEEE
Abstract—We present a study on the characterization and modeling of direct tunneling gate leakage current in both Nand P-type MOSFETs with ultrathin silicon nitride (Si3 N4 ) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms were extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si3 N4 gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.
model [6]. The electron and hole tunneling masses and barrier potentials for different tunneling mechanisms (Fig. 1(a)) such as electron tunneling from conduction band (ECB) and hole tunneling from valence band (HVB) were extracted from transistors with JVD Si N gate dielectric. II. THEORETICAL MODEL It has been shown that the direct tunneling gate current through SiO in CMOS transistors can be accurately described by a semi-empirical model [6]. This model, as given by [6]
Index Terms—CMOSFET, dielectric materials, direct tunneling, leakage current, silicon nitride.
I. INTRODUCTION
A
GGRESSIVE scaling of CMOS technology in recent years has reduced the SiO gate dielectric thickness below 30 Å [1]. Major causes for concern in further reduction of oxide thickness include increased polysilicon (poly-Si) gate depletion, boron penetration into the channel region, and high direct tunneling gate leakage current which leads to questions regarding dielectric integrity, reliability, and standby power consumption. As a result, there is immense interest in alternative gate dielectrics with higher relative permittivities . For a , using a higher- gate given equivalent oxide thickness dielectric and a physical thickness larger by a factor achieves significant suppression of direct tunneling gate current. Silicon 7.8) [2] has been intensively investigated nitride (Si N , as the first post-SiO gate dielectric due to its compatibility with conventional CMOS processes. Despite its growing importance, there has been relatively little modeling work done on the direct tunneling current through ultrathin Si N [3] in comparison to SiO [4], [5]. In this work, we examine the direct tunneling leakage currents through ultrathin Si N gate dielectric in both N- and P-type transistors using an analytical Manuscript received May 25, 2000. This work was supported by the SRC/SEMATECH Center for Front-End Processing under Contract 98-BC-616. The work of Y. C. Yeo was supported by a NUS Fellowship. The review of this letter was arranged by Editor S. Kawamura. Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail:
[email protected]). X. Wang and T. P. Ma are with the Department of Electrical Engineering, Yale University, New Haven, CT 06520 USA. W. C. Lee was with the Department of the Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. He is now with Intel Corporation, Hillsboro, OR 97124 USA. X. Guo was with the Department of Electrical Engineering, Yale University, New Haven, CT 06520 USA. He is now with Advanced Micro Devices, Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0741-3106(00)09273-9.
(1) is used to describe the gate current through ultrathin Si N in this work, where electronic charge; Planck’s constant; dielectric permittivity of Si N ; physical thickness of Si N ; tunneling barrier height in eV; carrier effective mass; voltage across the dielectric; electric field in the dielectric; ( ECB or HVB) indexes the tunneling mechanism. Equation (1) is similar to the direct tunneling model presented in [5] which is based on the Wentzel-Kramers-Brillouin (WKB) approximation and assumed independent and elastic electron processes with a one-band parabolic dispersion relation. The main difference between the models in [5] and [6] is the correction factor
(2) is a fitting parameter, and is the Si/Si N where band-offset equal to 2.10 eV for conduction band (used for and 1.90 eV for valence band (used for [7]. The exponential factor accounts for secondary effects such as energy dependence of the densities of states at the electrode
0741–3106/00$10.00 © 2000 IEEE
YEO et al.: DIRECT TUNNELING GATE LEAKAGE CURRENT
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Fig. 2. Model gate current densities, (a) J for PMOSFET and (b) J for NMOSFET, for various Si N (solid lines) and SiO (dashed lines) gate dielectric thicknesses. Open and solid symbols plot the experimental data for Si N and SiO gate dielectrics, respectively. Measurements were done on 10 m 10 m transistors. Gate-to-source/drain junction overlap area is less than 0.2 m .
2
TABLE I MODEL PARAMETERS FOR DIRECT TUNNELING GATE LEAKAGE CURRENT THROUGH JVD Si N AND SiO Fig. 1. (a) Energy band diagrams for p poly-Si PMOS and n poly-Si NMOS structures under inversion bias. (b) Carrier separation experiment. Inset shows the electrical connections. Under inversion, two components in the gate current I (solid symbol) can be separated: the source/drain-supplied current I (open symbol; represents hole tunneling current for PMOS and electron tunneling current for NMOS), and the substrate current I (+ center; represents electron tunneling current for PMOS and hole tunneling current for NMOS). Since, I I in both cases, it is evident that J is dominant in P poly-Si PMOS and J is dominant in n poly-Si NMOS.
interface and effective masses in the dielectric, and affects the curvature of the tunneling characteristic [6]. These effects were ensures a zero at zero . neglected in [5]. The factor is density of carriers in the inversion or accumulation layer given by [6]
(3) where ; Boltzmann’s constant; absolute temperature; threshold voltage; flatband voltage; ( effective gate voltage after accounting for the voltage drop across the poly-Si depletion region. The rate of increase of the subthreshold carrier density with is dictated by ( where is the subthreshold swing) which is positive for NMOS and negative for PMOS. III. EXPERIMENTAL AND MODELING RESULTS Fig. 1(b) summarizes the results of a carrier separation experiment where the transistors were fabricated by a JVD-Si N -in-
tegrated dual-poly-Si gate CMOS process [8]. The of 1.42 nm was determined from - fitting using a numerical simulator that accounts for quantum confinement in the Si inversion layer [9]. Fig. 1(b) establishes the fact that under typical inverV), the gate current is predominantly sion biases due to tunneling from the inversion layer to the gate and is supplied from the source and drain, i.e. hole (electron) tunneling from the valence (conduction) band in the channel of the p poly-Si PMOSFET (n poly-Si NMOSFET) dominates the gate current. This statement also holds true for dual-poly-Si CMOS transistors with SiO gate dielectric [10]. Electron (hole) concentration in the p (n ) poly-Si gate is too low for gate-to-substrate electron (hole) tunneling to have any significant contribution to . Therefore, P- and NMOSFET gate currents under and reinversion bias are accurately modeled by spectively. Fig. 2 demonstrates the good agreement between the model (solid lines for Si N and dashed lines for SiO ) and experimental data (open symbols for Si N and solid symbols for SiO ). Model parameters for Si N are summarized in Table I. The Si/Si N band-offsets and the electron effective mass for are taken from [7], which were extracted from has not been reported JVD Si N . The effective mass for in this work. The in the literature, and is extracted to be
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IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 11, NOVEMBER 2000
performance transistors could take place as early as the gate length is scaled to 100 nm (year 2001) if the most aggressive is used, or the latest by the time the gate length is scaled to 70 nm (year 2004). By adopting Si N as the gate dielectric, in high performance transistors Fig. 3 indicates that the can be scaled to as thin as 0.65 nm at the 50-nm technology is 32 nm, assuming that is 0.6 V (the node where higher value of the 0.5–0.6 V range [1]) and that a physical thickness of 1.3 nm is practically achievable. For low-power applications where the gate leakage requirements are more stringent (exactly three orders of magnitude lower than those of high performance transistors for all LG [1]), JVD Si N can be 1.13 nm at the 70 nm technology node where scaled to is 45 nm and is 0.9 V (the lower value of the 0.9 to 1.2 V range [1]). Fig. 3. Scaling limit of the JVD Si N gate dielectric is explored by examining the gate leakage current as a function of equivalent effective physical SiO thickness at various supply voltages. The International Technology Roadmap for Semiconductors (ITRS) [1] has two sets of gate leakage requirements, with the limit for low-power application lower than that for high-performance application by exactly three orders of magnitude. Only the limit for high-performance transistors are indicated here as horizontal lines. Lateral extent of these horizontal lines represents the recommended range of t to be used for the indicated gate length L (or year). The gray regions indicate possible values of the maximum gate leakage current corresponding to the range of V used. Open symbols are experimental data, solid symbols are simulation data from [4].
fitting parameter of 1.0 and 0.4 gave the best fit for and , respectively. SiO model parameters from [6] are shown for comparison. An important difference between the direct tunneling gate current through SiO and Si N should be noted. It is known that under inversion bias, tunneling current through SiO is substantially lower in the p poly-Si PMOSFET dominant) than in the n poly-Si NMOSFET dominant) (4.5 eV) being [10]. This is due to the barrier height for (3.1 eV) in the SiO /Si significantly larger than that for system. With Si N as the gate dielectric, the barrier height and (1.90 eV and , respectively) are effective mass for (2.10 eV and respectively). lower than those for Consequently, the gate current in the Si N /Si system is higher dominant) than in n poly-Si in p poly-Si PMOSFET dominant). This suggests that the JVD NMOSFET Si N scaling limit due to excessive tunneling leakage current will be first reached for PMOSFET, contrary to the observation for SiO [10]. We note that issues such as reliability, interfacial quality, and effective carrier mobility should also be considered in dielectric scaling, and these are currently under investigation. The scalability of JVD Si N is explored based on gate leakage considerations in Fig. 3. Gate currents taken from PMOSFET for Si N and NMOSFET for SiO are plotted as a function at various supply voltages . The gray regions of indicate the possible values of the maximum gate leakage to be used for current corresponding to the range of each technology. The maximum tolerable high performance is denoted by a transistor gate leakage for each gate length horizontal line, the lateral extent of which represents the range recommended for each [1]. The plot suggests of that the replacement of SiO with Si N or oxynitride in high
IV. CONCLUSION The direct tunneling gate currents through Si N in both Nand PMOSFETs were examined using an analytical model. Excellent agreement between model and experimental data was observed. Important differences between Si N and SiO paof JVD rameters were highlighted. It is projected that the Si N gate dielectric can be scaled down to 0.65 nm and 1.13 nm for high-performance and low-power applications respectively before it is limited by excessive tunneling gate leakage current. ACKNOWLEDGMENT The CMOS fabrication process was done at the Microfabrication Laboratory, University of California, Berkeley, except for the gate dielectric deposition, which was done at Yale University, New Haven, CT. REFERENCES [1] [2] [3] [4]
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International Technology Roadmap for Semiconductors—Front-End Processes, Semiconduct. Ind. Assoc., 1999. T. P. Ma, “Making silicon nitride film a viable gate dielectric,” IEEE Trans. Electron Devices, vol. 45, pp. 680–690, Mar. 1998. X. Guo and T. P. Ma, “Tunneling leakage current in oxynitride: Dependence on oxygen/nitrogen content,” IEEE Electron Device Lett., vol. 19, pp. 207–209, June 1998. S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s,” IEEE Electron Device Lett., vol. 18, pp. 209–211, May 1997. K. F. Schuegraf and C. Hu, “Hole injection SiO breakdown model for very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices, vol. 41, pp. 761–767, May 1994. W.-C. Lee and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” in Proc. Symp. VLSI Technology, Dig. Tech. Papers, W.-C. Lee, Ed.. Berkeley, CA, June 2000, pp. 198–199. Y. Shi, X. Wang, and T.-P. Ma, “Electrical properties of high-quality ultrathin nitride/oxide stack dielectrics,” IEEE Trans. Electron Devices, vol. 46, pp. 362–368, Feb. 1999. Q. Lu et al., “Comparison of 14 Å t JVD and RTCVD silicon nitride gate dielectrics for sub-100 nm MOSFETs,” in Proc. Int. Semiconductor Device Research Symp., Dec. 1999, pp. 489–492. K. Yang, Y.-C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in Symp. VLSI Technology Dig. Tech. Papers, June 1999, pp. 77–78. Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, “Polarity dependent gate tunneling currents in dual-gate CMOSFET’s,” IEEE Trans. Electron Devices, vol. 45, pp. 2355–2360, Nov. 1998.
