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Japanese Journal of Applied Physics 55, 054101 (2016) http://doi.org/10.7567/JJAP.55.054101
Effects of hole traps on the temperature dependence of current collapse in a normally-OFF gate-injection transistor Kenichiro Tanaka*, Hidekazu Umeda, Hidetoshi Ishida, Masahiro Ishida, and Tetsuzo Ueda Green Autonomous Technology Development Center, Engineering Division, Automotive and Industrial Systems Company, Panasonic Corporation, Nagaokakyo, Kyoto 617-8520, Japan *E-mail:
[email protected] Received December 5, 2015; accepted February 12, 2016; published online April 6, 2016 Kinetic studies on the current collapse of a normally-OFF AlGaN/GaN heterostructure gate-injection transistor (GIT) subject to current collapse have been performed above room temperature. The current collapse becomes more severe as the temperature increases, for which we clarified the physical mechanism based on a device simulation study that the hole traps in the epilayer play an important role. As the temperature increases, hole emission from the hole traps is stimulated, which causes sharper potential bending on the drain side in the OFF state, leading to more severe current collapse. The detailed dynamics of holes and the resultant energy profiles in the switching are discussed. © 2016 The Japan Society of Applied Physics
1.
1.4 1.6
Introduction
Transistors using wide-bandgap semiconductors such as GaN, SiC, and diamond have been under intensive study over several decades because they sustain higher breakdown voltages and can be operated at higher temperatures than conventional Si transistors. Among them, GaN transistors have been one of the most promising devices for the industry; thus, there has been a tremendous amount of reseach on them.1–5) However, it is well known for GaN transistors that the so-called current collapse deteriorates the switching performance.6–8) Here, current collapse is a phenomenon where the ON-state drain current is decreased once a high drain voltage is applied in the OFF state. Current collapse has been a critical issue for GaN transistors, in spite of numerous technical breakthroughts.6–15) To suppress current collapse, it is important to understand its physical mechanism. We previously reported that current collapse becomes more severe as the temperature increases for a GaN-based normallyOFF gate-injection transistor (GIT) subject to severe current collapse, for which we proposed a mechanism in which the capture and emission of electrons are involved.16) On the other hand, Ohno et al. reported that deep hole traps in the GaN epilayer play an important role in the current collapse phonemona.17) Following their work, we reexamined our experimental results and found that the increasingly severe current collapse in a GIT at elevated temperatures can be explained well by the model of Ohno et al. In this article, we report the detailed mechanism for the increasingly severe current collapse at higher temperatures and the carrier dynamics in the switching of a GIT subjected to current collapse. 2.
Experimental procedure
The device employed in this study consists of an AlGaN= GaN heteroepitaxial structure with an AlGaN buffer layer, as shown in Fig. 1.18) Here, deep traps are heavily doped during the metalorganic chemical vapor deposition (MOCVD) growth of the AlGaN buffer layer to suppress the leakage current because the deep traps compensate the shallow donors, making the AlGaN buffer layer semi-insulating. On the other hand, the deep trap density is lower in the GaN layer and AlGaN barrier layer than in the AlGaN buffer layer
7.5
1.0 gate
pGaN
source Al0.2Ga0.8N
0.02 GaN (0,0)
0.05
NDA=5 × 1016, NSD=1 × 1016cm−3
0.75
DA (Deep Acceptor) EV+0.67eV, 1 × 1018/cm3 SD (Shallow Donor) EC−0.01eV, 5 × 1017/cm3
Al0.05Ga0.95N Buffer p-Si substrate
drain
NDA=5 × 1016, NSD=1 × 1016cm−3
X
5.0
Y
Fig. 1. Schematic cross section of GIT. The device dimensions are indicated in µm. Energy levels and concentrations of traps employed in the simulation are shown.
because if deep traps are heavily doped near the channel at the interface between the AlGaN barrier layer and GaN layer, severe current collapse is observed. A p-GaN gate is formed on the undoped AlGaN=GaN heterostructure18) so as to realize normally-OFF operation. The threshold voltage is controlled by the thickness of the AlGaN barrier layer beneath the p-GaN layer. Here, the thickness of the recessed region of the AlGaN barrier layer underneath the pGaN gate is approximately 20 nm. The static characteristics of the device are shown in Fig. 2 in our previous work,16) where the threshold voltage of the GIT is 1.0 V.16) To investigate the trap dynamics causing the current collapse, we perform OFF–ON and ON–OFF–ON switching measurements with the electric circuit shown in Fig. 2(a).16) Here the Si substrate of the GIT is grounded. We apply a fixed voltage VDD of 130 V to the drain with an external resistance of 40 kΩ (RDD). Figure 2(b) illustrates the experimental procedure of the OFF–ON switching. After the device is maintained in the OFF state (VGS = 0 V, where VGS is the gate-to-source voltage) for 150 s, the gate voltage is switched to the ON state (VGS = 3.5 V), and the temporal ON-state VDS after the switching is measured with an oscilloscope. The VDS transient curve is expected to indicate the capture and emission processes of the traps.
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(b) VGS VDS
Vdd
~ ~
ΔVDS (t , T ) = A(T ) ⋅ e
A(T )
(d)
tp
−
β (T )
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tp
Fig. 2. (Color online) (a) Experimental setup. (b) Experimental procedure for OFF–ON switching. (c) Experimental setup for ON–OFF–ON switching. t¼100s (d) Schematic illustration of V DS as a function of OFF duration tp. Parameters are explained in the text.
4
(c)
16
log (τONT2) [s⋅K2]
~ ~ ~ ~
VDS(t=100μs)/VDS(t=100s)
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ΔEON=0.67eV
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Temperature (°C)
The measured temporal ON-state VDS ðt; TÞ can be fitted with the stretched exponential function19,20) described as ( ðTÞ ) t VDS ðt; TÞ ¼ V0 ðTÞ þ AðTÞ exp ; ð1Þ ON ðTÞ where 0 ≤ β ≤ 1. Here, the device is switched from the OFF state to the ON state at the instant t = 0 at the temperature T; τON is the characteristic time constant of VDS ðt; TÞ decay and β(T ) is the decay exponent. The value of V0(T ) corresponds to VDS ðt; TÞ at t = ∞ (i.e., VDS when the device is free from current collapse), which increases as the temperature increases because the ON-state resistance increases with the temperature. This is because a higher temperature decreases the mobility in the channel.21,22) The value of A(T ) describes the increase in VDS caused by the current collapse. The physical meaning of β is not very clear, but it is suggested that stretched exponential decay is commonly observed in disordered systems.23–25) After τON(T ) is obtained at each temperature, the activation energy of the decay constant in the OFF–ON switching, ΔEON, is extracted from the Arrhenius plot of τON(T ). Figure 3(a) shows the temporal response of VDS at various temperatures. The obtained data are fitted with Eq. (1), and the corresponding parameters are extracted. The extracted values of β are plotted as a function of the temperature in Fig. 3(b). The ratio VDS(t = 100 µs)=VDS(t = 100 s), which denotes the magnitude of the current collapse, increases with the temperature as shown by the triangles in Fig. 3(c). The observed temperature dependence is contrary to that in a previous report,26) in which the current collapse is suppressed by the enhanced emission of trapped electrons at elevated temperatures. On the other hand, the time constant of the current collapse recovery process, τON(T ), decreases as the temperature increases. The values of log(τONT 2) are plotted as a function of the inverse of the absolute temperature T in Fig. 3(d), from which the activation energy for the recovery process ΔEON is obtained to be 0.67 eV. Figures 2(c) and 2(d) illustrate the experimental procedure of the ON–OFF–ON switching. In the ON–OFF–ON switching, after the device is maintained in the ON state
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Fig. 3. (Color online) (a) Temporal response of VDS in OFF–ON switching measured at various temperatures. (b) Temperature dependence of β. (c) Experimental VDS(t = 100 µs)=VDS(t = 100 s) as a function of the temperature. (d) Plot of log(τONT 2) as a function of the inverse of the temperature T. The solid line indicates the least-squares fit to the data.
(VGS = 3.5 V) for 150 s, it is switched to the OFF state (VGS = 0 V), which is followed by a transition to the ON state (VGS = 3.5 V), where the OFF-state duration tp is varied. The increase in VDS as a function of the OFF-state duration tp indicates how much faster the current collapse occurs in the OFF state, which gives us a clue of the trap dynamics in the OFF state. The obtained V t¼100s is fitted with the following DS expression: V t¼100s ðtp Þ ¼ V0 ðTÞ þ V t¼100s ðtp Þ DS DS ¼ V0 ðTÞ þ BðTÞ 1 exp
tp ; ð2Þ OFF ðTÞ where the instant t = 0 corresponds to the moment at which the device switches from the OFF state to the ON state. τOFF is the characteristic time constant, and B(T ) indicates the maximum increase in VDS when tp is sufficiently long. Here, we first performed the fitting using stretched functions similar to Eq. (1); however, we found that the obtained value of β is nearly 1 for all the measured temperatures, thus we simply employed the exponential form described by Eq. (2). Figure 4(a) shows the dependence of V t¼100s on tp at DS various temperatures. The obtained data are fitted well by Eq. (2), and the corresponding parameters are obtained at each temperature. Figure 4(b) shows the Arrhenius plot of log(τOFFT 2). τOFF decreases with increasing temperature, suggesting that VDS saturates at a smaller tp as the temperature increases. From the slope of log(τOFFT 2) against 1=T, the corresponding activation energy ΔEOFF is estimated to be 0.67 eV. In the next section, we simulate the experimental data by employing the trap model proposed by Ohno et al.17) 3.
Simulation
We simulate the experimental results for switching using the conventional drift-diffusion transport equations with the
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VDS (V)
Table I. Combinations of deep (high concentration) and shallow (low concentration) traps in semi-insulating layer.
125°C 110°C
Deep traps
90°C
1.4
(i)
Electron traps
Donor
Hole traps
Acceptor
(ii)
Electron traps
Acceptor
Electron traps
Donor
(iii) (iv)
Hole traps Hole traps
Donor Acceptor
Hole traps Electron traps
Acceptor Donor
1.2 60°C
1.0
40°C
0.8
25°C
0.6
Shallow traps
0.4 10-2
10-1
100
101
102
103
tp (s)
1μm
(a)
5μm
1μm
16
0V n GaN
(b) (b)
14
12
ΔEOFF=0.67eV
Semi-insulating GaN
1s
2
2s
-50 0
0
-100
(i) 0
2.8
3.0
3.2
3.4
t=0s
10s 4
2
10 2.6
n GaN
0 4
CBE (eV)
log (τOFFT2) [s⋅K2]
VD
2
Position (μm)
4
6
0 4
CBE (eV)
1000/T (1/K) Fig. 4. (Color online) (a) ON state VDS at the instant t = 100 µs as a function of the OFF duration tp at various temperatures. (b) Plot of log(τOFFT 2) as a function of the inverse of the temperature T. The solid line indicates the least-squares fit to the data.
-50
1s
2 0
0
2s
t=0s
10s 4
2
-100
(ii) 0
2
Position (μm)
4
6
CBE (eV)
0
100
-50
1s 5s
50
t=0s -100
20s
0 0 0
2
4
(iii)
4
6
2
Position (μm) 0
CBE (eV)
Shockley–Read–Hall (SRH) model of deep traps.27–29) The simulations are performed on the structure described in Fig. 1. The axis Y = 0 sits at the AlGaN=GaN interface and X = 0 is located on the right side of the gate. As in the experiment, a fixed voltage VDD of 130 V is applied to the drain with an external resistance of 40 kΩ, and the device is maintained in the OFF state for 150 s before VGS is switched from 0 to 3.5 V in 0.2 µs. As a model for the epilayers, we assume a simple two-level compensation model comprising deep and shallow traps,17) in which the deep traps compensate the shallow traps, making the epilayer semi-insulating. To make the epilayer semiinsulating, the concentration of deep traps should be higher than that of shallow traps. Also, if the deep traps are acceptortype, the shallow traps should be donor-type, and vice versa. Under such conditions, the Fermi energy is located near the deep-trap energy level, which makes the epilayer semiinsulating because both the electron and hole densities in the layer are negligibly low. In addition, there are two possibilities in terms of the traps’ energy location. One of the possibilities is that the traps’ energy is located above the midgap, and the other is that it is located below the midgap. Here, we call the traps whose energy ET is located above the midgap “electron traps”, whose charged state is determined by the electron concentration and not by the hole concentration.17) On the other hand, we call the traps whose energy ET is located below the midgap to be “hole traps”, whose charged state is determined by the hole concentration and not by the electron concentration.17) On the basis of the above trap classification, to make the epilayer semi-insulating, there are four possible combinations of the deep and shallow traps, which are summarized in Table I.
100
1s 5s
50
-50
t=0s
0
-100
0
20s
0 2 2
Position (μm)
4 4
(iv) 6
Fig. 5. (Color online) (a) One-dimensional simulation structure. Trap conditions are described in the text. (b) Simulated transient conduction band energy profiles. Here, (i)–(iv) correspond to conditions of the semi-insulating GaN layer described in Table I.
To determine the behavior of the semi-insulating layers composed of trap types (i)–(iv) in Table I, we perform the device simulation for the simple one-dimensional structure shown in Fig. 5(a), where a 5-µm-thick semi-insulating GaN layer composed of combinations of deep and shallow traps described in Table I is sandwiched by 1-µm-thick n-type GaN layers whose electron concentrations are both set to 1 × 1018=cm3. In the simulation, we assume that the deep electron traps and deep hole traps are located 0.67 eV below the conduction band edge and 0.67 eV above the valence band edge, respectively. On the other hand, we set the shallow electron traps and shallow hole traps 0.01 eV below the conduction band edge and 0.01 eV above the valence band edge, respectively. The densities of the deep traps and shallow traps are set to 1 × 1018 and 5 × 1017=cm3, respectively.
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Time (s) 5
VDS(t=100μs)/VDS(t=100s)
In the one-dimensional simulation, after we apply VD of 130 V to the structure in Fig. 5(a) for 150 s, VD is switched back to 0 V in 200 ns. Figure 5(b) shows the calculated temporal conduction band profiles in cases (i)–(iv). In Fig. 5(b), the time t is the time after VD starts to be switched from 130 to 0 V. We find that the temporal behavior of the potential profile under an electric field that causes current collapse is mainly influenced not by whether the deep traps are an acceptor or a donor, but by whether they are electron or hole traps. This is because, regardless of whether the deep traps are an acceptor or a donor, if they are electron traps, the epilayer is positively charged under a high electric field, and if they are hole traps, the epilayer is negatively charged under a high electric field. This one-dimensional simulation indicates that it is impossible to indicate whether the deep traps are an acceptor or a donor only from the switching experimental data. Although it is impossible to indicate whether the shallow traps are of the donor or acceptor type, we assume here that they are donor-type electron traps. This is because secondary ion mass spectrometry on the epilayer indicates that Si and oxygen, which are known as shallow donors in GaN crystal and whose energy is located just below the conduction band edge, are incorporated during crystal growth by MOCVD. This means that cases (ii) and (iv) in Table I are considered. Here, we do not consider cases (i) and (iii), not because they are unreasonable, but because whether the deep traps are an acceptor or a donor does not affect the switching simulation. For the deep traps, following the paper of Ohno et al.,17) we tentatively assume them to be hole traps, which corresponds to case (iv) in Table I. From the experimental results of the switching, we assume the energy of the deep traps to be 0.67 eV above the valence band edge EV (ET = EV + 0.67 eV). This value is nearly the same as that of 0.76 eV reported by Ohno et al.17) We assume that the deep traps originate from carbon,30) which is incorporated during the growth of (Al)GaN. Since we assume here that ET is located below the midgap of (Al)GaN, the traps act as hole traps. In this study, we perform the simulation assuming that the deep traps in the epilayers are hole traps (ET = EV + 0.67 eV). However, in this article, we will also present some simulation results with the assumption that the deep traps in the epilayers are electron traps (ET = EC − 0.67 eV, where EC is the energy of the conduction band edge) to verify our assumption that the deep traps are hole traps. The electron and hole capture cross sections for the deep acceptor traps are set to 1 × 10−15 and 1 × 10−14 cm2, respectively. The deep acceptor density (NDA) and shallow donor density (NSD) in each layer are summarized in Fig. 1. We set the shallow donor level to 0.01 eV below the conduction band edge. On the other hand, the trap model at the AlGaN surface is based on the disorder-induced gap state model with donor-like states below the charge neutrality level ECNL and acceptor-like states above it. For the distribution of the AlGaN surface density, we employ the values reported by Miczek et al.31) In addition to the disorder-induced gap states, we assume discrete donor-like states located 0.37 eV below the conduction band edge, which are related to nitrogen vacancies.31,32) The density of the discrete level NVN is varied to reproduce the experimental switching data to obtain NVN =
(b) 4
3
2 Sim. (ET=EV+0.67eV) Sim. (ET=EC−0.67eV) Experiment
1
0
20
40
60
80
100
120
140
Temperature (°C) Fig. 6. (Color online) (a) Simulated temporal behavior of ON state VDS at several temperatures. (b) Simulated ratios VDS(t = 100 µs)=VDS(t = 100 s) as a function of the temperature if the deep traps are hole traps (ET = EV + 0.67 eV, red solid circles) and electron traps (ET = EC − 0.67 eV, green open circles). Experimental (black triangle) ratios VDS(t = 100 µs)=VDS(t = 100 s) are also shown for comparison (black triangles).
6 × 1012=cm2. If the donor-like states are not taken into account, the experimental data for switching are not reproduced well, in which the calculated ON-state VDS in the OFF– ON switching is much larger than the experimental value. Figure 6(a) shows the simulated transient VDS curves in the OFF–ON switching. The simulated recovery time coincides with the experimental data in terms of the order of magnitude. The black triangles and red solid circles in Fig. 6(b) show the experimental and simulated ratios VDS(t = 100 µs)= VDS(t = 100 s) as a function of the temperature, respectively. The simulation reproduces the experimental results in that the current collapse becomes more severe and the recovery time is shortened as the temperature increases. On the other hand, the green open circles in Fig. 6(b) show the temperature dependence of the ratio VDS(t = 100 µs)=VDS(t = 100 s) if the deep traps are electron traps (ET = EC − 0.67 eV). The simulation does not reproduce the experimental results in that the simulated current collapse becomes less severe as the temperature increases. Figure 7 shows the simulated V t¼100s as a function DS of the OFF-state duration tp in the ON–OFF–ON switching. The experimental data showing that V t¼100s saturates in a DS smaller tp at higher temperatures is reproduced well by the simulation. Furthermore, the simulated data agree with the experimental data in terms of the order of magnitude. Accordingly, it is reasonable to discuss the physical mechanism of current collapse using the simulated results. 4.
Discussion
Figure 8 shows the simulated conduction band energy (CBE) profiles in the vicinity of the two-dimensional electron gas
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charge neutral 25°C 50°C 75°C 100°C 125°C
1.0 0.8 0.6 10-3
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10-1
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tp (s)
negatively charged region
102
Fig. 9. (Color online) Schematic potential profile and trap charge variation of GIT in gate-to-drain access region in (a) OFF and (b) ON states.
t¼100s Fig. 7. (Color online) Simulated V DS as a function of OFF-state duration tp in ON–OFF–ON switching. Gate
Drain
2.0
Conduction Band Energy (eV)
Electric Field (MV/cm)
Drain
Gate
0 -20 -40 -60 -80 -100 -120 -140 -4
Y=0.05um t= 0us 0.06us 0.08us 0.1us 0.14us 0.2us -2
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Position X (μm) Fig. 8. (Color online) Simulated conduction band profile at Y = 0.05 µm at several times t after OFF–ON switching.
(2DEG) (Y = 0.05 µm) after the GIT turns ON in the OFF– ON switching. The depth Y = 0.05 µm is chosen to describe the potential around which the electrons in the 2DEG are transported in the ON state. The mechanism of the current collapse is described schematically in Fig. 9. The application of a high VDS in the OFF state causes hole emission in the epilayer because the traps are hole traps. The emitted holes move to the gate side and are recaptured to neutralize the gate-side region. As a result, the gate–drain region is divided into two regions, one of which is a charge-neutral region on the gate side, and the other is a negatively charged region on the drain side.17) As a result, a sharp potential drop appears on the drain side in the potential profile as shown in Fig. 9. This sharp potential drop means that the electric field is concentrated at the drain-side edge. Figure 10 shows the simulated absolute electric field distribution at Y = 0.05 µm for the GIT at t = 0 and 25 °C. The simulation shows that the maximum electric field is located at the drain-side edge. The inset in Fig. 10 shows an experimental electroluminescence image taken under the OFF condition (VDS = 130 V and VGS = 0 V), which supports the simulation results. Since a certain period of time is required for the negatively charged traps to be neutralized, the sharp potential drop remains on the drain side even after the GIT turns ON. As a result, current collapse is observed. Here, we discuss the temperature dependence of the ON–OFF–ON and OFF–ON switching results based on the simulated results. Firstly, we discuss the temperature dependence of the current collapse in the ON–OFF–ON switching. The simula-
Fig. 10. (Color online) Simulated absolute electric field distribution in the vicinity of the 2DEG (Y = 0.05 µm) at t = 0. The inset shows an experimental electroluminescence image of the GIT taken under the OFF condition (VDS = 130 V and VGS = 0 V).
tion model suggests that the tp dependence of V t¼100s DS reflects the hole emission rate of the deep traps in the ON–OFF–ON switching. Thus, it is reasonable that ΔVDS saturates at a smaller tp with increasing temperature, as observed in Fig. 4, because the hole emission rate during the OFF state is stimulated by increasing the temperature. Secondly, the temperature dependence of the current collapse in the OFF–ON switching is discussed. Figure 11(a) shows the simulated CBE at Y = 0.05 µm when the device is maintained in the OFF state (VDD = 130 V) for 150 s (t = 0) at several temperatures. At higher temperatures, hole emission is stimulated in the OFF state, leading to a much sharper potential drop on the drain side. As a result, the current collapse becomes increasingly severe as the temperature increases. Here, we note that although the increase in temperature enhances the current collapse recovery as observed in the OFF–ON switching measurement, the recovery of the ON state VDS requires more than 100 µs even at 125 °C. If the temperature is further increased, we expect that the ON state VDS at 100 µs will be decreased because the ON-state VDS recovers in less 100 µs at a much higher temperature. On the other hand, Fig. 11(b) shows the simulated CBE at Y = 0.05 µm and t = 0 if the deep traps are electron traps (ET = EC − 0.67 eV). In the case of electron traps, the CBE is not sharpened by increasing the temperature, unlike the case of hole traps. This is because electron traps emit electrons in the OFF state, which do not cause a sharp potential drop on the drain side, because the electron emission does not increase the potential. Thus, the current collapse does not become more severe as the temperature is increased, as shown in Fig. 6(b). We thus believe that the increasing
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0
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Fig. 12. (Color online) Experimental transient of ON state VDS in the OFF–ON switching at various ON state gate-to-source voltages VGS.
Drain
Gate
0
(b)
-20 -40 -60 -80 -100 -120 -140 -4
Y=0.05um, t=0 25°C 50°C 75°C 100°C 125°C
-2
0
2
4
6
8
Position X (μm) Fig. 11. (Color online) Simulated conduction band profile at Y = 0.05 µm when the device is maintained in the OFF state (VDS = 130 V) for 150 s at several temperatures (a) if the deep traps are hole traps (ET = EV + 0.67 eV), and (b) if the deep traps are electron traps (ET = EC − 0.67 eV).
severity of the current collapse at higher temperatures suggests that the current collapse is caused not by electron traps but by hole traps. In fact, it is difficult to specify the location of the deep hole traps in the GIT. However, we consider the hole traps in the GaN and AlGaN epilayer to be responsible for the increasingly severe current collapse with increasing temperature because the deep traps in GaN have a similar energy to the previously reported value.30) We also find that the current collapse depends on the growth conditions of the epitaxial layers. On the basis of our conclusion that the deep hole traps are responsible for the current collapse, we have recently proposed a new device where an additional pGaN layer connected to the drain is formed to compensate the hole emission in the OFF state, which completely suppresses the current collapse.33,34) This result also supports our conclusion. The simulation model suggests that the current collapse recovery in the OFF–ON switching reflects the charge neutralization of the negatively charged deep traps formed in the OFF state. The recovery rate cp in the OFF–ON switching can be described as ET EV cp ¼ vp ¼ vp NV exp ; ð3Þ kB T where p, NV, vp, σ, EV, and kB are the hole density, the effective density of states in the valence band, the thermal velocity of holes, the hole capture cross section of the traps, valence band energy, and the Boltzmann constant, respectively.27) Since cp increases with the temperature due to the exponential component in Eq. (3), the recovery process is enhanced at elevated temperatures.
Here, we assume three possibilities for the charge neutralization of the negatively charged traps, which is responsible for the current collapse recovery in the OFF–ON switching: (1) the emission of electrons from the deep traps, (2) the capture of holes injected from the substrate, and (3) the capture of the holes injected from the gate. Among them, we rule out the first possibility of the emission of electrons from the deep acceptor traps because their trap energy is located about 2.7 eV below the conduction band edge, indicating that the emission rate of electrons to the conduction band is negligibly low.17) We also rule out the second possibility of the capture of holes injected from the substrate because we observe that the OFF–ON switching is the same as that measured with the substrate floating.28) If the holes from the substrate play an important role in the OFF–ON switching, the recovery from the current collapse will be slower when the substrate is floating. We thus expect that the third possibility will be the most promising i.e., the current collapse recovery will be caused by the capture of holes from the gate. Figure 12 shows the experimental temporal response of the ON state VDS after OFF–ON switching as a function of the ON state VGS. We find that the experimental current collapse recovery is accelerated by increasing the ON state VGS, suggesting that hole injection from the p-GaN gate enhances the current collapse recovery. We thus conclude that the p-GaN gate, which is formed so as to make the GIT perform the normally-OFF operation, plays an important role in enhancing the current collapse recovery. Let us examine in more detail how the holes injected from the gate cause the recovery from current collapse in the OFF– ON switching. Figure 13(a) shows the simulated conduction and valence band profiles at 25 °C during the OFF–ON switching as a function of the position Y at the intersection where X = 5 µm. The corresponding schematic cross section of the GIT is shown in Fig. 13(b). Before the OFF–ON switching, the high VDS applied during the OFF state induces hole emission in the buffer layer and a subsequent increase in the potential energy of the buffer layer. After the GIT turns ON, the CBE is decreased gradually to be nearly flat after 10 s. Until then, the potential profiles in the buffer layer exhibit two negatively charged peaks at both ends of the buffer layer, toward which the injected or emitted holes are accumulated. The accumulated holes lower the potential profiles gradually. This behavior is the same as the “halfrecovery” process reported by Ohno et al.17) In particular, holes accumulate at the GaN=buffer interface because the
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potential at the interface is increased in the OFF state and the valence band discontinuity between the GaN and the AlGaN buffer induces hole accumulation on the AlGaN buffer side of the interface. The simulation suggests that the potential peak located at the GaN=buffer interface [see Fig. 13(a)] recovers faster than that located at the bottom of the buffer layer because the injected holes from the gate flow from the channel side and lower the potential around the GaN=buffer interface more effectively. Figure 13(c) shows that the temporal behavior of the ON-state VDS coincides with that of the CBE at the position ð5; 0:75Þ, indicating that the switching behavior reflects the CBE at the GaN=buffer interface. On the basis of the above discussion, the recovery process of the current collapse is summarized in Fig. 14. In the OFF state, the buffer layer emits holes and a negatively charged region is formed around the GaN=buffer interface as shown in Fig. 14(a). After the GIT turns ON, the holes injected from the gate move to the negatively charged region in the buffer, because its potential is higher. Thereby, the negatively charged region is neutralized, as shown in Fig. 14(b), where the potential at the GaN=buffer interface is recovered mainly by holes as indicated by the bold arrow. Finally, the neutralization of the buffer layer lowers the potential at the 2DEG via the capacitance of the GaN channel [indicated as “C” in Fig. 14(b)], leading to the current collapse recovery. Although this recovery process is similar to that reported for a GaAs transistor by Nogome et al.,35) it is different in that the injected holes from the pGaN gate are responsible for the current collapse recovery in the case of the GIT. 5.
D
Conclusions
We investigated the switching characteristics of a normallyOFF AlGaN=GaN heterostructure gate-injection transistor (GIT) at elevated temperatures. In the OFF–ON switching, we found that current collapse became increasingly severe as the temperature increased, contrary to a past report that the
Fig. 14. (Color online) Schematic of potential profile and trap charge variation of GIT in (a) OFF and (b) ON states.
ON state resistance is suppressed at high temperatures.26) This seemingly anomalous result is explained well by assuming hole traps whose energy is located 0.67 eV above the valence band edge, where the hole emission stimulated at high temperatures causes sharper energy band bending on the drain side in the OFF state. The current collapse recovery process was discussed in detail on the basis of the simulated results. The injected holes from the p-GaN gate when the GIT turns ON move to the GaN=buffer interface, whose energy is increased in the OFF state, leading to the enhancement of the current collapse recovery. The p-GaN gate, which is formed to make the GIT perform the normally-OFF operation, also plays an important role in accelerating the current collapse recovery.
1) H. Morkoç, S. Strite, G. B. Gao, M. E. Lin, B. Sverdlov, and M. Burns, J. Appl. Phys. 76, 1363 (1994). 2) M. A. Khan, Q. Chen, M. S. Shur, B. T. Mcdermott, and J. A. Higgins, IEEE Electron Device Lett. 17, 325 (1996). 3) Y. F. Wu, B. P. Keller, D. Kapolnek, P. Kozodoy, S. P. DenBaars, and U. K. Mishra, Appl. Phys. Lett. 69, 1438 (1996). 4) D. Ueda, T. Murata, M. Hikita, S. Nakazawa, M. Kuroda, H. Ishida, M. Yanagihara, K. Inoue, T. Ueda, Y. Uemoto, T. Tanaka, and T. Egawa, IEDM Tech. Dig., 2005, p. 377. 5) S. Yoshida and J. Suzuki, Jpn. J. Appl. Phys. 37, L482 (1998). 6) S. C. Binari, K. Ikossi, J. A. Roussos, W. Kruppa, D. Park, H. B. Dietrich, D. D. Koleske, A. E. Wickenden, and R. L. Henry, IEEE Trans. Electron Devices 48, 465 (2001). 7) A. F. M. Anwar, S. S. Islam, and R. T. Webster, Appl. Phys. Lett. 84, 1970 (2004). 8) T. Mizutani, Y. Ohno, M. Akita, S. Kishimoto, and K. Maezawa, IEEE Trans. Electron Devices 50, 2015 (2003). 9) H. Kim, R. M. Thompson, V. Tilak, T. R. Prunty, J. R. Shealy, and L. F. Eastman, IEEE Electron Device Lett. 24, 421 (2003). 10) P. B. Klein, S. C. Binari, K. Ikossi, A. E. Wickenden, D. D. Koleske, and R. L. Henry, Appl. Phys. Lett. 79, 3527 (2001). 11) P. Kordoš, J. Bernát, M. Marso, H. Lüth, F. Rampazzo, G. Tamiazzo, R. Pierobon, and G. Meneghesso, Appl. Phys. Lett. 86, 253511 (2005). 12) W. D. Hu, X. S. Chen, F. Yin, J. B. Zhang, and W. Lu, J. Appl. Phys. 105, 084502 (2009). 13) W. Saito, T. Nitta, Y. Kakiuchi, Y. Saito, K. Tsuda, I. Omura, and M. Yamaguchi, IEEE Trans. Electron Devices 54, 1825 (2007). 14) A. Nakajima, Y. Sumida, M. H. Dhyani, H. Kawai, and E. M. Sankara Narayanan, IEEE Electron Device Lett. 32, 542 (2011).
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K. Tanaka et al.
15) T. Hashizume, S. Ootomo, S. Oyama, M. Konishi, and H. Hasegawa, J. Vac. Sci. Technol. B 19, 1675 (2001). 16) K. Tanaka, M. Ishida, T. Ueda, and T. Tanaka, Jpn. J. Appl. Phys. 52, 04CF07 (2013). 17) Y. Ohno, Y. Kio, Y. Ikawa, and J.-P. Ao, Jpn. J. Appl. Phys. 52, 08JN28 (2013). 18) Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, and D. Ueda, IEEE Trans. Electron Devices 54, 3393 (2007). 19) G. Meneghesso, M. Meneghini, D. Bisi, I. Rossetto, A. Cester, U. K. Mishra, and E. Zanoni, Semicond. Sci. Technol. 28, 074021 (2013). 20) D. Bisi, M. Meneghini, C. de Santi, A. Chini, M. Dammann, P. Brückner, M. Mikulla, G. Meneghesso, and E. Zanoni, IEEE Trans. Electron Devices 60, 3166 (2013). 21) I. P. Smorchkova, C. R. Elsass, J. P. Ibbetson, R. Vetury, B. Heying, P. Fini, E. Haus, S. P. DenBaars, J. S. Speck, and U. K. Mishra, J. Appl. Phys. 86, 4520 (1999). 22) M. N. Gurusinghe, S. K. Davidsson, and T. G. Andersson, Phys. Rev. B 72, 045316 (2005). 23) E. Arslan, S. Bütün, S. B. Lisesivdin, M. Kasap, S. Ozcelik, and E. Ozbay, J. Appl. Phys. 103, 103701 (2008). 24) J. Z. Li, J. Y. Lin, H. X. Jiang, M. Asif Khan, and Q. Chen, J. Appl. Phys. 82, 1227 (1997).
25) H. M. Chen, Y. F. Chen, M. C. Lee, and M. S. Feng, J. Appl. Phys. 82, 899 (1997). 26) C. S. Oh, C. J. Youn, G. M. Yang, K. Y. Lim, and J. W. Yang, Appl. Phys. Lett. 86, 012106 (2005). 27) W. Shockley and W. T. Read, Jr., Phys. Rev. 87, 835 (1952). 28) M. Nogome, K. Kunihiro, and Y. Ohno, Solid-State Electron. 41, 423 (1997). 29) K. Horio, K. Yonemoto, H. Takayanagi, and H. Nakano, J. Appl. Phys. 98, 124502 (2005). 30) T. Ogino and M. Aoki, Jpn. J. Appl. Phys. 19, 2395 (1980). 31) M. Miczek, C. Mizue, T. Hashizume, and B. Adamowicz, J. Appl. Phys. 103, 104510 (2008). 32) J. Kotani, S. Kasasi, T. Hashizume, and H. Hasegawa, J. Vac. Sci. Technol. 23, 1799 (2005). 33) K. Tanaka, T. Morita, H. Umeda, S. Kaneko, M. Kuroda, A. Ikoshi, H. Yamagiwa, H. Okita, M. Hikita, M. Yanagihara, Y. Uemoto, S. Takahashi, H. Ueno, H. Ishida, M. Ishida, and T. Ueda, Appl. Phys. Lett. 107, 163502 (2015). 34) S. Kaneko, M. Kuroda, M. Yanagihara, A. Ikoshi, H. Okita, T. Morita, K. Tanaka, M. Hikita, Y. Uemoto, S. Takahashi, and T. Ueda, Proc. Int. Symp. Power Semiconductor Devices and ICs, 2015, p. 41. 35) M. Nogome, K. Kunihiro, and Y. Ohno, Solid-State Electron. 42, 73 (1998).
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