A New ZVS DC/DC Converter With Three APWM Circuits - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 10, OCTOBER 2013

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A New ZVS DC/DC Converter With Three APWM Circuits Bor-Ren Lin, Senior Member, IEEE, and Chia-Hung Chao

Abstract—This paper presents a new soft-switching dc/dc converter with series-connected transformers to implement the features of zero-voltage switching (ZVS), load current sharing, low voltage stress for MOSFETs, and low current rating for the rectifier diodes and the output inductors. The proposed converter includes two half-bridge circuits connected in series to limit the voltage stress of MOSFETs at one-half of the input voltage. The output sides of the two circuits are connected in parallel to reduce the current rating on the rectifier diodes and the output inductors and to achieve load current sharing. In order to balance two output inductor currents, series-connected transformers at the low-voltage side are adopted. Thus, the output power is equally distributed by the two half-bridge circuits. The output capacitances of MOSFETs and the resonant inductances are resonant at the transition instant such that MOSFETs can be turned on at ZVS. Finally, experiments based on a laboratory prototype with 1-kW rated power are provided to demonstrate the performance of the proposed converter. Index Terms—Power converters, power electronics.

I. I NTRODUCTION

P

OWER FACTOR corrections (PFCs) have been widely used in modern power converters to compensate the reactive power and eliminate the ac current harmonics at the utility side. For a three-phase 380-V PFC converter or a single-phase PFC converter with wide input voltage range in South Africa or India, the dc bus voltage may be greater than 600 V. Therefore, MOSFETs with 600-V voltage stress and low turn-on resistance cannot be used in the rear dc/dc stage. Although high-voltage MOSFETs such as those with 900-V voltage stress can be used in the rear dc/dc converter, the disadvantages of highvoltage MOSFETs are high cost and large turn-on resistance. To overcome the voltage limitation of MOSFETs, three-level dc/dc converters [1]–[7] have been proposed. By using more MOSFETs, split capacitors, and clamp diodes, the voltage stress of each MOSFET can be reduced to one-half of the dc bus voltage. Therefore, MOSFETs with 600-V voltage stress can be used in the rear dc/dc converter for high-input-voltage applications. A phase-shift pulsewidth-modulation (PWM) IC Manuscript received May 1, 2012; revised August 5, 2012 and August 18, 2012; accepted August 24, 2012. Date of publication September 7, 2012; date of current version May 16, 2013. B.-R. Lin is with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou 640, Taiwan (e-mail: [email protected]). C.-H. Chao is with the Graduate School of Engineering Science and Technology, National Yunlin University of Science and Technology, Douliou 640, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2217722

was normally adopted to generate four PWM signals for power switches with zero-voltage switching (ZVS) turn-on at the designed load range. A center-tapped rectifier or a diode bridge rectifier is adopted in the secondary side for low- or highvoltage applications. Compared to two-level converters, threelevel converters have more circuit components and high cost. Soft-switching techniques [5], [8]–[14] have been developed and proposed for the past 20 years to reduce switching losses and increase circuit efficiency. This paper presents a new soft-switching dc/dc converter for high-input-voltage applications. The main advantages of the proposed converter are low switching losses, ZVS turn-on, and low voltage stress on MOSFETs. Two capacitors and two halfbridge circuits are connected in series at the high-voltage side to clamp the voltage stress of MOSFETs at one-half of the dc bus voltage. Two center-tapped rectifiers with series connection are adopted to reduce the current rating of the transformer windings and rectifier diodes and to balance the transformer primary currents. Therefore, power can be equally transferred to the output load through two circuit cells. Asymmetric PWM (APWM) is adopted to control four MOSFETs so that the general PWM IC with three isolated gate drives can be used in the proposed circuit. Based on the resonant behavior by the output capacitance of MOSFETs and the resonant inductance, MOSFETs can be turned on at ZVS. Experiments with a 1-kW prototype are presented to verify the effectiveness of the proposed converter. II. C IRCUIT C ONFIGURATION Fig. 1(a) shows the circuit configuration of the stacked half-bridge ZVS dc/dc converter with low voltage stress on MOSFETs and with fewer circuit components to achieve load current sharing. The input dc bus voltage is obtained from a three-phase 380-V ac utility voltage with a diode rectifier. The normal dc input voltage Vin = 480–600 V. Two input voltage supplies and two half-bridge circuits are connected in series at the high-voltage side to limit the voltage stress of MOSFETs at one-half of the dc bus voltage. Therefore, MOSFETs with 500-V voltage rating can be used in this circuit. However, two output inductor currents iLo1 and iLo2 are not balanced if the circuit parameters of the two half-bridge circuits are not identical. To overcome this problem, we add a third half-bridge circuit to share the same power switches as shown in Fig. 1(b). The secondary windings of T1 and T2 are connected in series in order to balance the primary currents, i.e., |iLr1 | = |iLr2 |, and to reduce the secondary winding turns of T1 and T2 . Similarly,

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Fig. 2.

Key waveforms of the proposed converter.

tapped rectifiers are used in the secondary side to have only one diode conduction loss. Since the secondary windings of three circuits are connected in series, two output inductor currents are automatically balanced for high-output-current applications. III. O PERATION P RINCIPLE

Fig. 1. Circuit configuration. (a) Series-connected half-bridge converter with APWM operation. (b) Proposed converter.

the secondary windings of T3 and T4 are also connected in series such that |iLr2 | = |iLr3 |. Thus, three primary currents are balanced, i.e., |iLr1 | = |iLr2 | = |iLr3 |, and two output inductor currents are also identical, i.e., iLo1 = iLo2 . The components of circuit 1 include Vin /2, S1 , S2 , Cr1 , Cr2 , C1 , Lr1 , T1 , D1 , D2 , and Lo1 . Circuit 2 includes the components of Vin /2, S3 , S4 , Cr3 , Cr4 , C3 , Lr3 , T4 , D3 , D4 , and Lo2 . However, the components of the third circuit include Vin , S1 –S4 , Cr1 –Cr4 , C2 , Lr2 , T3 , T4 , D1 –D4 , Lo1 , and Lo2 . Co and Ro denote the output capacitance and load resistance, respectively. C1 –C3 are the dc blocking capacitances. The dc blocking voltages VC1 –VC3 are related to the duty ratio of MOSFETs. Cr1 –Cr4 are the output capacitances of MOSFETs S1 –S4 , respectively. Lr1 –Lr3 are the resonant inductances. Lm1 –Lm4 are the magnetizing inductances of transformers T1 –T4 , respectively. Lo1 and Lo2 are the output inductances. D1 –D4 are the rectifier diodes. The APWM scheme is used to control MOSFETs S1 –S4 . S1 and S4 have the same PWM signals, and S2 and S3 have the same PWM waveforms. However, S1 and S2 are complementary to each other with a dead time to allow ZVS operation. Therefore, the PWM signals of S1 –S4 can be easily generated by an analog PWM IC and three isolated gate drivers. The voltage stress of S1 –S4 is clamped to Vin /2. The center-

Fig. 2 shows the theoretical waveforms of the proposed converter in one switching cycle. The duty cycle of S1 and S4 is δ, and the duty cycle of S2 and S3 is 1 − δ. Before the system analysis, the following assumptions are made: 1) MOSFETs S1 –S4 and diodes D1 –D4 are ideal; 2) Lm1 = Lm2 = Lm3 = Lm4 = Lm , Lr1 = Lr2 = Lr3 Lm , and Lo1 = Lo2 = Lo ; 3) the turn ratio of transformers T1 –T3 is n = np /ns1 = np /ns2 ; 4) Cr1 = Cr2 = Cr3 = Cr4 = Cr and C1 = C2 = C3 = Cc Cr ; and 5) the energy stored in resonant inductors is greater than the energy stored in resonant capacitors such that the ZVS turn-on of all switches can be achieved. Based on the ON / OFF states of S1 –S4 and D1 –D4 , there are eight operation modes in one switching cycle. The equivalent circuits of these eight modes are shown in Fig. 3. Prior to t0 , MOSFETs S2 and S3 and diodes D2 and D4 are conducting. Inductor currents iLr1 > 0, iLr2 < 0, and iLr3 > 0. Mode 1 [t0 ≤ t < t1 ; Fig. 3(a)]: At t0 , S2 and S3 are turned off. Since iLr1 > 0, iLr2 < 0, and iLr3 > 0, Cr1 and Cr4 are discharged and Cr2 and Cr3 are charged in this mode. In this mode, the inductor currents iLr1 –iLr3 are almost constant. This mode ends at t1 when the capacitor voltages vCr1 = VC1 , vCr2 = vCr3 = VC2 /2, and vCr4 = VC3 . Mode 2 [t1 ≤ t < t2 ; Fig. 3(b)]: At t1 , vCr1 = VC1 , vCr2 = vCr3 = VC2 /2, and vCr4 = VC3 . At this instant, the primary and secondary winding voltages of transformers T1 –T4 are all zero voltage. Thus, D1 –D4 are all conducting to commutate the output inductor currents iLo1 and iLo2 , and the output inductor voltages vLo1 = vLo2 = −Vo . Therefore, the inductor currents iLo1 and iLo2 decrease with the slope of −Vo /Lo in this mode. Diode currents iD1 and iD3 increase and diode currents iD2 and iD4 decrease in this time interval. Cr1 and Cr4 are continuously discharged and Cr2 and Cr3 are charged in this mode. If the energy stored in Lr1 and Lr2 is greater than the energy stored in Cr1 and Cr2 , then Cr1 can be discharged to zero voltage. Similarly, Cr4 can be discharged to zero voltage if the energy

LIN AND CHAO: NEW ZVS DC/DC CONVERTER WITH THREE APWM CIRCUITS

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Fig. 3. Operation modes of the proposed converter during one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8.

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stored in Lr2 and Lr3 is greater than the energy stored in Cr3 and Cr4 . This mode ends at t2 when vCr1 = vCr4 = 0. The time interval in modes 1 and 2 can be expressed as Δt02 = t2 − t0 ≈

Cr Vin . iLr1 (t0 ) − iLr2 (t0 )

(1)

The dead time td between switches S1 and S2 must be greater than the time interval Δt02 in order to achieve ZVS turn-on for switches S1 and S4 . Mode 3 [t2 ≤ t < t3 ; Fig. 3(c)]: At t2 , vCr1 = vCr4 = 0. Since iS1 (t2 ) = iLr2 (t2 ) − iLr1 (t2 ) < 0 and iS4 (t2 ) = iLr2 (t2 ) − iLr3 (t2 ) < 0, the antiparallel diodes of S1 and S4 are conducting at t2 . Before iS1 and iS4 are positive, S1 and S4 must be turned on to achieve ZVS. Since diodes D1 –D4 are still conducting, the primary and secondary winding voltages of T1 –T4 are all zero voltage. Thus, the resonant inductor voltages vLr1 = −VC1 < 0, vLr2 = Vin − VC2 > 0, and vLr3 = −VC3 < 0. The inductor current iLr2 increases and iLr1 and iLr3 decrease in this mode. This mode ends at t3 when the diode currents iD2 and iD4 are decreasing to zero. In this mode, the current variations on Lr1 –Lr3 are ΔiLr1 = ΔiLr2 = ΔiLr3 ≈ Io /n. The time interval in this mode is given as Δt23 = t3 − t2 ≈

Lr3 Io Lr1 Io Lr2 Io = = . nVC1 n(Vin − VC2 ) nVC3

(2)

Since VC1 = VC3 = (Vin − VC2 )/2, we can obtain Lr2 = 2Lr1 = 2Lr3 from (2). In this mode, switches S1 and S4 are in the ON state, and the inductor voltages vLo1 = vLo2 = −Vo . No power is transferred from Vin to the output load. Thus, the duty loss in mode 3 is expressed as δloss,3 =

Δt23 Lr1 Io fs ≈ Ts nVC1

(3)

where Ts and fs are the switching period and the switching frequency, respectively. Mode 4 [t3 ≤ t < t4 ; Fig. 3(d)]: At t3 , iD2 = iD4 = 0, and D2 and D4 are turned off. The magnetizing voltages vLm1 ≈ −VC1 < 0, vLm2 = vLm3 ≈ (Vin − VC2 )/2 > 0, and vLm4 ≈ −VC3 < 0. Therefore, the magnetizing currents iLm1 and iLm4 decrease and the magnetizing currents iLm2 and iLm3 increase in this mode. Since VC1 = VC3 , the output inductor voltages vLo1 = vLo2 = (Vin /2 − VC2 /2 + VC1 )/n − Vo > 0 and the inductor currents iLo1 and iLo2 increase in this mode. Power is transferred from Vin to the output load through S1 , C2 , Lr2 , T2 , T3 , S4 , D1 , D3 , Lo1 , and Lo2 . This mode ends at t4 when switches S1 and S4 are turned off. Mode 5 [t4 ≤ t < t5 ; Fig. 3(e)]: At t4 , S1 and S4 are turned off. Since iLr1 (t4 ) − iLr2 (t4 ) < 0 and iLr3 (t4 ) − iLr2 (t4 ) < 0, Cr1 and Cr4 are charged and Cr2 and Cr3 are discharged in this time interval. The inductor currents iLr1 –iLr3 are almost constant in this mode. This mode ends at t5 when vCr1 = VC1 , vCr2 = vCr3 = VC2 /2, and vCr4 = VC3 . Mode 6 [t5 ≤ t < t6 ; Fig. 3(f)]: At t5 , vCr1 = VC1 , vCr2 = vCr3 = VC2 /2, and vCr4 = VC3 . The primary and secondary winding voltages of T1 –T4 are all equal to zero voltage. Thus, diodes D1 –D4 are all conducting, and the output inductor voltages vLo1 = vLo2 = −Vo . The inductor currents iLo1 and

iLo2 decrease in this time interval. Diode currents iD1 and iD3 decrease and iD2 and iD4 increase in mode 6. Cr1 and Cr4 are continuously charged and Cr2 and Cr3 are discharged in this mode. If the energy stored in Lr1 and Lr2 is greater than the energy stored in Cr1 and Cr2 , then Cr2 can be discharged to zero voltage. Similarly, Cr3 can be discharged to zero voltage if the energy stored in Lr2 and Lr3 is greater than the energy stored in Cr3 and Cr4 . This mode ends at t6 when vCr2 = vCr3 = 0. The time interval in modes 5 and 6 can be expressed as Δt46 = t6 − t4 ≈

Cr Vin . iLr2 (t4 ) − iLr1 (t4 )

(4)

In order to turn on S2 and S3 at ZVS, the dead time td between switches S1 and S2 must be greater than the time interval Δt46 . Mode 7 [t6 ≤ t < t7 ; Fig. 3(g)]: At t6 , vCr2 = vCr3 = 0. Since iS2 (t6 ) = iLr1 (t6 ) − iLr2 (t6 ) < 0 and iS3 (t6 ) = iLr3 (t6 ) − iLr2 (t6 ) < 0, the antiparallel diodes of S2 and S3 are conducting at t6 . Before iS2 and iS3 are positive, switches S2 and S3 must be turned on to achieve ZVS. In this mode, D1 –D4 are still in the commutation state. The inductor voltages vLr1 = Vin /2 − VC1 > 0, vLr2 = −VC2 < 0, and vLr3 = Vin /2 − VC3 > 0 such that the inductor currents iLr1 and iLr3 increase and iLr2 decreases in this mode. This mode ends at t7 when diode currents iD1 = iD3 = 0. In this mode, the current variations on Lr1 –Lr3 are ΔiLr1 = ΔiLr2 = ΔiLr3 ≈ Io /n. The time interval in this mode is given as Δt67 = t7 − t6 Lr1 Io ≈ n(Vin /2 − VC1 ) Lr2 Io = nVC2 Lr3 Io . = n(Vin /2 − VC3 )

(5)

In mode 7, switches S2 and S3 are in the ON state, and vLo1 = vLo2 = −Vo . Thus, the duty loss in mode 7 is given as δloss,7 =

Δt67 Lr1 Io fs . ≈ Ts n(Vin /2 − VC1 )

(6)

Mode 8 [t7 ≤ t < t0 + T ; Fig. 3(h)]: At t7 , iD1 = iD3 = 0. The magnetizing voltages vLm1 ≈ Vin /2 − VC1 > 0, vLm2 = vLm3 ≈ −VC2 /2 < 0, and vLm4 ≈ Vin /2 − VC3 > 0. Thus, the magnetizing currents iLm1 and iLm4 increase and the magnetizing currents iLm2 and iLm3 decrease in this mode. The secondary winding voltages of T1 and T2 are positive and negative, respectively, such that D2 is forward biased. The output inductor voltage vLo1 = (Vin /2 − VC1 + VC2 /2)/n − Vo . In the same manner, diode D4 is also forward biased, and the output inductor voltage vLo2 = (Vin /2 − VC3 + VC2 /2)/n − Vo . Power is transferred from Vin to the output load through C1 , Lr1 , T1 , S2 , S3 , C3 , Lr3 , T4 , D2 , D4 , Lo1 , and Lo2 . This mode ends at t0 + Ts when S2 and S3 are turned off. Then, the circuit operations of the proposed converter in one switching cycle are completed.


IV. C IRCUIT C HARACTERISTICS Since the transition intervals at the turn-on and turn-off instants in modes 1, 2, 5, and 6 are much less than the turnon time of S1 –S4 , the effects of modes 1, 2, 5, and 6 are not considered in the following discussion. From the volt–second balance on Lr1 and Lm1 , the average capacitor voltage VC1 is obtained as VC1 =

(1 − δ)Vin 2

(7)

where δ is the duty cycle of S1 and S4 . In the same manner, the average capacitor voltages VC2 and VC3 are obtained as VC2 = δVin

VC3 =

(1 − δ)Vin . 2

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The ripple currents of the magnetizing inductances Lm1 –Lm4 can be expressed as ΔiLm ≈

The average currents of the rectifier diodes D1 –D4 are expressed as ID1,av = ID3,av ≈

≈

=

VC1 n

− (Vo + Vf )

Lo

(δ − δloss,3 )Ts

Vin Ts 2Lr1 Io fs (4δ − 1) δ(1 − δ)(1 − 2δ) + nLo nVin 2 Lr1 Io fs 8 . − 1−δ nVin

(11)

Since the average currents on the capacitors of C1 –C3 are zero, the average magnetizing currents ILm,T 1 –ILm,T 4 are obtained as ILm,T 1 = ILm,T 4 (2δ − 1)Io ≈ (2n) ILm,T 2 = ILm,T 3 (1 − 2δ)Io ≈ (2n) = − ILm,T 1 = − ILm,T 4 .

(12)

(13)

(16)

iS1,peak = iS4,peak ≈ iLr2,max − iLr1,min ≈

ΔiLo1 = ΔiLo2 +

2(1 − δ)Vin . n

The peak currents of switches S1 and S4 at t4 are approximately expressed as

The output voltage Vo is related to δ, Vin , f , Lr1 , and Io . In steady state, the average output inductor currents ILo1 = ILo2 = Io /2. The ripple currents on the output inductors can be expressed as

VC2 2n

(1 − δ)Io . 2 (15)

vD1,stress = vD3,stress 2δVin ≈ n vD2,stress = vD4,stress

(9)

where Vf is the voltage drop on each of diodes D1 –D4 . From (3), (6), and (9), the final output voltage can be expressed as 2Vin 2Lr1 Io fs Vo = (10) − Vf . δ(1 − δ) − n nVin

−

ID2,av = ID4,av ≈

(8)

Vo + Vf −2δ 2 + δ(2 + δloss,3 − δloss,7 ) − δloss,3 = Vin n

Vin 2n

δIo 2

In modes 4 and 8, we can obtain the voltage stresses of rectifier diodes D1 –D4

Based on the key waveforms shown in Fig. 2 and the voltsecond balance on Lo1 at steady state, we can obtain the dc voltage conversion ratio of the proposed converter

≈

VC1 (δ − δloss,3 )Ts δ(1 − δ)Vin Ts Lr1 Io = − . Lm 2Lm nLm (14)

δ(1 − δ)Vin Ts 2(1 − δ)Io Lr1 Io + − n 2Lm nLm Vin Ts 2Lr1 Io fs (4δ − 1) + 2 δ(1 − δ)(1 − 2δ) + n Lo nVin 2 Lr1 Io fs 8 . (17) − 1−δ nVin

Similarly, the peak currents of S2 and S3 at t8 are expressed as iS2,peak = iS3,peak ≈ iLr1,max − iLr2,min ≈

δ(1 − δ)Vin Ts 2δIo Lr1 Io + − n 2Lm nLm Vin Ts 2Lr1 Io fs (4δ − 1) + 2 δ(1 − δ)(1 − 2δ) + n Lo nVin 2 Lr1 Io fs 8 − . (18) 1−δ nVin

The root-mean-square (rms) currents of S1 –S4 can be expressed as √ 2(1 − δ)Io δ (19) iS1,rms = iS4,rms ≈ √n 2δIo 1 − δ . (20) iS2,rms = iS3,rms ≈ n

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The voltage stresses of S1 –S4 are clamped at Vin /2. At t1 in mode 2, the inductor currents iLr1 (t1 )–iLr3 (t1 ) are expressed as iLr1 (t1 ) = iLr3 (t1 ) ≈ iLr1,max δ(1 − δ)Vin Ts δIo Lr1 Io + = − n 2nLm 4Lm 2Lr1 Io fs (4δ − 1) Vin Ts δ(1 − δ)(1 − 2δ) + + 2 2n Lo nVin 2 Lr1 Io fs 8 − (21) 1−δ nVin iLr2 (t1 ) ≈ iLr2,min δ(1 − δ)Vin Ts δIo Lr1 Io − =− + n 2nLm 4Lm 2Lr1 Io fs (4δ − 1) Vin Ts δ(1 − δ)(1 − 2δ) + − 2 2n Lo nVin 2 Lr1 Io fs 8 − . (22) 1−δ nVin Similarly, the inductor currents iLr1 (t5 ) and iLr2 (t5 ) in mode 6 are approximately given as iLr1 (t5 ) = iLr3 (t5 ) ≈ iLr1,min δ(1 − δ)Vin Ts (1 − δ)Io Lr1 Io − =− + n 4Lm 2nLm Vin Ts 2Lr1 Io fs (4δ − 1) − 2 δ(1 − δ)(1 − 2δ) + 2n Lo nVin 2 Lr1 Io fs 8 − (23) 1−δ nVin iLr2 (t5 ) ≈ iLr2,max δ(1 − δ)Vin Ts (1 − δ)Io Lr1 Io + = − n 4L 2nL m m Vin Ts 2Lr1 Io fs (4δ − 1) + 2 δ(1 − δ)(1 − 2δ) + 2n Lo nVin 2 Lr1 Io fs 8 − . (24) 1−δ nVin The ZVS condition of S1 and S4 is expressed in Lr1 i2Lr1 (t1 ) + Lr2 i2Lr2 (t1 ) ≥ (1 − δ)Cr Vin2 /2.

(25)

Similarly, the ZVS condition of S2 and S3 is expressed in Lr1 i2Lr1 (t5 ) + Lr2 i2Lr2 (t5 ) ≥ δCr Vin2 /2.

(26)

V. E XPERIMENTAL R ESULTS Experimental results are provided to demonstrate the effectiveness of the proposed converter. The circuit specifications of a laboratory prototype are Vin = 480–600 V, Vo = 24 V, and Po = 1 kW. The switching frequency fs is 100 kHz. The nominal input voltage Vin,nom is 540 V. The maximum duty cycle of S1 and S4 is selected as 0.45 for the case of

Fig. 4. Measured PWM waveforms of switches S1 –S4 at full load and (a) Vin = 480 V, (b) Vin = 540 V, and (c) Vin = 600 V.

Vin = 480 V and Po = 1 kW. MOSFETs IRFP460 are used for S1 –S4 . The dc blocking capacitances are C1 = C3 = 330 nF and C2 = 660 nF. The resonant inductances are Lr1 = Lr3 = 18 μH and Lr2 = 36 μH. The fast recovery diodes U30D20C are used for D1 –D6 . The turn ratio of transformers T1 –T4 is 34 : 5 : 5. The magnetizing inductance of T1 –T4 is 870 μH. The output capacitance is Co = 6200 μF. The output inductances are Lo1 = Lo2 = 46 μH. The measured PWM signals of S1 –S4 at full load and the different input voltages are shown in Fig. 4. Fig. 5 shows the measured gate voltage, drain voltage, and switch current of switches S1 and S2 at the nominal input voltage Vin = 540 V and 25%- to 100%-load conditions. The drain voltages vS1,ds and vS2,ds have been decreased to zero voltage before switches S1 and S2 are turned on. Thus, S1 and S2 are turned on at ZVS from 25% to 100% load. Since the switches S1 and S4 have the same PWM waveforms and S2 and


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Fig. 6. Measured waveforms of the gate voltage vS1,gs and the inductor currents iLr1 –iLr4 at full load and the nominal input voltage.

Fig. 7. Measured waveforms of vS1,gs , vC1 , vC2 , and vC3 at full-load condition.

Fig. 5. Measured waveforms of the gate voltage, drain voltage, and switch current with the nominal input voltage Vin = 540 V. (a) Switch S1 at 25% load. (b) Switch S2 at 25% load. (c) Switch S1 at 50% load. (d) Switch S2 at 50% load. (e) Switch S1 at 100% load. (f) Switch S2 at 100% load.

S3 have the same PWM waveforms, it is clear that S3 and S4 are also turned on at ZVS. Fig. 6 shows the measured waveforms of the gate voltage vS1,gs and the inductor currents iLr1 –iLr4 at full load and the nominal input voltage. When switch S1 is in the ON state, the inductor currents iLr1 and iLr3 decrease, and iLr2 increases. On the other hand, inductor currents iLr1 and iLr3 increase and iLr2 decreases if switch S1 is in the OFF state. Fig. 7 shows the measured waveforms of vS1,gs , vC1 ,

Fig. 8. Measured waveforms of vS1,gs , iD1 –iD4 , iLo1 , and iLo2 at full-load condition.

vC2 , and vC3 at full-load condition. When switch S1 is on, the inductor currents iLr1 and iLr3 are negative so that capacitor voltages vC1 and vC3 decrease. However, inductor current iLr2 is positive so that capacitor voltage vC2 increases. Fig. 8 shows the measured waveforms of vS1,gs , iD1 –iD4 , iLo1 , and iLo2 at full-load condition. The load current Io is equally supplied by two output inductor currents iLo1 and iLo2 . Fig. 9 shows the measured efficiencies of the proposed converter at different load conditions.

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Fig. 9. Measured efficiencies of the proposed converter for different input voltages and load conditions.

VI. C ONCLUSION This paper has presented a new dc/dc converter with seriesconnected transformers. The main functions of the proposed converter are as follows: 1) ZVS turn-on for all power switches; 2) magnetic flux reset using the APWM scheme; and 3) low voltage stress of power switches with a series half-bridge converter. Two split capacitors and two half-bridge converter circuits connected in series were used at the high-voltage side to limit the voltage stress of power switches at one-half of the input voltage. Thus, the MOSFETs can be used in highinput-voltage applications to achieve high switching frequency, low converter size, and high circuit efficiency. Three APWM converters were used in the primary side, and two centertapped rectifiers with series-connected transformers were used to distribute the load current and balance the primary winding currents for high-output-current applications. The proposed converter can also be operated as an LLC circuit with a 0.5 duty cycle and a variable switching frequency by removing two output inductors. Finally, experiments with a 1-kW prototype were provided to verify the effectiveness of the proposed converter. R EFERENCES [1] H. Ertl, J. W. Kolar, and F. C. Zach, “Analysis of a multilevel multicell switch-mode power amplifier employing the flying-battery concept,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 816–823, Aug. 2002. [2] H. Ertl, J. W. Kolar, and F. C. Zach, “A novel multicell DC–AC converter for applications in renewable energy systems,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1048–1057, Oct. 2002. [3] F. Canales, P. Barbosa, and F. C. Lee, “A zero-voltage and zero-current switching three-level DC/DC converter,” IEEE Trans. Power Electron., vol. 17, no. 6, pp. 898–904, Nov. 2002. [4] W. Chen and X. Ruan, “Zero-voltage-switching PWM hybrid full-bridge three-level converter with secondary-voltage clamping scheme,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 644–654, Feb. 2008. [5] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang, “Three-level LLC series resonant DC/DC converter,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 781–789, Jul. 2005. [6] J. R. Pinheiro and I. Barbi, “The three-level ZVS-PWM DC-to-DC converter,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 486–492, Oct. 1993.

[7] F. Liu, J. Yan, and X. Ruan, “Zero-voltage and zero-current-switching PWM combined three-level DC/DC converter,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1644–1654, May 2010. [8] K. H. Yi and G. W. Moon, “Novel two-phase interleaved LLC seriesresonant converter using a phase of the resonant capacitor,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1815–1819, May 2009. [9] X. Xie, J. Zhang, Z. Chen, Z. Zhao, and Z. Qian, “Analysis and optimization of LLC resonant converter with a novel over-current protection circuit,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 435–443, Mar. 2007. [10] B. R. Lin and S. F. Wu, “ZVS resonant converter with series-connected transformers,” IEEE Trans. Ind. Electron., vol. 58, no. 8, pp. 3547–3554, Aug. 2011. [11] B.-R. Lin and J.-Y. Dong, “ZVS resonant converter with parallel–series transformer connection,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 2972–2979, Jul. 2011. [12] J. Yungtack, M. M. Jovanovic, and Y. M. Chang, “A new ZVS-PWM full-bridge converter,” IEEE Trans. Power Electron., vol. 18, no. 5, pp. 1122–1129, Sep. 2003. [13] Y. Jiang, Z. Chen, and J. Pan, “Zero-voltage switching phase shift fullbridge step-up converter with integrated magnetic structure,” IET Power Electron., vol. 3, no. 5, pp. 732–739, Sep. 2010. [14] B.-R. Lin, J.-Y. Dong, and J.-J. Chen, “Analysis and implementation of a ZVS/ZCS DC–DC switching converter with voltage step-up,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 2962–2971, Jul. 2011.

Bor-Ren Lin (S’91–M’93–SM’02) received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri, Columbia, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. He has authored more than 200 published technical journal papers in the area of power electronics. His main research interests include power factor correction, multilevel converters, active power filters, and soft-switching converters. Dr. Lin is an Associate Editor of the IEEE T RANSACTIONS ON I NDUS TRIAL E LECTRONICS . He was the recipient of the Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He was also the recipient of the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the 2007 Taiwan Power Electronics Conference, and the 2009 IEEE Power Electronics and Drive Systems Conference.

Chia-Hung Chao received the B.S. and M.S. degrees in electrical engineering from the National Yunlin University of Science and Technology, Douliou, Taiwan, in 2011 and 2012, respectively, where he is currently working toward the Ph.D. degree at the Graduate School of Engineering Science and Technology. His research interests include the design and analysis of power factor correction techniques, switching-mode power supplies, and soft-switching converters.