A Phase Shifted PWM Technique for Common- mode ... - IEEE Xplore

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A Phase Shifted PWM Technique for Commonmode Voltage Reduction in Five Level H-bridge Cascaded Inverter N.L.H. Bang, N.V. Nho, Member, IEEE, N.K.T. Tam and N.M. Dung

Abstract-- In electric drive applications, the conventional carrier based and space vector pulse width modulation (PWM) which schemes for two-level inverter topology generate large common-mode voltages, this leads to the phenomenon of bearing current. These current spikes can cause electromagnetic interference (EMI) and reduction in the life expectancy of the motor. Cascade multilevel inverters can reduce voltage stress on power switches; generate smaller common-mode voltages and output voltages with low distortion. Phase shifted PWM is a compatible solution for H-bridge cascaded inverters. In this paper, we will present a simple and flexible phase shifted PWM technique for common-mode voltage reduction of a five level Hbridge cascade inverter topology. Simulation results are presented for validation and comparison with other techniques. Index Terms-- cascade inverter; common-mode voltage; phaseshifted PWM; multilevel inverter; space vector PWM; carrier PWM; Matlab/simulink.

NOMENCLATURE PWM CHB NPC EMI PS APOD

A

Pulse width modulation Cascaded H-bridge Neutral point clamped Electromagnetic interference Phase shifted Alternative phase opposite disposition

proposes a new technique for a 5-level cascaded H-bridge inverter to reduce the common-mode voltage based on phase shifted PWM. The phase shifted PWM can produce even power distribution among the H-bridge cells, naturally balance the capacitor voltage of the cells and mitigate input current harmonics of cascaded H-bridge inverter. Figure 1 shows the 5-level H-bridge cascaded inverter and the voltage from the load neutral point to the common point of the cells equals the common-mode voltage (VNO). In the previous schemes focus on two approach methods: 1) limiting the common-mode voltage in 3 minimum values [1], [5]; 2) eliminating the common-mode voltage completely [2]-[4]. This paper adopts the first approach. Based on the phase shifted PWM, the proposed technique not only reduces the common-mode voltage, but also maintain the even power distribution among the H-bridge cells and the balanced capacitor voltages. This paper divided into 5 sections. Section I is the introduction. Section II presents the conventional phase shifted PWM and the common-mode voltage in this PWM method. All analysis and equations will be described in this section. Section III presents the proposed technique. Section IV presents the simulation results. Section V conclusive the paper. The presented principles simulate in the Matlab / simulink environment software for validation.

I. INTRODUCTION

LTHOUGH, PWM multilevel inverters have reduced the common-mode voltage reference to the traditional twolevel inverters, the PWM schemes solve the common-mode voltage reduction problem has been proposed in order to limit EMI effect, maintain the bearing life, reduce the voltage derivates. These schemes have been presented for two multilevel inverter topologies cascaded H-bridge and neutral point clamped [1]-[5]. These schemes mainly based on space vector PWM and multicarrier level shifted PWM. This paper This work was supported in part by the HCMUT under fund support for master student program TSĐH-2012-ĐĐT-02. N. L. H. Bang is researcher the Power Engineering Research Lab, the Department of Electrical Electronics Engineering, Ho Chi Minh City University of Technology, Viet Nam (e-mail: [email protected]). N. K. T. Tam; N. M. Dung; N. V. Nho are lecturers of the Power Engineering Research Lab, in the Department of Electrical Electronics Engineering, Ho Chi Minh City University of Technology, Viet Nam.

Fig. 1. The five-level cascaded H-bridge inverter.


II. THE COMMON-MODE VOLTAGE OF THE CONVENTIONAL PHASE SHIFTED PWM. A. The principle of common-mode voltage reduction. In the three-phase and three wires power systems, the common-mode voltage can be considered as the voltage from the neutral point of power source to the neutral point of the load. In a system consist of the inverter supply for three-phase, in order to solve the common-mode voltage problem, the common-mode voltage can be seen as the voltage between the DC-link neutral point (in NPC topologies) or the common point of the cells like N point in Fig.1 (CHB topologies) in and the three-phase load neutral point. The voltage VNO in a three-phase 5-level CHB inverter motor system as Fig.1 can be described as the formula below: 1 VNO = (VAO + VBO + VCO ) (1) 3 The output voltage of each phase VXO (X=A or B or C) can be obtained one of five values -2E; -E; 0; E; 2E. As a result, the voltage VNO will be obtained the 13 values from -2E to 2E with two contiguous values separated by an E/3 valuable distance. For a simple analysis, all the voltages can be normalized to unity by divide itself by E value. After that, the 2 value will be added for avoiding computation in the negative numbers. Therefore, the output voltages in unity can be expressed as the switching states SA, SB, SC, where SA,B,C ϵ {4, 3, 2, 1, 0}. The table I show the relationship between switching states of switches in each phase and the output voltage of that phase. TABLE I THE RELATIONSHIP BETWEEN SWITCHING STATES AND THE OUTPUT VOLTAGES

VXO

(S1X,S2X,S3X,S4X)

SX

-2E

(0,0,0,0)

4

-E

(1,0,0,0); (0,1,0,0) (0,0,1,0); (0,0,0,1)

3

(1,1,0,0); (1,0,1,0) 0

(1,0,0,1); (0,1,1,0)

2

(0,1,0,1); (0,0,1,1) E 2E

(1,1,1,0); (1,1,0,1) (1,0,1,1); (0,1,1,1) (1,1,1,1)

1 0

The common-mode voltage can be expressed by the sum of switching states as below: 1 1 VNO = E ( S A + S B + SC - 6) = E.(S S - 6) (2) 3 3 Based on the equation (2), in order to maintain the commonmode voltage in three minimum values {-E/3, 0, E/3}, the sum of switching states ∑S must be limited in three values {5, 6, 7}. In previous papers [1], [6], the authors adopted the space

vector PWM with vectors which have the small sum of switching states ∑S to reduce the common mode voltage. Others used the offset voltages or changing the carrier wave to reduce common mode voltage in carrier based PWM. [3], [5]. This paper analyses all commutation in the phase shifted PWM. Based on those results, we will modify the carrier wave or add the offset voltages to obtain the reduced common-mode voltage. The proposed method still balances the capacitor voltages and distributes the cell powers evenly as the conventional phase shifted carrier PWM. B. The switching sequences in conventional phase shifted PWM. In the phase shifted multicarrier modulation, the m-level inverter requires (m-1) triangular carriers and these carriers have the same frequency, amplitude, but two adjacent carriers have a phase displacement, given by [99]:

(3)

f shifted = 360o / (m - 1)

The establishment of commutations for the five - level cascaded H-bridge inverter with the conventional phase shifted PWM are expressed in Figure 2. 2E vc1

vc2

vc1'

4

vc2' udka

E

3

0

2

-E

-udka 1 0

-2E 0

1

1

1

1

0

0

0

E

0

S1A

0

0

0

E

0

1

1

1

1

0

0

0

0

E

0

E

1

0

0

E

E

S2A' VH1 S3A S4A' VH2 VAO

Fig. 2. Phase-shifted PWM for five-level CHB inverters.

Only phase A are analyzed for simplicity. Phase B, C will be understood similarly. Where, two triangular carriers vc2 are shifted by ϕshifted = 90o from vc1. The other carriers of vc1' and vc2', have opposite values with vc1 and vc2, respectively. Typically, to generate the controlling pulses for switches, the process includes two steps 1a, 1b as follows: 1a) compared vc1, vc2 the triangular carriers with the reference signal udka to create the controlling pulses for the switches S1A, S3A,


respectively; 1b) compared vc1, vc2 the triangular carriers with the opposite reference signal -udka to create the controlling pulses for the switches S2A', S4A', respectively (Figure 2). In order to reduce the reference signal -udka, we will use the opposite triangular carrier vc1' and vc2'. The modified process includes two steps 2a, 2b as follows: 2a) compared vc1, vc2 the triangular carriers with the reference signal udka to create the controlling pulses for the switches S1A, S3A, respectively; 2b) compared vc1', vc2' the opposite triangular carriers with the reference signal udka to create the controlling pulses for the switches S2A, S4A, respectively. The controlling pulses of the switches S1A', S3A, S2A', S4A' are opposite with S1A, S3A,S2A, S4A, respectively and vice versa. In this paper, we use the method 2a and 2b. According to the commutation of the phase shifted PWM, the H-bridge cell voltages and the output voltages corresponding to the different reference signals udkx are illustrated in Figure 3, where x = A, B, C. In figure 3a, 3b, 3c, 3d, the reference signals udkx, after adding the 2 value, belongs to segments [4; 3], [3; 2], [2; 1], [1; 0], respectively. The analysis in the first quarter cycle shows the change of the output voltages. It is different while the reference signals change to the different segments. In a quarter cycle, the output voltage changes in two adjacent values belong to the group {2E, -E, 0, E, 2E} or {4, 3, 2, 1, 0} for the values of switching states. Unless, when udkx = 4 or 3 or 2 or 1 or 0, the output voltages do not change during the sampling cycle. We define VhighX and VlowX are two adjacent values, where VhighX > VlowX. The rules of change are VhighX → VlowX → VhighX in segments [4; 3] and [3; 2]; VlowX → VhighX → VlowX in segments [2; 1] and [1; 0]. It is similar to the APOD level-shifted carriers PWM. C. The common-mode voltage in the conventional phase shifted PWM. 1) Two components of the leg voltages and its sum in threeref phase: The reference three-phase load voltages VXN , X = A, B , C are defined, as follows: ref ìï v AN = Vm cos wt ; ïï ref ïí v = V cos ( wt - 2p 3 ); (4) ïï BNref m ïï vCN = Vm cos ( wt - 4p 3) î

Where, ω = 2 π f and f is the output frequency, Vm = m 4 E ,

3

m is the modulation index. The range 0 ≤m ≤ 1 is called the linear modulation mode and range m ≥ 1 is called overmodulation mode [7]. In this paper, we only analyze in the linear

modulation

with

0

≤

m

≤

3 = 0.866 . 2

ref Therefore, −2 ≤ v XN ≤ 2 . From carrier based PWM with offset

regulation, the reference output voltages or leg voltages consists of the fundamental and an offset component [8]. For the sine PWM, we choose voffset = 0 as: ref ref ref v XO = v XN + voffset = v XN

(5)

In order to analyze easily, in a sampling cycle, the leg voltages

will be split into two components and add a 2 value for avoiding computing in negative numbers, as follows: 4 vc1

vc2

vc1'

vc2'

udkx

4 vc1

3

3

2

2

1

1

0

vc2

vc1'

vc2'

udkx

0 0

E E

0

0

E

2E E

E

0

E

2E

2E

E

0 E

VH1X

0

VH2X

E

VXO

E

E

vc2

0

E

0

E

0

E

0

0

E

VH2X

E

VXO

VH1X

vc1'

3

3

2

2 udkx

1

1

0

0

0

E

3b)

4 vc1

vc2'

0

E

Ts

Ts/4

3a)

4 vc1

0

2E E

Ts

Ts/4

E

vc2

vc1'

vc2'

udkx 0

-E

0

-E

-E

0

-E

0

-E 0

-E

Ts/4

0

-E

0

Ts

3c)

-E

0

0

VH1X -E

VH2X

-E

VXO

0

-E -E

-E

0

-E -2E -E -2E -E

-2E -E

0

Ts/4

0

-E

0

-E

-2E -E

VH1X VH2X VXO

Ts

3d)

Fig. 3. The different reference signals udkx and its output voltages. ref udkx = v XO + 2 = INTX + xX

(6)

Where,

ìï integer(V ref ) , if 0 £ v ref + 2 < 4 XN XO INTX = ïí ref ref ïï integer(VXN if v ) 1, XO + 2 = 4 î ref xX = v XN - INTX

(7)

In the pulse width modulation, the integer components INTX indicate the level of output voltages and the remainders ξX indicate the duty of output voltage in the sample cycle. Fig. 4 shows this relationship in the quarter cycle. The remaining quarter cycles are similar. According to that, two adjacent voltage values are defined as follow: VlowX = INTX (8) VhighX = INTX + 1 We define the sum of the low voltages Slow and the sum of the remainder voltages Sξ of three-phase as follow: Slow = VlowA + VlowB + VlowC (9) Sx = xA + xB + xC


2) The generation to the common-mode voltages: Because the switching sequences of the phase-shifted PWM is VhighX → VlowX → VhighX or VlowX → VhighX → VlowX. Therefore, all the possible switching states ∑S, in three-phase switching sequences, are (Vlow +Vlow + Vlow) or (VlowX + Vlow + Vhigh) or (VlowX + Vhigh + VhighX) or (Vhigh+Vhigh + Vhigh). It equal (Slow) or (Slow+1) or (Slow+2) or (Slow+3) (based on (8)), respectively. When Slow=4 or, Slow=5, we have two cases of the sum of switching states as follows: Slow = 4 Þ S S = 4,5, 6, or 7 (14) Slow = 5 Þ S S = 5, 6, 7, or 8

4 The output voltage level INTx

3 udkx 2

vc2'

1 The duty ξx Ts/4

0

The sampling cycle Ts VhighX

E 0

1

0

1

0

1

0

1

0

The output voltage VXO

1

In the cases ∑S=4 and 8, the common-mode voltage will equals -2E/3 or 2E/3, respectively. The figure 5 shows the common-mode voltage of the five-level H-bridge cascaded in the conventional phase shifted PWM with m = 0.7. Where, the voltages in capacitors are E =100 V.

VlowX

Fig. 4. The relationship of INTX and ξX in phase shifted PWM. Based on the equations (5), (6), (7), (8) and (9), we have: ref ref ref Slow + Sx = v AO + vBO + vCO + 6= 6 (10) 0 £ xX £ 1 Þ 0 £ Sx £ 3

As a result of the equations (9), (10), Sξ can obtain three possible values Sξ = 0, 1, 2 or 3. Therefore, 6, 5, 4, 3 are three possible values of Slow , respectively. In fact, if or Slow 3= and Sξ 3 Slow 6= and Sξ 0 = =

0 VlowA= VlowB= VlowC= 2 and ξ= ξ= ξ= A B C 1 VlowA= VlowB= VlowC= 1 and ξ= ξ= ξ= A B C

(11)

then or (12),

respectively. The case (12) is impossible while voffset =0. The ref ref ref case (11) occurs when v= 0 . In this case, the v= vCO = AO BO common-mode voltage will be zero (13).

Fig. 5. The load phase voltage & common-mode voltage of the conventional phase shifted PWM, m=0.7.

III. THE PROPOSED METHOD FOR COMMON-MODE VOLTAGE REDUCTION

Firstly, the max, mid, and min functions are respectively defined as the greatest, middle, and least values of three variables, xA , xB , xC as follows: ïìï xmax = Max (xA , xB , xC ) ïï (15) í xmid = Mid (xA , xB , xC ) ïï ïïî xmin = Min (xA , xB , xC ) Secondly, in order to avoid the values, we will add an offset voltage into the leg voltage so that one phase does not change the switching states in that sampling cycle. The offset voltages calculation method is presented as equations below: ìï voff = 1- xmax if Slow = 4 ïí (16) ïï voff = - xmin if Slow = 5 î

After adding the offset voltage: 1) in the case Slow=4, the phase of ξmax will not change and equal VhighX during this sampling cycle. Therefore, the available three-phase switching states is (VlowX + Vlow + Vhigh) or (VlowX + Vhigh + VhighX) or (Vhigh+Vhigh + Vhigh) and the sum of switching states will equal 5, 6 or 7, respectively; 2) in the case Slow=5, the phase of ξmin will not change and equal VlowX during this sampling cycle. Therefore, the available three-phase switching states is (VlowX + Vlow + Vlow) or (VlowX + Vlow + VhighX) or (Vlow+Vhigh + Vhigh) and the sum of switching states will equal 5, 6 or 7, respectively. As a result, the cases ∑S=4 and 8 are avoided and the common-mode voltage are maintained in the three values {E/3; 0; E/3}. The scheme of the proposed method is illustrated in Figure 7. IV. THE SIMULATION RESULTS Figure 8 shows the inverter was simulated in the Matlab/ Simulink environment with three phase load R-L in series, R=20 (Ω), L=20 (mH), E = 100 V , output frequency fout =

Fig. 6. The load phase voltage & its FFT analysis of the conventional phase shifted PWM, m=0. 7.

50 (Hz). The frequency of the triangle carrier waveform was selected as 2.5 kHz. Figure 9, 10 shows the load phase voltage, its FFT analysis and reduced common-mode voltage


The reference leg voltage

ref VXO

+

2

udkx

Signal analysis

at m=0.85. Figure 11, 12 shows the load phase voltage and reduced common-mode voltage at m = 0.7 and m = 0.35, respectively. Figure 13, 14 shows the three-phase current and its FFT analysis at m = 0.85. The leg voltage and the line-line voltage is shown in Figure 15 and 16, respectively.

Interger Remainder Comparison  max  mid min 

Computing the sum Slow

Computing the offset voltage

+ -

+

Phase shifted carriers

Fig. 9. The load phase voltage & common-mode voltage of the modified phase shifted PWM, m=0.85.

PWM

Inverter Fig. 7. The proposed method scheme for common-mode voltage reduction.

Fig. 10. The load phase voltage & its FFT analysis of the conventional phase shifted PWM, m=0. 85.

Fig. 8. The five level CHB inverter simulated models in Matlab/Simulink.



Fig. 15. The output voltage VAO voltage of the modified phase shifted PWM, m=0.85.


Fig. 16. The line-line VAB voltage of the modified phase shifted PWM, m=0.85.

V. COLLUSIONS In the paper, a simple method to analysis and control for common-mode voltage reduction has been presented. The common-mode voltage is maintained in three values {-E/3; 0; E/3}. The proposed phase shifted PWM method can be implemented by adding an offset voltage. The number of commutation is reduced, therefore the switching loss is less than. Simulation results have proven the validity of the proposed mathematical model. Fig. 13. m=0.85.

The three-phase current of the modified phase shifted PWM,

ACKNOWLEDGMENT The authors gratefully acknowledge the contributions of Ho Chi Minh City University of Technology for their fund for this project. REFERENCES [1]

[2]

[3] Fig. 14. The three-phase current and its FFT analysis of the modified phase shifted PWM, m=0.85.

[4]

[5]

H.-J. Kim, H.-D. Lee and S.-K. Sul, “A new pwm strategy for commonmode voltage reduction in neutral-point-clamped inverter fed ac motor drives,” IEEE Trans. Ind. Appl., vol. 37, no. 6, pp.1840–1845, Nov.– Dec. 2001. K. R. M. N. Ratnayake and Y. Murai, “A novel pwm scheme to eliminate common-mode voltage in three-level voltage source inverter,” in Proc. 29th Annu. Power Electronics Specialists Conf. (PESC) Rec., May 1998, vol. 1, pp. 269–274. H. Zhang, A. Von Jouanne, S. Dai, A. K. Wallace, and F. Wang, “Multilevel inverter modulation schemes to eliminate common-mode volt-ages,” IEEE Trans. Ind. Appl., vol. 36, no. 6, pp. 1645 –1653, Nov.–Dec.2000. A. von Jouanne, S. Dai, and H. Zhang, “A multilevel inverter approach providing dc-link balancing ride-through enhancement, and commonmode voltage elimination,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 739–745, Aug. 2002. P. C. Loh, D. G. Holmes, Y. Fukuta, and T. A. Lipo, “Reduced common-mode modulation strategies for cascaded multilevel inverters, ”


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IEEE Trans. Ind. Appl., vol. 39, no. 5, pp. 1386 –1395, Sep. –Oct. 2003. A. K. Gupta and A. M. Khambadkone, “A space vector modulation acheme to reduce common mode voltage for cascaded multilevel inverters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1672 – 1681, Sep. 2007. J. Holtz, W. Lotzkat, and A. M. Khambadkone, “On continuous control of PWM inverters in overmodulation range including six-step,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 546 –553, Jul. 1993. J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724 –738, Aug. 2002.

Nguyen Van Nho (M’ 2005) was born in Vietnam, in 1964. He received the M.S and PhD degrees in electrical engineering from University of West Bohemia, Czech Republic's in 1988 and 1991, respectively. Since 1992, he has been with Department of Electrical and Electronics Engineering, Hochiminh City University of Technology, Vietnam, where he is currently an associate professor. He was with KAIST as a postdoc fellow for six months in 2001 and a visiting professor for a year in 2003-2004. His research interests are in the areas of modeling and control of AC motors, active power filters, switching power supply, and PWM techniques for power converters.

Ngo Manh Dung was born in Dong Nai, Viet Nam, on 1856. He received the M.S., and Ph.D. degrees in mechatronics engineering from Pukyong National University, Seoul, South Korea, in 2004 and 2007, respectively. Since 2007, he has been with Department of Electrical and Electronics Engineering, Hochiminh City University of Technology, Vietnam, where he is currently a lecturer. His research interests are in the areas of automation control systems, robotics system, digital control systems for industrial products, and development of DC inverter and its application.

Nguyen Le Huy Bang was born in Tien Giang, Vietnam, in 1986. He received his Bachelor Degree of Electrical Electronics Engineering from Ho Chi Minh City University of Technology, Vietnam in 2010. He is currently working as research assistant at Power Engineering Research Lab (PERL). He is also pursuing the M.E degree in Power Electronics at HCMUT. His research interests include power electronics, power quality, FACTS, digital control systems.

Nguyen Khanh Tu Tam was born in Quang Nam, Vietnam, in 1986. He received his Bachelor and Master Degree of Electrical Electronics Engineering from Ho Chi Minh City University of Technology, Vietnam in 2010 and 2013 respectively. He is currently working as researcher at Power Engineering Research Lab (PERL). His research interests include advanced control of electrical machines, multi-level inverter, active power filters and matrix converter.research assistant at Power Engineering Research Lab (PERL). He is also pursuing the M.E degree in Power Electronics at HCMUT. His research interests include power electronics, power quality, FACTS.